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FPGA and ARM SoC FMC Carrier FASEC
Commit d5590770 authored by Pieter Van Trappen's avatar Pieter Van Trappen
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after synthesis

parent 48a224f0
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FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_4/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd
View file @ d5590770
......@@ -294,8 +294,8 @@ begin
s_data(c_FASEC_BASE+1) <= resize(unsigned(s_ins), g_S00_AXI_DATA_WIDTH);
s_data(c_FASEC_BASE+2) <= resize(unsigned(gem_status_vector_i), g_S00_AXI_DATA_WIDTH);
-- s_data(c_FASEC_BASE+3).data used in p_fasec_dio
s_data(c_FASEC_BASE+6) <= x"DEADBEE1"; -- tcl-script will put unix build time
s_data(c_FASEC_BASE+7) <= x"DEADBEE2"; -- tcl-script will put git commit id
s_data(c_FASEC_BASE+6) <= x"5915BD9E"; -- tcl-script will put unix build time
s_data(c_FASEC_BASE+7) <= x"48a224f0"; -- tcl-script will put git commit id
-- copy in rw data, 'for generate' only possible with constants!
gen_data_readwrite : for i in 0 to c_MEMMAX-1 generate
gen_fasec : if c_FASECMEM(i).ro = '0' generate
......@@ -452,3 +452,4 @@ begin
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready);
end rtl;
FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bxml
View file @ d5590770
......@@ -2,9 +2,9 @@
<Root MajorVersion="0" MinorVersion="33">
<CompositeFile CompositeFileTopName="system_design" CanBeSetAsTop="true" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1494596805"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1494596805"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1494596805"/>
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1494855746"/>
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1494855746"/>
<Generation Name="SIMULATION" State="STALE" Timestamp="1494855746"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="ip/system_design_processing_system7_0_0/system_design_processing_system7_0_0.xci" Type="IP">
<Instance HierarchyPath="processing_system7_0"/>
......
FASEC_prototype.srcs/sources_1/bd/system_design/ui/bd_7f01d80e.ui
View file @ d5590770
......@@ -55,7 +55,7 @@ preplace inst fasec_hwtest_0 -pg 1 -lvl 9 -y 900 -defaultsOSRD
preplace inst axi_dma_0 -pg 1 -lvl 5 -y 370 -defaultsOSRD
preplace inst xadc_axis_fifo_adapter_0 -pg 1 -lvl 4 -y 460 -defaultsOSRD
preplace inst rst_processing_system7_0_100M -pg 1 -lvl 1 -y 470 -defaultsOSRD
preplace inst wrc_1p_kintex7_0 -pg 1 -lvl 9 -y 1470 -defaultsOSRD
preplace inst wrc_1p_kintex7_0 -pg 1 -lvl 9 -y 1480 -defaultsOSRD
preplace inst xadc_wiz_0 -pg 1 -lvl 3 -y 590 -defaultsOSRD
preplace inst xlconcat_0 -pg 1 -lvl 6 -y 430 -defaultsOSRD
preplace inst axi_wb_i2c_master_0 -pg 1 -lvl 3 -y 190 -defaultsOSRD
......@@ -76,39 +76,39 @@ preplace netloc fasec_hwtest_0_dig_outs_i 1 9 1 NJ
preplace netloc gtp_dedicated_clk_n_i_1 1 0 9 NJ 1460 NJ 1460 NJ 1460 NJ 1460 NJ 1460 NJ 1460 NJ 1460 NJ 1460 NJ
preplace netloc wrc_1p_kintex7_0_dac_din_o 1 9 1 NJ
preplace netloc gtp_dedicated_clk_p_i_1 1 0 9 NJ 1440 NJ 1440 NJ 1440 NJ 1440 NJ 1440 NJ 1440 NJ 1440 NJ 1440 NJ
preplace netloc wrc_1p_kintex7_0_clk_rx_rbclk_o 1 8 2 3010 1190 3360
preplace netloc axi_uartlite_0_tx 1 3 7 NJ 600 NJ 600 NJ 600 NJ 600 NJ 600 NJ 600 3390
preplace netloc wrc_1p_kintex7_0_clk_rx_rbclk_o 1 8 2 3030 1190 3390
preplace netloc axi_uartlite_0_tx 1 3 7 NJ 600 NJ 600 NJ 600 NJ 600 NJ 600 NJ 600 3430
preplace netloc dig_in3_n_i_1 1 0 9 NJ 1040 NJ 1040 NJ 1040 NJ 1040 NJ 1040 NJ 1040 NJ 1040 NJ 1040 NJ
preplace netloc FMC1_PRSNTM2C_n_i_1 1 0 9 NJ 660 NJ 660 NJ 290 NJ 220 NJ 220 NJ 230 NJ 230 NJ 230 NJ
preplace netloc dig_in1_i_1 1 0 9 NJ 1000 NJ 1000 NJ 1000 NJ 1000 NJ 1000 NJ 1000 NJ 1000 NJ 1000 NJ
preplace netloc xlconcat_0_dout 1 6 1 2040
preplace netloc fasec_hwtest_0_FMC1_CLK0C2M_P_o 1 9 1 NJ
preplace netloc pb_gp_i_1 1 0 9 NJ 980 NJ 980 NJ 980 NJ 980 NJ 980 NJ 980 NJ 980 NJ 980 2950
preplace netloc pb_gp_i_1 1 0 9 NJ 980 NJ 980 NJ 980 NJ 980 NJ 980 NJ 980 NJ 980 NJ 980 2940
preplace netloc wrc_1p_kintex7_0_dac_sclk_o 1 9 1 NJ
preplace netloc fasec_hwtest_0_led_line_pl_o 1 9 1 NJ
preplace netloc processing_system7_0_axi_periph_M06_AXI 1 2 3 N 330 NJ 330 NJ
preplace netloc axi_wb_i2c_master_2_axi_int_o 1 5 5 1730 300 NJ 270 NJ 270 NJ 270 3450
preplace netloc axi_wb_i2c_master_2_axi_int_o 1 5 5 1730 300 NJ 270 NJ 270 NJ 270 3480
preplace netloc processing_system7_0_DDR 1 7 3 NJ 340 NJ 340 NJ
preplace netloc FMC1_CLK0M2C_N_i_1 1 0 9 NJ 910 NJ 910 NJ 910 NJ 900 NJ 900 NJ 900 NJ 900 NJ 900 NJ
preplace netloc wrc_1p_kintex7_0_dac_cs2_n_o 1 9 1 NJ
preplace netloc axi_interconnect_1_M00_AXI 1 8 1 2900
preplace netloc axi_interconnect_1_M00_AXI 1 8 1 2920
preplace netloc FMC2_CLK0M2C_N_i_1 1 0 9 NJ 640 NJ 640 NJ 440 NJ 580 NJ 580 NJ 580 NJ 580 NJ 580 NJ
preplace netloc processing_system7_0_axi_periph_M05_AXI 1 2 2 N 310 NJ
preplace netloc fasec_hwtest_0_dig_out6_n 1 9 1 NJ
preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 8 20 600 NJ 600 NJ 270 NJ 270 NJ 270 NJ 270 2060 620 2490
preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 8 20 600 NJ 600 NJ 270 NJ 270 NJ 270 NJ 270 2060 630 2490
preplace netloc FMC2_PRSNTM2C_n_i_1 1 0 9 NJ 740 NJ 740 NJ 740 NJ 740 NJ 740 NJ 740 NJ 830 NJ 630 NJ
preplace netloc xadc_wiz_0_M_AXIS 1 3 1 1070
preplace netloc rst_wrc_1p_kintex7_0_62M_interconnect_aresetn 1 7 1 N
preplace netloc processing_system7_0_axi_periph_M02_AXI 1 2 7 NJ 280 NJ 280 NJ 280 NJ 290 NJ 290 NJ 290 2970
preplace netloc processing_system7_0_axi_periph_M02_AXI 1 2 7 NJ 280 NJ 280 NJ 280 NJ 290 NJ 290 NJ 290 2990
preplace netloc xadc_axis_fifo_adapter_0_M_AXIS 1 4 1 1320
preplace netloc processing_system7_0_axi_periph_M07_AXI 1 2 1 700
preplace netloc fasec_hwtest_0_intr_led_o 1 5 5 1730 590 NJ 590 NJ 590 NJ 580 3400
preplace netloc wrc_1p_kintex7_0_gtp0_synced_led_o 1 8 2 3000 570 3440
preplace netloc fasec_hwtest_0_intr_led_o 1 5 5 1730 590 NJ 590 NJ 570 NJ 570 3440
preplace netloc wrc_1p_kintex7_0_gtp0_synced_led_o 1 8 2 3020 580 3480
preplace netloc fasec_hwtest_0_FMC2_CLK0C2M_N_o 1 9 1 NJ
preplace netloc rst_wrc_1p_kintex7_0_62M_peripheral_aresetn 1 7 2 2530 660 2890
preplace netloc rst_wrc_1p_kintex7_0_62M_peripheral_aresetn 1 7 2 2520 660 2910
preplace netloc clk_25m_vcxo_i_1 1 0 9 NJ 1420 NJ 1420 NJ 1420 NJ 1420 NJ 1420 NJ 1420 NJ 1420 NJ 1420 2900
preplace netloc axi_dma_0_M_AXI_S2MM 1 5 1 1670
preplace netloc wrc_1p_kintex7_0_gtp0_link_led_o 1 8 2 3020 620 3420
preplace netloc wrc_1p_kintex7_0_gtp0_link_led_o 1 8 2 3040 630 3460
preplace netloc fasec_hwtest_0_FMC2_CLK0C2M_P_o 1 9 1 NJ
preplace netloc Vaux2_1 1 0 3 NJ 570 NJ 570 NJ
preplace netloc Vp_Vn_1 1 0 3 NJ 560 NJ 560 NJ
......@@ -117,24 +117,24 @@ preplace netloc fasec_hwtest_0_watchdog_pl_o 1 9 1 NJ
preplace netloc processing_system7_0_axi_periph_M01_AXI 1 2 1 730
preplace netloc fasec_hwtest_0_dig_out5_n 1 9 1 NJ
preplace netloc FMC1_CLK0M2C_P_i_1 1 0 9 NJ 920 NJ 920 NJ 920 NJ 920 NJ 920 NJ 920 NJ 920 NJ 920 NJ
preplace netloc wrc_1p_kintex7_0_clk_dmtd_o 1 8 2 3020 1170 3380
preplace netloc wrc_1p_kintex7_0_clk_dmtd_o 1 8 2 3040 1170 3410
preplace netloc Vaux0_1 1 0 3 NJ 360 NJ 540 NJ
preplace netloc Net 1 9 1 NJ
preplace netloc Net10 1 9 1 NJ
preplace netloc wrc_1p_kintex7_0_uart_txd_o 1 3 7 NJ 630 NJ 630 NJ 630 NJ 630 NJ 550 NJ 550 3430
preplace netloc wrc_1p_kintex7_0_uart_txd_o 1 3 7 NJ 620 NJ 620 NJ 620 NJ 620 NJ 610 NJ 610 3420
preplace netloc Net1 1 9 1 NJ
preplace netloc processing_system7_0_FCLK_CLK0 1 0 9 20 350 380 580 740 350 1080 350 1310 240 1710 310 2050 570 2500 480 2990
preplace netloc processing_system7_0_FCLK_CLK0 1 0 9 20 350 380 580 740 350 1080 350 1310 240 1710 310 2050 570 2500 480 3000
preplace netloc Net11 1 9 1 NJ
preplace netloc Net2 1 9 1 NJ
preplace netloc fasec_hwtest_0_intr_o 1 5 5 1670 610 NJ 610 NJ 610 NJ 610 3360
preplace netloc fasec_hwtest_0_intr_o 1 5 5 1670 610 NJ 610 NJ 550 NJ 550 3450
preplace netloc Net3 1 9 1 NJ
preplace netloc rst_processing_system7_0_100M_interconnect_aresetn 1 1 1 370
preplace netloc processing_system7_0_axi_periph_M00_AXI 1 2 7 NJ 260 NJ 260 NJ 260 NJ 280 NJ 280 NJ 280 3000
preplace netloc processing_system7_0_axi_periph_M00_AXI 1 2 7 NJ 260 NJ 260 NJ 260 NJ 280 NJ 280 NJ 280 3040
preplace netloc fasec_hwtest_0_led_line_en_pl_o 1 9 1 NJ
preplace netloc wrc_1p_kintex7_0_s00_axi_aclk_o 1 6 4 2070 850 2550 560 NJ 560 3450
preplace netloc wrc_1p_kintex7_0_s00_axi_aclk_o 1 6 4 2070 850 2550 620 NJ 620 3470
preplace netloc Net4 1 9 1 NJ
preplace netloc Vaux8_1 1 0 3 NJ 590 NJ 590 NJ
preplace netloc wrc_1p_kintex7_0_gtp0_activity_led_o 1 8 2 3010 630 3410
preplace netloc wrc_1p_kintex7_0_gtp0_activity_led_o 1 8 2 3010 1200 3380
preplace netloc Net5 1 9 1 NJ
preplace netloc xadc_wiz_0_ip2intc_irpt 1 3 3 1060 230 NJ 230 NJ
preplace netloc Net6 1 9 1 NJ
......@@ -144,20 +144,20 @@ preplace netloc dig_in2_i_1 1 0 9 NJ 1020 NJ 1020 NJ 1020 NJ 1020 NJ 1020 NJ 102
preplace netloc axi_uartlite_0_interrupt 1 3 3 1060 590 NJ 460 NJ
preplace netloc Vaux10_1 1 0 3 NJ 630 NJ 630 NJ
preplace netloc processing_system7_0_M_AXI_GP0 1 1 7 400 20 NJ 20 NJ 20 NJ 20 NJ 240 NJ 240 2490
preplace netloc wrc_1p_kintex7_0_clk_ref_o 1 8 2 3000 1180 3370
preplace netloc wrc_1p_kintex7_0_clk_ref_o 1 8 2 3020 1180 3400
preplace netloc Vaux1_1 1 0 3 NJ 380 NJ 550 NJ
preplace netloc Vaux9_1 1 0 3 NJ 610 NJ 610 NJ
preplace netloc axi_dma_0_s2mm_introut 1 5 1 1650
preplace netloc processing_system7_0_axi_periph_M04_AXI 1 2 1 710
preplace netloc rst_processing_system7_0_100M_peripheral_aresetn 1 1 8 400 620 750 340 1090 340 1330 250 1690 250 NJ 250 NJ 250 2930
preplace netloc rst_processing_system7_0_100M_peripheral_aresetn 1 1 8 400 620 750 340 1090 340 1330 250 1690 250 NJ 250 NJ 250 2950
preplace netloc FMC2_CLK0M2C_P_i_1 1 0 9 NJ 10 NJ 10 NJ 10 NJ 10 NJ 10 NJ 260 NJ 220 NJ 220 NJ
preplace netloc wrc_1p_kintex7_0_dac_cs1_n_o 1 9 1 NJ
preplace netloc wrc_1p_kintex7_0_gtp_wr 1 9 1 NJ
preplace netloc S00_AXI_1 1 7 1 2520
preplace netloc S00_AXI_1 1 7 1 2530
preplace netloc axi_interconnect_0_M00_AXI 1 6 1 2080
preplace netloc xlconstant_7_dout 1 8 1 NJ
preplace netloc axi_wb_i2c_master_0_axi_int_o 1 3 3 NJ 200 NJ 200 1680
levelinfo -pg 1 -30 200 550 920 1200 1490 1890 2300 2740 3190 3470 -top 0 -bot 1750
levelinfo -pg 1 -30 200 550 920 1200 1490 1890 2300 2740 3210 3510 -top 0 -bot 1760
",
}
{
......
FASEC_prototype.srcs/tcl/set_registers.tcl
View file @ d5590770
......@@ -2,7 +2,7 @@
# in a VHDL file for use during synthesis
# !! FIXME: first remove top if IP updated: $ rm modules/fasec_hwtest/top_mod.vhd.old
# start manually as follows:
# cd /home/pieter/Development/projects/FIDS/FASEC_prototype; source FASEC_prototype.srcs/tcl/set_registers.tcl; reset_run synth_1; launch_runs synth_1 -force -jobs 4; launch_runs impl_1 -to_step write_bitstream -jobs 4
# cd /home/pieter/Development/projects/FIDS/FASEC_prototype; source FASEC_prototype.srcs/tcl/set_registers.tcl
# xilinc tcl info:
# each class can have many properties, to list them:
......
FASEC_prototype.xpr
View file @ d5590770
......@@ -57,6 +57,7 @@
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_interconnect_1_0/system_design_axi_interconnect_1_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="hdl/system_design.vhd"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_wrc_1p_kintex7_0_0/system_design_wrc_1p_kintex7_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="hdl/system_design.hwdef"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_processing_system7_0_0/system_design_processing_system7_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xlconstant_3_2/system_design_xlconstant_3_2.xci"/>
......@@ -65,6 +66,8 @@
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_processing_system7_0_axi_periph_3/system_design_processing_system7_0_axi_periph_3.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xbar_0/system_design_xbar_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="hw_handoff/system_design_bd.tcl"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="hw_handoff/system_design.hwh"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xadc_wiz_0_0/system_design_xadc_wiz_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xadc_axis_fifo_adapter_0_0/system_design_xadc_axis_fifo_adapter_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_dma_0_0/system_design_axi_dma_0_0.xci"/>
......@@ -72,6 +75,10 @@
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xlconcat_0_0/system_design_xlconcat_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_uartlite_0_0/system_design_axi_uartlite_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_auto_pc_2/system_design_auto_pc_2.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="system_design_ooc.xdc"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_auto_pc_0/system_design_auto_pc_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_auto_pc_1/system_design_auto_pc_1.xci"/>
</File>
<File Path="$PSRCDIR/sources_1/bd/system_design/hdl/system_design_wrapper.vhd">
<FileInfo>
......
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