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Pieter Van Trappen authored
No VHDL/IP changes but new SDK workspace (..sdk2) for Periph-test; by adding 2ns analogue delay and some software fixes FASEC-2 finally PASSED EmacPsDmaIntrExample test
fefff94d
No VHDL/IP changes but new SDK workspace (..sdk2) for Periph-test; by adding 2ns analogue delay and some software fixes FASEC-2 finally PASSED EmacPsDmaIntrExample test
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Dhrystone_FASEC | Loading commit data... | |
Hello_FASEC | Loading commit data... | |
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Mem-Test_FASEC | Loading commit data... | |
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