FASEC_prototype.sdk · master · Projects / FPGA and ARM SoC FMC Carrier FASEC

No VHDL/IP changes but new SDK workspace (..sdk2) for Periph-test; by adding 2ns… · fefff94d

Pieter Van Trappen authored Oct 24, 2016

No VHDL/IP changes but new SDK workspace (..sdk2) for Periph-test; by adding 2ns analogue delay and some software fixes FASEC-2 finally PASSED EmacPsDmaIntrExample test

fefff94d

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.metadata		Loading commit data...
.sdk/launch_scripts/xilinx_c-c++_application_(system_debugger)		Loading commit data...
Dhrystone_FASEC		Loading commit data...
Hello_FASEC		Loading commit data...
I2C_tests_FASEC		Loading commit data...
Mem-Test_FASEC		Loading commit data...
Periph-Test_FASEC		Loading commit data...
RemoteSystemsTempFiles		Loading commit data...
standalone_bsp_0		Loading commit data...
system_design_wrapper_hw_platform_0		Loading commit data...
webtalk		Loading commit data...
SDK.log		Loading commit data...
system_design_wrapper.hdf		Loading commit data...