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FMC ADC 100M 14b 4cha - Gateware
Commit 07e7b7de authored by Dimitris Lampridis's avatar Dimitris Lampridis Committed by Dimitris Lampridis
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hdl: work in progress for WRPC integration

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doc/manual/spec/carrier_csr.tex
View file @ 07e7b7de
......@@ -92,18 +92,12 @@ Red LED
@code{DAC_CLR_N}
@tab @code{0} @tab
DAC clear
@item @code{3}
@tab R/W @tab
@code{WRABBIT_EN}
@tab @code{0} @tab
White Rabbit enable
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{led_green} @tab Manual control of the front panel green LED (unused in the fmc-adc application)
@item @code{led_red} @tab Manual control of the front panel red LED (unused in the fmc-adc application)
@item @code{dac_clr_n} @tab Active low clear signal for VCXO DACs
@item @code{wrabbit_en} @tab Enable White Rabbit features
@end multitable
@regsection @code{rst} - Reset Register
Controls software reset of the mezzanine including the ddr interface and the time-tagging core.
......
doc/manual/svec/carrier_csr.tex
View file @ 07e7b7de
......@@ -88,16 +88,10 @@ DDR3 bank 5 calibration status
@code{FP_LEDS_MAN}
@tab @code{0} @tab
Front panel LED manual control
@item @code{16}
@tab R/W @tab
@code{WRABBIT_EN}
@tab @code{0} @tab
White Rabbit enable
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{fp_leds_man} @tab Height front panel LED, two bits per LED.@*00 = OFF@*01 = Green@*10 = Red@*11 = Orange
@item @code{wrabbit_en} @tab Enable White Rabbit features
@end multitable
@regsection @code{rst} - Reset Register
Controls software reset of the mezzanines including the ddr interface and the time-tagging core.
......
vme64x-core @ fa34d06e
Subproject commit b2fc3ce76485404f831d15f7ce31fdde08e234d5
Subproject commit fa34d06e35ca0bfad8eac24aa51713e81639da64
hdl/spec/rtl/carrier_csr.vhd
View file @ 07e7b7de
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Thu Jun 16 16:45:19 2016
-- Created : Mon Feb 26 15:24:45 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
......@@ -40,27 +40,16 @@ architecture syn of carrier_csr is
signal carrier_csr_ctrl_led_green_int : std_logic ;
signal carrier_csr_ctrl_led_red_int : std_logic ;
signal carrier_csr_ctrl_dac_clr_n_int : std_logic ;
signal carrier_csr_ctrl_wrabbit_en_int : std_logic ;
signal carrier_csr_rst_fmc0_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
-- Some internal signals assignments
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
......@@ -72,7 +61,6 @@ begin
carrier_csr_ctrl_led_green_int <= '0';
carrier_csr_ctrl_led_red_int <= '0';
carrier_csr_ctrl_dac_clr_n_int <= '0';
carrier_csr_ctrl_wrabbit_en_int <= '0';
carrier_csr_rst_fmc0_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
......@@ -136,12 +124,11 @@ begin
carrier_csr_ctrl_led_green_int <= wrdata_reg(0);
carrier_csr_ctrl_led_red_int <= wrdata_reg(1);
carrier_csr_ctrl_dac_clr_n_int <= wrdata_reg(2);
carrier_csr_ctrl_wrabbit_en_int <= wrdata_reg(3);
end if;
rddata_reg(0) <= carrier_csr_ctrl_led_green_int;
rddata_reg(1) <= carrier_csr_ctrl_led_red_int;
rddata_reg(2) <= carrier_csr_ctrl_dac_clr_n_int;
rddata_reg(3) <= carrier_csr_ctrl_wrabbit_en_int;
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
......@@ -236,8 +223,6 @@ begin
regs_o.ctrl_led_red_o <= carrier_csr_ctrl_led_red_int;
-- DAC clear
regs_o.ctrl_dac_clr_n_o <= carrier_csr_ctrl_dac_clr_n_int;
-- White Rabbit enable
regs_o.ctrl_wrabbit_en_o <= carrier_csr_ctrl_wrabbit_en_int;
-- State of the reset line
regs_o.rst_fmc0_o <= carrier_csr_rst_fmc0_int;
rwaddr_reg <= wb_adr_i;
......
hdl/spec/rtl/carrier_csr_wbgen2_pkg.vhd
View file @ 07e7b7de
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Thu Jun 16 16:45:19 2016
-- Created : Mon Feb 26 15:24:45 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
......@@ -45,7 +45,6 @@ package carrier_csr_wbgen2_pkg is
ctrl_led_green_o : std_logic;
ctrl_led_red_o : std_logic;
ctrl_dac_clr_n_o : std_logic;
ctrl_wrabbit_en_o : std_logic;
rst_fmc0_o : std_logic;
end record;
......@@ -53,7 +52,6 @@ package carrier_csr_wbgen2_pkg is
ctrl_led_green_o => '0',
ctrl_led_red_o => '0',
ctrl_dac_clr_n_o => '0',
ctrl_wrabbit_en_o => '0',
rst_fmc0_o => '0'
);
function "or" (left, right: t_carrier_csr_in_registers) return t_carrier_csr_in_registers;
......@@ -74,10 +72,10 @@ function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
if x(i) = '1' then
tmp(i):= '1';
else
tmp(i):=x(i);
tmp(i):= '0';
end if;
end loop;
return tmp;
......
hdl/spec/spec_top_fmc_adc_100Ms.ucf
View file @ 07e7b7de
......@@ -602,10 +602,10 @@ INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
TIMESPEC TS_ = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
NET "ddr_clk_buf" TNM_NET = ddr_clk;
NET "sys_clk_62_5" TNM_NET = sys_clk_62_5;
#NET "ddr_clk_buf" TNM_NET = ddr_clk;
#NET "sys_clk_62_5" TNM_NET = sys_clk_62_5;
TIMESPEC TS_sys_to_drr_cross = FROM "sys_clk_62_5" TO "ddr_clk" 16ns DATAPATHONLY;
#TIMESPEC TS_sys_to_drr_cross = FROM "sys_clk_62_5" TO "ddr_clk" 16ns DATAPATHONLY;
#===============================================================================
# False Path
......
hdl/spec/wb_gen/carrier_csr.h
View file @ 07e7b7de
......@@ -3,7 +3,7 @@
* File : carrier_csr.h
* Author : auto-generated by wbgen2 from carrier_csr.wb
* Created : Thu Jun 16 16:45:19 2016
* Created : Mon Feb 26 15:24:45 2018
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
......@@ -80,9 +80,6 @@
/* definitions for field: DAC clear in reg: Control */
#define CARRIER_CSR_CTRL_DAC_CLR_N WBGEN2_GEN_MASK(2, 1)
/* definitions for field: White Rabbit enable in reg: Control */
#define CARRIER_CSR_CTRL_WRABBIT_EN WBGEN2_GEN_MASK(3, 1)
/* definitions for register: Reset Register */
/* definitions for field: State of the reset line in reg: Reset Register */
......
hdl/spec/wb_gen/carrier_csr.htm
View file @ 07e7b7de
......@@ -390,23 +390,6 @@ carrier_csr_ctrl_dac_clr_n_o
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_ctrl_wrabbit_en_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
......@@ -1229,8 +1212,8 @@ CTRL
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
WRABBIT_EN
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
DAC_CLR_N
......@@ -1256,10 +1239,6 @@ LED_RED
DAC_CLR_N
</b>[<i>read/write</i>]: DAC clear
<br>Active low clear signal for VCXO DACs
<li><b>
WRABBIT_EN
</b>[<i>read/write</i>]: White Rabbit enable
<br>Enable White Rabbit features
</ul>
<a name="RST"></a>
<h3><a name="sect_3_4">3.4. Reset Register</a></h3>
......
hdl/spec/wb_gen/carrier_csr.wb
View file @ 07e7b7de
......@@ -112,15 +112,6 @@ peripheral {
access_dev = READ_ONLY;
};
field {
name = "White Rabbit enable";
description = "Enable White Rabbit features";
prefix = "wrabbit_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
......
hdl/svec/rtl/carrier_csr.vhd
View file @ 07e7b7de
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Thu Jun 16 17:11:57 2016
-- Created : Fri Feb 23 15:39:10 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
......@@ -38,28 +38,17 @@ end carrier_csr;
architecture syn of carrier_csr is
signal carrier_csr_ctrl_fp_leds_man_int : std_logic_vector(15 downto 0);
signal carrier_csr_ctrl_wrabbit_en_int : std_logic ;
signal carrier_csr_rst_fmc0_int : std_logic ;
signal carrier_csr_rst_fmc1_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
-- Some internal signals assignments
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
......@@ -69,7 +58,6 @@ begin
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
carrier_csr_ctrl_fp_leds_man_int <= "0000000000000000";
carrier_csr_ctrl_wrabbit_en_int <= '0';
carrier_csr_rst_fmc0_int <= '0';
carrier_csr_rst_fmc1_int <= '0';
elsif rising_edge(clk_sys_i) then
......@@ -132,10 +120,9 @@ begin
when "10" =>
if (wb_we_i = '1') then
carrier_csr_ctrl_fp_leds_man_int <= wrdata_reg(15 downto 0);
carrier_csr_ctrl_wrabbit_en_int <= wrdata_reg(16);
end if;
rddata_reg(15 downto 0) <= carrier_csr_ctrl_fp_leds_man_int;
rddata_reg(16) <= carrier_csr_ctrl_wrabbit_en_int;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
......@@ -215,8 +202,6 @@ begin
-- DDR3 bank 5 calibration status
-- Front panel LED manual control
regs_o.ctrl_fp_leds_man_o <= carrier_csr_ctrl_fp_leds_man_int;
-- White Rabbit enable
regs_o.ctrl_wrabbit_en_o <= carrier_csr_ctrl_wrabbit_en_int;
-- State of the FMC 1 reset line
regs_o.rst_fmc0_o <= carrier_csr_rst_fmc0_int;
-- State of the FMC 2 reset line
......
hdl/svec/rtl/carrier_csr_wbgen2_pkg.vhd
View file @ 07e7b7de
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Thu Jun 16 17:11:57 2016
-- Created : Fri Feb 23 15:39:10 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
......@@ -45,14 +45,12 @@ package carrier_csr_wbgen2_pkg is
type t_carrier_csr_out_registers is record
ctrl_fp_leds_man_o : std_logic_vector(15 downto 0);
ctrl_wrabbit_en_o : std_logic;
rst_fmc0_o : std_logic;
rst_fmc1_o : std_logic;
end record;
constant c_carrier_csr_out_registers_init_value: t_carrier_csr_out_registers := (
ctrl_fp_leds_man_o => (others => '0'),
ctrl_wrabbit_en_o => '0',
rst_fmc0_o => '0',
rst_fmc1_o => '0'
);
......@@ -74,10 +72,10 @@ function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
if x(i) = '1' then
tmp(i):= '1';
else
tmp(i):=x(i);
tmp(i):= '0';
end if;
end loop;
return tmp;
......
hdl/svec/rtl/svec_top_fmc_adc_100Ms.vhd
View file @ 07e7b7de
......@@ -4,17 +4,14 @@
-- URL : http://www.ohwr.org/projects/fmc-adc-100m14b4cha-gw
-------------------------------------------------------------------------------
-- File : svec_top_fmc_adc_100Ms.vhd
-- Author(s) : Matthieu Cattin <matthieu.cattin@cern.ch>
-- : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2013-07-04
-- Last update: 2018-10-24
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Top entity of FMC ADC 100Ms/s design for Simple VME FMC
-- Carrier (SVEC). See also: http://www.ohwr.org/projects/svec
-------------------------------------------------------------------------------
-- Copyright (c) 2013-2016 CERN (BE-CO-HT)
-- Copyright (c) 2013-2018 CERN (BE-CO-HT)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------
......@@ -28,13 +25,6 @@
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2016-04-20 4.1 Dimitrios Lampridis
-- 2014-04-25 4.0 Matthieu Cattin
-- 2014-01-16 3.0 Matthieu Cattin
-- 2013-07-29 1.0 Matthieu Cattin
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
......@@ -50,17 +40,18 @@ use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.fmc_adc_mezzanine_pkg.all;
use work.sdb_meta_pkg.all;
use work.xvme64x_core_pkg.all;
use work.vme64x_pkg.all;
use work.timetag_core_pkg.all;
use work.carrier_csr_wbgen2_pkg.all;
use work.wrcore_pkg.all;
use work.wr_xilinx_pkg.all;
use work.wr_board_pkg.all;
use work.wr_svec_pkg.all;
entity svec_top_fmc_adc_100Ms is
generic(
g_simulation : integer := 0;
g_multishot_ram_size : natural := 8192;
g_CALIB_SOFT_IP : string := "TRUE");
g_CALIB_SOFT_IP : string := "TRUE";
g_wrpc_initf : string := "../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram");
port
(
-- Reset from system fpga
......@@ -103,10 +94,10 @@ entity svec_top_fmc_adc_100Ms is
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_mod_def0_b : in std_logic; -- sfp detect
sfp_mod_def1_b : inout std_logic; -- scl
sfp_mod_def2_b : inout std_logic; -- sda
sfp_rate_select_b : inout std_logic;
sfp_mod_def0_i : in std_logic; -- sfp detect
sfp_mod_def1_b : inout std_logic; -- scl
sfp_mod_def2_b : inout std_logic; -- sda
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic;
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic;
......@@ -121,12 +112,21 @@ entity svec_top_fmc_adc_100Ms is
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
-- GPIO
fp_gpio1_o : out std_logic; -- PPS output
fp_gpio2_o : out std_logic; -- Ref clock div2 output
fp_gpio3_i : in std_logic; -- ext 10MHz clock input
fp_gpio4_i : in std_logic; -- ext PPS intput
fp_term_en_o : out std_logic_vector(4 downto 1);
fp_gpio1_a2b_o : out std_logic;
fp_gpio2_a2b_o : out std_logic;
fp_gpio34_a2b_o : out std_logic;
------------------------------------------
-- VME interface
------------------------------------------
vme_write_n_i : in std_logic;
vme_sysreset_n_i : in std_logic;
--vme_sysclk_i : in std_logic;
vme_retry_oe_o : out std_logic;
vme_retry_n_o : out std_logic;
vme_lword_n_b : inout std_logic;
......@@ -143,8 +143,8 @@ entity svec_top_fmc_adc_100Ms is
vme_as_n_i : in std_logic;
vme_addr_oe_n_o : out std_logic;
vme_addr_dir_o : out std_logic;
vme_irq_n_o : out std_logic_vector(7 downto 1);
vme_ga_i : in std_logic_vector(5 downto 0);
vme_irq_o : out std_logic_vector(7 downto 1);
vme_ga_i : in std_logic_vector(4 downto 0);
vme_data_b : inout std_logic_vector(31 downto 0);
vme_am_i : in std_logic_vector(5 downto 0);
vme_addr_b : inout std_logic_vector(31 downto 1);
......@@ -344,9 +344,6 @@ architecture rtl of svec_top_fmc_adc_100Ms is
xdone_o : out std_logic);
end component;
-- Conversion of g_simulation to boolean
constant c_SIMULATION_BOOL : boolean := f_int2bool(g_simulation);
------------------------------------------------------------------------------
-- SDB crossbar constants declaration
--
......@@ -468,41 +465,47 @@ architecture rtl of svec_top_fmc_adc_100Ms is
-- Number of FMC slots
constant c_NB_FMC_SLOTS : natural := 2;
-- Conversion of g_simulation to string needed for DDR3 controller
function f_int2string (n : natural) return string is
begin
if n = 0 then
return "FALSE";
else
return "TRUE ";
end if;
end;
constant c_SIMULATION_STR : string := f_int2string(g_simulation);
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
-- System clock
signal sys_clk_62_5_buf : std_logic;
signal sys_clk_62_5 : std_logic;
signal sys_clk_125_buf : std_logic;
signal sys_clk_125 : std_logic;
signal sys_clk_pll_locked : std_logic;
signal dmtd_clk_fb : std_logic;
signal clk_125m_pllref : std_logic;
signal clk_125m_pllref_buf : std_logic;
signal clk_125m_gtp : std_logic;
signal clk_20m_vcxo_buf : std_logic;
signal pllout_clk_dmtd : std_logic;
signal clk_dmtd : std_logic;
-- DDR3 clock
signal ddr_clk : std_logic;
signal ddr_clk_buf : std_logic;
-- Reset
signal powerup_arst_n : std_logic := '0';
signal powerup_clk_in : std_logic_vector(2 downto 0);
signal powerup_rst_out : std_logic_vector(2 downto 0);
signal sys_rst_62_5_n : std_logic;
signal sys_rst_125_n : std_logic;
signal sw_rst_fmc0 : std_logic := '1';
signal sw_rst_fmc1 : std_logic := '1';
signal sw_rst_fmc0_sync : std_logic;
signal sw_rst_fmc1_sync : std_logic;
signal fmc0_rst_n : std_logic;
signal fmc1_rst_n : std_logic;
signal ddr_rst_n : std_logic;
-- Clocks and resets
signal clk_sys_62m5 : std_logic;
signal clk_ref_125m : std_logic;
signal clk_ref_div2 : std_logic;
signal sys_clk_pll_locked : std_logic;
signal clk_ext_ref : std_logic;
signal clk_ddr_333m_buf : std_logic;
signal clk_ddr_333m : std_logic;
signal clk_fb_buf : std_logic;
signal clk_fb : std_logic;
signal ddr_clk_pll_locked : std_logic;
signal ddr_clk_pll_rst : std_logic;
signal areset_n : std_logic := '0';
signal rst_sys_62m5_n : std_logic;
signal rst_ref_125m_n : std_logic;
signal rst_ddr_333m_n : std_logic;
signal sw_rst_fmc0 : std_logic := '1';
signal sw_rst_fmc1 : std_logic := '1';
signal sw_rst_ddr0_sync : std_logic;
signal sw_rst_ddr1_sync : std_logic;
signal fmc0_rst_n : std_logic;
signal fmc1_rst_n : std_logic;
signal ddr_arst_n : std_logic;
signal ddr0_rst_n : std_logic;
signal ddr1_rst_n : std_logic;
-- VME
signal vme_data_b_out : std_logic_vector(31 downto 0);
......@@ -510,8 +513,10 @@ architecture rtl of svec_top_fmc_adc_100Ms is
signal vme_lword_n_b_out : std_logic;
signal Vme_data_dir_int : std_logic;
signal vme_addr_dir_int : std_logic;
signal vme_access : std_logic;
signal vme_ga : std_logic_vector(5 downto 0);
signal vme_berr_n : std_logic;
signal vme_irq_n : std_logic_vector(7 downto 1);
signal vme_access : std_logic;
-- Wishbone buse(s) from crossbar master port(s)
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
......@@ -548,18 +553,19 @@ architecture rtl of svec_top_fmc_adc_100Ms is
signal wb_ddr1_adc_ack : std_logic;
signal wb_ddr1_adc_stall : std_logic;
-- Interrupts stuff
signal ddr_wr_fifo_empty : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
signal acq_end_irq_p : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
signal trig_irq_p : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
signal fmc0_trig_irq_led : std_logic;
signal fmc0_acq_end_irq_led : std_logic;
signal irq_to_vme : std_logic;
signal fmc_irq : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
-- Interrupts
signal ddr_wr_fifo_empty : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
signal acq_end_irq_p : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
signal trig_irq_p : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
signal fmc_trig_irq_led : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
signal fmc_acq_end_irq_led : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
signal irq_to_vme : std_logic;
signal fmc_irq : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
-- Front panel LED control
signal svec_led : std_logic_vector(15 downto 0);
signal led_state : std_logic_vector(15 downto 0);
signal led_state_man : std_logic_vector(15 downto 0);
signal led_state_csr : std_logic_vector(15 downto 0);
-- DDR0 (bank 4)
signal ddr0_status : std_logic_vector(31 downto 0);
......@@ -589,21 +595,9 @@ architecture rtl of svec_top_fmc_adc_100Ms is
signal sfp_scl_in : std_logic;
signal sfp_sda_in : std_logic;
-- PHY
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_k : std_logic;
signal phy_tx_disparity : std_logic;
signal phy_tx_enc_err : std_logic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_rx_rbclk : std_logic;
signal phy_rx_k : std_logic;
signal phy_rx_enc_err : std_logic;
signal phy_rx_bitslide : std_logic_vector(3 downto 0);
signal phy_rst : std_logic;
signal phy_loopen : std_logic;
signal phy_loopen_vec : std_logic_vector(2 downto 0);
signal phy_prbs_sel : std_logic_vector(2 downto 0);
signal phy_rdy : std_logic;
-- OneWire
signal onewire_data : std_logic;
signal onewire_oe : std_logic;
-- White Rabbit
signal wrabbit_en : std_logic;
......@@ -611,239 +605,167 @@ architecture rtl of svec_top_fmc_adc_100Ms is
signal wrc_scl_in : std_logic;
signal wrc_sda_out : std_logic;
signal wrc_sda_in : std_logic;
signal wrc_owr_en : std_logic_vector(1 downto 0);
signal wrc_owr_in : std_logic_vector(1 downto 0);
signal pps : std_logic;
signal pps_led : std_logic;
signal pps_ext_in : std_logic;
signal wr_led_act : std_logic;
signal wr_led_link : std_logic;
-- DACs
signal dac_hpll_load_p1 : std_logic;
signal dac_dpll_load_p1 : std_logic;
signal dac_hpll_data : std_logic_vector(15 downto 0);
signal dac_dpll_data : std_logic_vector(15 downto 0);
-- WR PTP core timing interface
signal tm_link_up : std_logic;
signal tm_tai : std_logic_vector(39 downto 0);
signal tm_cycles : std_logic_vector(27 downto 0);
signal tm_time_valid : std_logic;
-- IO for CSR registers
signal csr_regin : t_carrier_csr_in_registers;
signal csr_regout : t_carrier_csr_out_registers;
begin
-- diff clock buffer from 125MHz clock reference
cmp_pll_clk_dsbuf : IBUFGDS
generic map (
DIFF_TERM => TRUE,
IBUF_LOW_PWR => TRUE)
port map (
O => clk_125m_pllref_buf,
I => clk_125m_pllref_p_i,
IB => clk_125m_pllref_n_i);
cmp_pll_clk_buf : BUFG
port map (
O => clk_125m_pllref,
I => clk_125m_pllref_buf);
cmp_clk_vcxo : BUFG
port map (
O => clk_20m_vcxo_buf,
I => clk_20m_vcxo_i);
------------------------------------------------------------------------------
-- 333MHz DDR clock PLL and BUFG based on DCM_SP without feedback (since we
-- are only using the CLKFX output). Input clock is 125MHz ref from WRPC PLLs.
------------------------------------------------------------------------------
cmp_sys_clk_pll : DCM_SP
generic map (
CLKDV_DIVIDE => 2.0, -- CLKDV divide value
-- (1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,7,7.5,8,9,10,11,12,13,14,15,16).
CLKFX_DIVIDE => 3, -- Divide value on CLKFX outputs - D - (1-32)
CLKFX_MULTIPLY => 8, -- Multiply value on CLKFX outputs - M - (2-32)
CLKIN_DIVIDE_BY_2 => FALSE, -- CLKIN divide by two (TRUE/FALSE)
CLKIN_PERIOD => 8.0, -- Input clock period specified in nS
CLKOUT_PHASE_SHIFT => "NONE", -- Output phase shift (NONE, FIXED, VARIABLE)
CLK_FEEDBACK => "1X", -- Feedback source (NONE, 1X, 2X)
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SYSTEM_SYNCHRNOUS or SOURCE_SYNCHRONOUS
DFS_FREQUENCY_MODE => "LOW", -- Unsupported - Do not change value
DLL_FREQUENCY_MODE => "LOW", -- Unsupported - Do not change value
DSS_MODE => "NONE", -- Unsupported - Do not change value
DUTY_CYCLE_CORRECTION => TRUE, -- Unsupported - Do not change value
FACTORY_JF => X"c080", -- Unsupported - Do not change value
PHASE_SHIFT => 0, -- Amount of fixed phase shift (-255 to 255)
STARTUP_WAIT => FALSE -- Delay config DONE until DCM_SP LOCKED (TRUE/FALSE)
CLKFX_DIVIDE => 3,
CLKFX_MULTIPLY => 8,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 8.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DSS_MODE => "NONE",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => X"c080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE
)
port map (
CLK0 => sys_clk_125_buf, -- 1-bit output: 0 degree clock output
CLK180 => open, -- 1-bit output: 180 degree clock output
CLK270 => open, -- 1-bit output: 270 degree clock output
CLK2X => open, -- 1-bit output: 2X clock frequency clock output
CLK2X180 => open, -- 1-bit output: 2X clock frequency, 180 degree clock output
CLK90 => open, -- 1-bit output: 90 degree clock output
CLKDV => sys_clk_62_5_buf, -- 1-bit output: Divided clock output
CLKFX => ddr_clk_buf, -- 1-bit output: Digital Frequency Synthesizer output (DFS)
CLKFX180 => open, -- 1-bit output: 180 degree CLKFX output
LOCKED => sys_clk_pll_locked, -- 1-bit output: DCM_SP Lock Output
PSDONE => open, -- 1-bit output: Phase shift done output
STATUS => open, -- 8-bit output: DCM_SP status output
CLKFB => sys_clk_125, -- 1-bit input: Clock feedback input
CLKIN => clk_125m_pllref, -- 1-bit input: Clock input
DSSEN => '0', -- 1-bit input: Unsupported, specify to GND.
PSCLK => '0', -- 1-bit input: Phase shift clock input
PSEN => '0', -- 1-bit input: Phase shift enable
PSINCDEC => '0', -- 1-bit input: Phase shift increment/decrement input
RST => '0' -- 1-bit input: Active high reset input
);
cmp_dmtd_clk_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50, -- 1GHz
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 16, -- 62.5MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 16,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 16,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 50.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => dmtd_clk_fb,
CLKOUT0 => pllout_clk_dmtd,
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => open,
RST => '0',
CLKFBIN => dmtd_clk_fb,
CLKIN => clk_20m_vcxo_buf);
cmp_clk_62_5_buf : BUFG
CLK0 => clk_fb_buf,
CLKFX => clk_ddr_333m_buf,
CLKFX180 => open,
LOCKED => ddr_clk_pll_locked,
CLKFB => clk_fb,
CLKIN => clk_ref_125m,
DSSEN => '0',
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
RST => ddr_clk_pll_rst);
cmp_fb_clk_buf : BUFG
port map (
O => sys_clk_62_5,
I => sys_clk_62_5_buf);
cmp_clk_125_buf : BUFG
port map (
O => sys_clk_125,
I => sys_clk_125_buf);
O => clk_fb,
I => clk_fb_buf);
cmp_ddr_clk_buf : BUFG
port map (
O => ddr_clk,
I => ddr_clk_buf);
cmp_clk_dmtd_buf : BUFG
port map (
O => clk_dmtd,
I => pllout_clk_dmtd);
U_Dedicated_GTP_Clock_Buffer : IBUFGDS
generic map(
DIFF_TERM => TRUE,
IBUF_LOW_PWR => TRUE,
IOSTANDARD => "DEFAULT")
port map (
O => clk_125m_gtp,
I => clk_125m_gtp_p_i,
IB => clk_125m_gtp_n_i
);
O => clk_ddr_333m,
I => clk_ddr_333m_buf);
------------------------------------------------------------------------------
-- System reset
-- Reset logic
------------------------------------------------------------------------------
-- logic AND of all async reset sources (active low)
powerup_arst_n <= sys_clk_pll_locked and vme_sysreset_n_i and rst_n_i;
areset_n <= vme_sysreset_n_i and rst_n_i;
sys_clk_pll_locked <= '1';
-- concatenation of all clocks required to have synced resets
powerup_clk_in(0) <= sys_clk_62_5;
powerup_clk_in(1) <= sys_clk_125;
powerup_clk_in(2) <= ddr_clk;
-- logic AND of all async reset sources for DDR (active low)
ddr_arst_n <= sys_clk_pll_locked and ddr_clk_pll_locked;
cmp_powerup_reset : gc_reset
generic map (
g_clocks => 3, -- 62.5MHz, 125MHz, 333MHz
g_logdelay => 4, -- 16 clock cycles
g_syncdepth => 3) -- length of sync chains
g_clocks => 1, -- 333MHz
g_logdelay => 4, -- 16 clock cycles
g_syncdepth => 3) -- length of sync chains
port map (
free_clk_i => clk_125m_pllref,
locked_i => powerup_arst_n,
clks_i => powerup_clk_in,
rstn_o => powerup_rst_out);
-- distribution of resets (already synchronized to their clock domains)
sys_rst_62_5_n <= powerup_rst_out(0);
sys_rst_125_n <= powerup_rst_out(1);
ddr_rst_n <= powerup_rst_out(2);
-- sync fmc sw reset to 125MHz
cmp_fmc0_sw_reset_sync : gc_sync_ffs
free_clk_i => clk_ref_125m,
locked_i => ddr_arst_n,
clks_i(0) => clk_ddr_333m,
rstn_o(0) => rst_ddr_333m_n);
-- reset for mezzanines
-- (including soft reset, no need to re-sync from 62.5MHz domain)
fmc0_rst_n <= rst_ref_125m_n and (not sw_rst_fmc0);
fmc1_rst_n <= rst_ref_125m_n and (not sw_rst_fmc1);
-- reset for DDR
-- (including soft reset, with re-sync from 62.5MHz domain)
cmp_ddr0_sw_reset_sync : gc_sync_ffs
port map (
clk_i => sys_clk_125,
rst_n_i => sys_rst_125_n,
clk_i => clk_ddr_333m,
rst_n_i => rst_ddr_333m_n,
data_i => sw_rst_fmc0,
synced_o => sw_rst_fmc0_sync);
synced_o => sw_rst_ddr0_sync);
-- sync fmc sw reset to 125MHz
cmp_fmc1_sw_reset_sync : gc_sync_ffs
cmp_ddr1_sw_reset_sync : gc_sync_ffs
port map (
clk_i => sys_clk_125,
rst_n_i => sys_rst_125_n,
clk_i => clk_ddr_333m,
rst_n_i => rst_ddr_333m_n,
data_i => sw_rst_fmc1,
synced_o => sw_rst_fmc1_sync);
synced_o => sw_rst_ddr1_sync);
-- reset for mezzanine (including soft reset)
fmc0_rst_n <= sys_rst_125_n and (not sw_rst_fmc0_sync);
fmc1_rst_n <= sys_rst_125_n and (not sw_rst_fmc1_sync);
ddr0_rst_n <= rst_ddr_333m_n and (not sw_rst_ddr0_sync);
ddr1_rst_n <= rst_ddr_333m_n and (not sw_rst_ddr0_sync);
------------------------------------------------------------------------------
-- VME interface
------------------------------------------------------------------------------
cmp_vme_core : xvme64x_core
generic map (
g_CLOCK_PERIOD => 16,
g_DECODE_AM => TRUE,
g_USER_CSR_EXT => FALSE,
g_WB_GRANULARITY => BYTE,
g_MANUFACTURER_ID => c_CERN_ID,
g_BOARD_ID => c_SVEC_ID,
g_REVISION_ID => c_SVEC_REVISION_ID,
g_PROGRAM_ID => c_SVEC_PROGRAM_ID)
port map (
clk_i => sys_clk_62_5,
rst_n_i => sys_rst_62_5_n,
VME_AS_n_i => vme_as_n_i,
VME_RST_n_i => sys_rst_62_5_n,
VME_WRITE_n_i => vme_write_n_i,
VME_AM_i => vme_am_i,
VME_DS_n_i => vme_ds_n_i,
VME_GA_i => vme_ga_i,
VME_BERR_o => vme_berr_o,
VME_DTACK_n_o => vme_dtack_n_o,
VME_RETRY_n_o => vme_retry_n_o,
VME_RETRY_OE_o => vme_retry_oe_o,
VME_LWORD_n_b_i => vme_lword_n_b,
VME_LWORD_n_b_o => vme_lword_n_b_out,
VME_ADDR_b_i => vme_addr_b,
VME_DATA_b_o => vme_data_b_out,
VME_ADDR_b_o => vme_addr_b_out,
VME_DATA_b_i => vme_data_b,
VME_IRQ_n_o => vme_irq_n_o,
VME_IACK_n_i => vme_iack_n_i,
VME_IACKIN_n_i => vme_iackin_n_i,
VME_IACKOUT_n_o => vme_iackout_n_o,
VME_DTACK_OE_o => vme_dtack_oe_o,
VME_DATA_DIR_o => vme_data_dir_int,
VME_DATA_OE_N_o => vme_data_oe_n_o,
VME_ADDR_DIR_o => vme_addr_dir_int,
VME_ADDR_OE_N_o => vme_addr_oe_n_o,
master_o => cnx_slave_in(c_WB_MASTER_VME),
master_i => cnx_slave_out(c_WB_MASTER_VME),
irq_i => irq_to_vme
);
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
vme_i.as_n => vme_as_n_i,
vme_i.rst_n => vme_sysreset_n_i,
vme_i.write_n => vme_write_n_i,
vme_i.am => vme_am_i,
vme_i.ds_n => vme_ds_n_i,
vme_i.ga => vme_ga,
vme_i.lword_n => vme_lword_n_b,
vme_i.addr => vme_addr_b,
vme_i.data => vme_data_b,
vme_i.iack_n => vme_iack_n_i,
vme_i.iackin_n => vme_iackin_n_i,
vme_o.berr_n => vme_berr_n,
vme_o.dtack_n => vme_dtack_n_o,
vme_o.retry_n => vme_retry_n_o,
vme_o.retry_oe => vme_retry_oe_o,
vme_o.lword_n => vme_lword_n_b_out,
vme_o.data => vme_data_b_out,
vme_o.addr => vme_addr_b_out,
vme_o.irq_n => vme_irq_n,
vme_o.iackout_n => vme_iackout_n_o,
vme_o.dtack_oe => vme_dtack_oe_o,
vme_o.data_dir => vme_data_dir_int,
vme_o.data_oe_n => vme_data_oe_n_o,
vme_o.addr_dir => vme_addr_dir_int,
vme_o.addr_oe_n => vme_addr_oe_n_o,
wb_o => cnx_slave_in(c_WB_MASTER_VME),
wb_i.ack => cnx_slave_out(c_WB_MASTER_VME).ack,
wb_i.err => cnx_slave_out(c_WB_MASTER_VME).err,
wb_i.rty => cnx_slave_out(c_WB_MASTER_VME).rty,
wb_i.stall => cnx_slave_out(c_WB_MASTER_VME).stall,
wb_i.int => irq_to_vme,
wb_i.dat => cnx_slave_out(c_WB_MASTER_VME).dat);
vme_ga <= vme_gap_i & vme_ga_i;
vme_berr_o <= not vme_berr_n;
vme_irq_o <= not vme_irq_n;
-- VME tri-state buffers
vme_data_b <= vme_data_b_out when vme_data_dir_int = '1' else (others => 'Z');
......@@ -854,7 +776,7 @@ begin
vme_data_dir_o <= vme_data_dir_int;
------------------------------------------------------------------------------
-- CSR wishbone crossbar
-- Primary wishbone crossbar
------------------------------------------------------------------------------
cmp_sdb_crossbar : xwb_sdb_crossbar
generic map (
......@@ -865,16 +787,15 @@ begin
g_layout => c_INTERCONNECT_LAYOUT,
g_sdb_addr => c_SDB_ADDRESS)
port map (
clk_sys_i => sys_clk_62_5,
rst_n_i => sys_rst_62_5_n,
clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
slave_i => cnx_slave_in,
slave_o => cnx_slave_out,
master_i => cnx_master_in,
master_o => cnx_master_out);
-------------------------------------------------------------------------------
-- White Rabbit Core + PHY
-- White Rabbit Core (SVEC board package)
-------------------------------------------------------------------------------
-- Tristates for Carrier EEPROM
......@@ -889,174 +810,70 @@ begin
sfp_scl_in <= sfp_mod_def1_b;
sfp_sda_in <= sfp_mod_def2_b;
carrier_onewire_b <= '0' when wrc_owr_en(0) = '1' else 'Z';
wrc_owr_in(0) <= carrier_onewire_b;
wrc_owr_in(1) <= '1';
carrier_onewire_b <= '0' when onewire_oe = '1' else 'Z';
onewire_data <= carrier_onewire_b;
---------------------
U_GTP : wr_gtp_phy_spartan6
generic map (
g_simulation => g_simulation,
g_enable_ch0 => 0,
g_enable_ch1 => 1)
port map (
gtp_clk_i => clk_125m_gtp,
ch0_ref_clk_i => clk_125m_pllref,
ch0_tx_data_i => x"00",
ch0_tx_k_i => '0',
ch0_tx_disparity_o => open,
ch0_tx_enc_err_o => open,
ch0_rx_rbclk_o => open,
ch0_rx_data_o => open,
ch0_rx_k_o => open,
ch0_rx_enc_err_o => open,
ch0_rx_bitslide_o => open,
ch0_rst_i => '1',
ch0_loopen_i => '0',
ch1_ref_clk_i => clk_125m_pllref,
ch1_tx_data_i => phy_tx_data,
ch1_tx_k_i => phy_tx_k,
ch1_tx_disparity_o => phy_tx_disparity,
ch1_tx_enc_err_o => phy_tx_enc_err,
ch1_rx_data_o => phy_rx_data,
ch1_rx_rbclk_o => phy_rx_rbclk,
ch1_rx_k_o => phy_rx_k,
ch1_rx_enc_err_o => phy_rx_enc_err,
ch1_rx_bitslide_o => phy_rx_bitslide,
ch1_rst_i => phy_rst,
ch1_loopen_i => phy_loopen,
ch1_loopen_vec_i => phy_loopen_vec,
ch1_tx_prbs_sel_i => phy_prbs_sel,
ch1_rdy_o => phy_rdy,
pad_txn0_o => open,
pad_txp0_o => open,
pad_rxn0_i => '0',
pad_rxp0_i => '0',
pad_txn1_o => sfp_txn_o,
pad_txp1_o => sfp_txp_o,
pad_rxn1_i => sfp_rxn_i,
pad_rxp1_i => sfp_rxp_i);
U_DAC_Helper : spec_serial_dac
cmp_xwrc_board_svec : xwrc_board_svec
generic map (
g_num_data_bits => 16,
g_num_extra_bits => 8,
g_num_cs_select => 1)
g_simulation => g_simulation,
g_with_external_clock_input => TRUE,
g_dpram_initf => g_wrpc_initf,
g_fabric_iface => PLAIN)
port map (
clk_i => sys_clk_62_5,
rst_n_i => sys_rst_62_5_n,
value_i => dac_hpll_data,
cs_sel_i => "1",
load_i => dac_hpll_load_p1,
sclk_divsel_i => "010",
dac_cs_n_o(0) => pll20dac_sync_n_o,
dac_sclk_o => pll20dac_sclk_o,
dac_sdata_o => pll20dac_din_o,
xdone_o => open);
U_DAC_Main : spec_serial_dac
generic map (
g_num_data_bits => 16,
g_num_extra_bits => 8,
g_num_cs_select => 1)
port map (
clk_i => sys_clk_62_5,
rst_n_i => sys_rst_62_5_n,
value_i => dac_dpll_data,
cs_sel_i => "1",
load_i => dac_dpll_load_p1,
sclk_divsel_i => "010",
dac_cs_n_o(0) => pll25dac_sync_n_o,
dac_sclk_o => pll25dac_sclk_o,
dac_sdata_o => pll25dac_din_o,
xdone_o => open);
sfp_tx_disable_o <= '0';
U_WR_CORE : xwr_core
generic map (
g_simulation => g_simulation,
g_dpram_initf => "../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram")
port map (
clk_sys_i => sys_clk_62_5,
clk_dmtd_i => clk_dmtd,
clk_ref_i => clk_125m_pllref,
rst_n_i => sys_rst_62_5_n,
--wrf_snk_i => wrcore_snk_in,
--wrf_snk_o => wrcore_snk_out,
--wrf_src_i => wrcore_src_in,
--wrf_src_o => wrcore_src_out,
dac_hpll_load_p1_o => dac_hpll_load_p1,
dac_hpll_data_o => dac_hpll_data,
dac_dpll_load_p1_o => dac_dpll_load_p1,
dac_dpll_data_o => dac_dpll_data,
phy_ref_clk_i => clk_125m_pllref,
phy_tx_data_o => phy_tx_data,
phy_tx_k_o(0) => phy_tx_k,
phy_tx_disparity_i => phy_tx_disparity,
phy_tx_enc_err_i => phy_tx_enc_err,
phy_rx_data_i => phy_rx_data,
phy_rx_rbclk_i => phy_rx_rbclk,
phy_rx_k_i(0) => phy_rx_k,
phy_rx_enc_err_i => phy_rx_enc_err,
phy_rx_bitslide_i => phy_rx_bitslide,
phy_rst_o => phy_rst,
phy_loopen_o => phy_loopen,
phy_loopen_vec_o => phy_loopen_vec,
phy_tx_prbs_sel_o => phy_prbs_sel,
phy_rdy_i => phy_rdy,
-- phy_loopen_o => phy_loopen,
led_act_o => wr_led_act,
led_link_o => wr_led_link,
scl_o => wrc_scl_out,
scl_i => wrc_scl_in,
sda_o => wrc_sda_out,
sda_i => wrc_sda_in,
sfp_scl_o => sfp_scl_out,
sfp_scl_i => sfp_scl_in,
sfp_sda_o => sfp_sda_out,
sfp_sda_i => sfp_sda_in,
sfp_det_i => sfp_mod_def0_b,
-- SPI flash is connected to SFPGA, and routed
-- to AFPGA once boot process is complete
spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
owr_en_o => wrc_owr_en,
owr_i => wrc_owr_in,
slave_i => cnx_master_out(c_WB_SLAVE_WR_CORE),
slave_o => cnx_master_in(c_WB_SLAVE_WR_CORE),
tm_dac_value_o => open,
tm_dac_wr_o => open,
tm_clk_aux_lock_en_i => (others => '0'),
tm_clk_aux_locked_o => open,
tm_link_up_o => tm_link_up,
tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_tai,
tm_cycles_o => tm_cycles,
btn1_i => '0',
btn2_i => '0',
pps_p_o => open
);
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
clk_10m_ext_i => clk_ext_ref,
areset_n_i => areset_n,
clk_sys_62m5_o => clk_sys_62m5,
clk_ref_125m_o => clk_ref_125m,
rst_sys_62m5_n_o => rst_sys_62m5_n,
rst_ref_125m_n_o => rst_ref_125m_n,
pll20dac_din_o => pll20dac_din_o,
pll20dac_sclk_o => pll20dac_sclk_o,
pll20dac_sync_n_o => pll20dac_sync_n_o,
pll25dac_din_o => pll25dac_din_o,
pll25dac_sclk_o => pll25dac_sclk_o,
pll25dac_sync_n_o => pll25dac_sync_n_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_det_i => sfp_mod_def0_i,
sfp_sda_i => sfp_sda_in,
sfp_sda_o => sfp_sda_out,
sfp_scl_i => sfp_scl_in,
sfp_scl_o => sfp_scl_out,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
eeprom_sda_i => wrc_sda_in,
eeprom_sda_o => wrc_sda_out,
eeprom_scl_i => wrc_scl_in,
eeprom_scl_o => wrc_scl_out,
onewire_i => onewire_data,
onewire_oen_o => onewire_oe,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
wb_slave_o => cnx_master_in(c_WB_SLAVE_WR_CORE),
wb_slave_i => cnx_master_out(c_WB_SLAVE_WR_CORE),
tm_link_up_o => tm_link_up,
tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_tai,
tm_cycles_o => tm_cycles,
pps_ext_i => pps_ext_in,
pps_p_o => pps,
pps_led_o => pps_led,
led_link_o => wr_led_link,
led_act_o => wr_led_act,
link_ok_o => wrabbit_en);
------------------------------------------------------------------------------
-- Carrier CSR
......@@ -1066,8 +883,8 @@ begin
------------------------------------------------------------------------------
cmp_carrier_csr : carrier_csr
port map(
rst_n_i => sys_rst_62_5_n,
clk_sys_i => sys_clk_62_5,
rst_n_i => rst_sys_62m5_n,
clk_sys_i => clk_sys_62m5,
wb_adr_i => cnx_master_out(c_WB_SLAVE_SVEC_CSR).adr(3 downto 2), -- cnx_master_out.adr is byte address
wb_dat_i => cnx_master_out(c_WB_SLAVE_SVEC_CSR).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_SVEC_CSR).dat,
......@@ -1089,8 +906,7 @@ begin
csr_regin.stat_ddr0_cal_done_i <= ddr0_calib_done;
csr_regin.stat_ddr1_cal_done_i <= ddr1_calib_done;
led_state_man <= csr_regout.ctrl_fp_leds_man_o;
wrabbit_en <= csr_regout.ctrl_wrabbit_en_o;
led_state_csr <= csr_regout.ctrl_fp_leds_man_o;
sw_rst_fmc0 <= csr_regout.rst_fmc0_o;
sw_rst_fmc1 <= csr_regout.rst_fmc1_o;
......@@ -1110,8 +926,8 @@ begin
g_num_interrupts => 2,
g_init_vectors => c_VIC_VECTOR_TABLE)
port map (
clk_sys_i => sys_clk_62_5,
rst_n_i => sys_rst_62_5_n,
clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
slave_i => cnx_master_out(c_WB_SLAVE_VIC),
slave_o => cnx_master_in(c_WB_SLAVE_VIC),
irqs_i(0) => fmc_irq(0),
......@@ -1132,12 +948,12 @@ begin
g_size => 16
)
port map(
slave_clk_i => sys_clk_62_5,
slave_rst_n_i => sys_rst_62_5_n,
slave_clk_i => clk_sys_62m5,
slave_rst_n_i => rst_sys_62m5_n,
slave_i => cnx_master_out(c_WB_SLAVE_FMC0_ADC),
slave_o => cnx_master_in(c_WB_SLAVE_FMC0_ADC),
master_clk_i => sys_clk_125,
master_rst_n_i => sys_rst_125_n,
master_clk_i => clk_ref_125m,
master_rst_n_i => fmc0_rst_n,
master_i => cnx_fmc0_sync_master_in,
master_o => cnx_fmc0_sync_master_out
);
......@@ -1148,7 +964,7 @@ begin
g_carrier_type => "SVEC"
)
port map(
sys_clk_i => sys_clk_125,
sys_clk_i => clk_ref_125m,
sys_rst_n_i => fmc0_rst_n,
wb_csr_adr_i => cnx_fmc0_sync_master_out.adr,
......@@ -1161,7 +977,7 @@ begin
wb_csr_ack_o => cnx_fmc0_sync_master_in.ack,
wb_csr_stall_o => cnx_fmc0_sync_master_in.stall,
wb_ddr_clk_i => sys_clk_125,
wb_ddr_clk_i => clk_ref_125m,
wb_ddr_adr_o => wb_ddr0_adc_adr,
wb_ddr_dat_o => wb_ddr0_adc_dat_o,
wb_ddr_sel_o => wb_ddr0_adc_sel,
......@@ -1241,12 +1057,12 @@ begin
g_size => 16
)
port map(
slave_clk_i => sys_clk_62_5,
slave_rst_n_i => sys_rst_62_5_n,
slave_clk_i => clk_sys_62m5,
slave_rst_n_i => rst_sys_62m5_n,
slave_i => cnx_master_out(c_WB_SLAVE_FMC1_ADC),
slave_o => cnx_master_in(c_WB_SLAVE_FMC1_ADC),
master_clk_i => sys_clk_125,
master_rst_n_i => sys_rst_125_n,
master_clk_i => clk_ref_125m,
master_rst_n_i => fmc1_rst_n,
master_i => cnx_fmc1_sync_master_in,
master_o => cnx_fmc1_sync_master_out
);
......@@ -1257,7 +1073,7 @@ begin
g_carrier_type => "SVEC"
)
port map(
sys_clk_i => sys_clk_125,
sys_clk_i => clk_ref_125m,
sys_rst_n_i => fmc1_rst_n,
wb_csr_adr_i => cnx_fmc1_sync_master_out.adr,
......@@ -1270,7 +1086,7 @@ begin
wb_csr_ack_o => cnx_fmc1_sync_master_in.ack,
wb_csr_stall_o => cnx_fmc1_sync_master_in.stall,
wb_ddr_clk_i => sys_clk_125,
wb_ddr_clk_i => clk_ref_125m,
wb_ddr_adr_o => wb_ddr1_adc_adr,
wb_ddr_dat_o => wb_ddr1_adc_dat_o,
wb_ddr_sel_o => wb_ddr1_adc_sel,
......@@ -1343,7 +1159,7 @@ begin
generic map(
g_BANK_PORT_SELECT => "SVEC_BANK4_64B_32B",
g_MEMCLK_PERIOD => 3000,
g_SIMULATION => c_SIMULATION_BOOL,
g_SIMULATION => c_SIMULATION_STR,
g_CALIB_SOFT_IP => g_CALIB_SOFT_IP,
g_P0_MASK_SIZE => 8,
g_P0_DATA_PORT_SIZE => 64,
......@@ -1352,8 +1168,8 @@ begin
g_P1_DATA_PORT_SIZE => 32,
g_P1_BYTE_ADDR_WIDTH => 30)
port map (
clk_i => ddr_clk,
rst_n_i => ddr_rst_n,
clk_i => clk_ddr_333m,
rst_n_i => ddr0_rst_n,
status_o => ddr0_status,
......@@ -1377,8 +1193,8 @@ begin
ddr3_rzq_b => ddr0_rzq_b,
ddr3_zio_b => ddr0_zio_b,
wb0_rst_n_i => sys_rst_125_n,
wb0_clk_i => sys_clk_125,
wb0_rst_n_i => rst_ref_125m_n,
wb0_clk_i => clk_ref_125m,
wb0_sel_i => wb_ddr0_adc_sel,
wb0_cyc_i => wb_ddr0_adc_cyc,
wb0_stb_i => wb_ddr0_adc_stb,
......@@ -1402,8 +1218,8 @@ begin
p0_wr_underrun_o => open,
p0_wr_error_o => open,
wb1_rst_n_i => sys_rst_62_5_n,
wb1_clk_i => sys_clk_62_5,
wb1_rst_n_i => rst_sys_62m5_n,
wb1_clk_i => clk_sys_62m5,
wb1_sel_i => cnx_master_out(c_WB_SLAVE_FMC0_DDR_DAT).sel,
wb1_cyc_i => cnx_master_out(c_WB_SLAVE_FMC0_DDR_DAT).cyc,
wb1_stb_i => cnx_master_out(c_WB_SLAVE_FMC0_DDR_DAT).stb,
......@@ -1437,10 +1253,10 @@ begin
-- The counter is incremented on the falling edge of cyc. This is because the ddr controller
-- samples the address on (cyc_re and stb)+1
p_ddr0_dat_cyc : process (sys_clk_62_5)
p_ddr0_dat_cyc : process (clk_sys_62m5)
begin
if rising_edge(sys_clk_62_5) then
if (sys_rst_62_5_n = '0' or sw_rst_fmc0 = '1') then
if rising_edge(clk_sys_62m5) then
if (rst_sys_62m5_n = '0' or sw_rst_fmc0 = '1') then
ddr0_dat_cyc_d <= '0';
else
ddr0_dat_cyc_d <= cnx_master_out(c_WB_SLAVE_FMC0_DDR_DAT).cyc;
......@@ -1451,10 +1267,10 @@ begin
ddr0_addr_cnt_en <= not(cnx_master_out(c_WB_SLAVE_FMC0_DDR_DAT).cyc) and ddr0_dat_cyc_d;
-- address counter
p_ddr0_addr_cnt : process (sys_clk_62_5)
p_ddr0_addr_cnt : process (clk_sys_62m5)
begin
if rising_edge(sys_clk_62_5) then
if (sys_rst_62_5_n = '0' or sw_rst_fmc0 = '1') then
if rising_edge(clk_sys_62m5) then
if (rst_sys_62m5_n = '0' or sw_rst_fmc0 = '1') then
ddr0_addr_cnt <= (others => '0');
elsif (cnx_master_out(c_WB_SLAVE_FMC0_DDR_ADR).we = '1' and
cnx_master_out(c_WB_SLAVE_FMC0_DDR_ADR).stb = '1' and
......@@ -1467,10 +1283,10 @@ begin
end process p_ddr0_addr_cnt;
-- ack generation
p_ddr0_addr_ack : process (sys_clk_62_5)
p_ddr0_addr_ack : process (clk_sys_62m5)
begin
if rising_edge(sys_clk_62_5) then
if (sys_rst_62_5_n = '0' or sw_rst_fmc0 = '1') then
if rising_edge(clk_sys_62m5) then
if (rst_sys_62m5_n = '0' or sw_rst_fmc0 = '1') then
cnx_master_in(c_WB_SLAVE_FMC0_DDR_ADR).ack <= '0';
elsif (cnx_master_out(c_WB_SLAVE_FMC0_DDR_ADR).stb = '1' and
cnx_master_out(c_WB_SLAVE_FMC0_DDR_ADR).cyc = '1') then
......@@ -1485,6 +1301,9 @@ begin
cnx_master_in(c_WB_SLAVE_FMC0_DDR_ADR).dat <= std_logic_vector(ddr0_addr_cnt);
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_FMC0_DDR_DAT).err <= '0';
cnx_master_in(c_WB_SLAVE_FMC0_DDR_DAT).rty <= '0';
cnx_master_in(c_WB_SLAVE_FMC0_DDR_DAT).int <= '0';
cnx_master_in(c_WB_SLAVE_FMC0_DDR_ADR).err <= '0';
cnx_master_in(c_WB_SLAVE_FMC0_DDR_ADR).rty <= '0';
cnx_master_in(c_WB_SLAVE_FMC0_DDR_ADR).stall <= '0';
......@@ -1497,7 +1316,7 @@ begin
generic map(
g_BANK_PORT_SELECT => "SVEC_BANK5_64B_32B",
g_MEMCLK_PERIOD => 3000,
g_SIMULATION => c_SIMULATION_BOOL,
g_SIMULATION => c_SIMULATION_STR,
g_CALIB_SOFT_IP => g_CALIB_SOFT_IP,
g_P0_MASK_SIZE => 8,
g_P0_DATA_PORT_SIZE => 64,
......@@ -1506,8 +1325,8 @@ begin
g_P1_DATA_PORT_SIZE => 32,
g_P1_BYTE_ADDR_WIDTH => 30)
port map (
clk_i => ddr_clk,
rst_n_i => ddr_rst_n,
clk_i => clk_ddr_333m,
rst_n_i => ddr1_rst_n,
status_o => ddr1_status,
......@@ -1531,8 +1350,8 @@ begin
ddr3_rzq_b => ddr1_rzq_b,
ddr3_zio_b => ddr1_zio_b,
wb0_rst_n_i => sys_rst_125_n,
wb0_clk_i => sys_clk_125,
wb0_rst_n_i => rst_ref_125m_n,
wb0_clk_i => clk_ref_125m,
wb0_sel_i => wb_ddr1_adc_sel,
wb0_cyc_i => wb_ddr1_adc_cyc,
wb0_stb_i => wb_ddr1_adc_stb,
......@@ -1556,8 +1375,8 @@ begin
p0_wr_underrun_o => open,
p0_wr_error_o => open,
wb1_rst_n_i => sys_rst_62_5_n,
wb1_clk_i => sys_clk_62_5,
wb1_rst_n_i => rst_sys_62m5_n,
wb1_clk_i => clk_sys_62m5,
wb1_sel_i => cnx_master_out(c_WB_SLAVE_FMC1_DDR_DAT).sel,
wb1_cyc_i => cnx_master_out(c_WB_SLAVE_FMC1_DDR_DAT).cyc,
wb1_stb_i => cnx_master_out(c_WB_SLAVE_FMC1_DDR_DAT).stb,
......@@ -1591,10 +1410,10 @@ begin
-- The counter is incremented on the falling edge of cyc. This is because the ddr controller
-- samples the address on (cyc_re and stb)+1
p_ddr1_dat_cyc : process (sys_clk_62_5)
p_ddr1_dat_cyc : process (clk_sys_62m5)
begin
if rising_edge(sys_clk_62_5) then
if (sys_rst_62_5_n = '0' or sw_rst_fmc0 = '1') then
if rising_edge(clk_sys_62m5) then
if (rst_sys_62m5_n = '0' or sw_rst_fmc0 = '1') then
ddr1_dat_cyc_d <= '0';
else
ddr1_dat_cyc_d <= cnx_master_out(c_WB_SLAVE_FMC1_DDR_DAT).cyc;
......@@ -1605,10 +1424,10 @@ begin
ddr1_addr_cnt_en <= not(cnx_master_out(c_WB_SLAVE_FMC1_DDR_DAT).cyc) and ddr1_dat_cyc_d;
-- address counter
p_ddr1_addr_cnt : process (sys_clk_62_5)
p_ddr1_addr_cnt : process (clk_sys_62m5)
begin
if rising_edge(sys_clk_62_5) then
if (sys_rst_62_5_n = '0' or sw_rst_fmc0 = '1') then
if rising_edge(clk_sys_62m5) then
if (rst_sys_62m5_n = '0' or sw_rst_fmc0 = '1') then
ddr1_addr_cnt <= (others => '0');
elsif (cnx_master_out(c_WB_SLAVE_FMC1_DDR_ADR).we = '1' and
cnx_master_out(c_WB_SLAVE_FMC1_DDR_ADR).stb = '1' and
......@@ -1621,10 +1440,10 @@ begin
end process p_ddr1_addr_cnt;
-- ack generation
p_ddr1_addr_ack : process (sys_clk_62_5)
p_ddr1_addr_ack : process (clk_sys_62m5)
begin
if rising_edge(sys_clk_62_5) then
if (sys_rst_62_5_n = '0' or sw_rst_fmc0 = '1') then
if rising_edge(clk_sys_62m5) then
if (rst_sys_62m5_n = '0' or sw_rst_fmc0 = '1') then
cnx_master_in(c_WB_SLAVE_FMC1_DDR_ADR).ack <= '0';
elsif (cnx_master_out(c_WB_SLAVE_FMC1_DDR_ADR).stb = '1' and
cnx_master_out(c_WB_SLAVE_FMC1_DDR_ADR).cyc = '1') then
......@@ -1639,14 +1458,16 @@ begin
cnx_master_in(c_WB_SLAVE_FMC1_DDR_ADR).dat <= std_logic_vector(ddr1_addr_cnt);
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_FMC1_DDR_DAT).err <= '0';
cnx_master_in(c_WB_SLAVE_FMC1_DDR_DAT).rty <= '0';
cnx_master_in(c_WB_SLAVE_FMC1_DDR_DAT).int <= '0';
cnx_master_in(c_WB_SLAVE_FMC1_DDR_ADR).err <= '0';
cnx_master_in(c_WB_SLAVE_FMC1_DDR_ADR).rty <= '0';
cnx_master_in(c_WB_SLAVE_FMC1_DDR_ADR).stall <= '0';
cnx_master_in(c_WB_SLAVE_FMC1_DDR_ADR).int <= '0';
------------------------------------------------------------------------------
-- Front panel LED control
--
-- Carrier front panel LEDs and LEMOs
------------------------------------------------------------------------------
cmp_led_controller : gc_bicolor_led_ctrl
generic map(
......@@ -1656,12 +1477,12 @@ begin
g_refresh_rate => 250 -- in Hz
)
port map(
rst_n_i => sys_rst_62_5_n,
clk_i => sys_clk_62_5,
rst_n_i => rst_sys_62m5_n,
clk_i => clk_sys_62m5,
led_intensity_i => "1100100", -- in %
led_state_i => led_state,
led_state_i => svec_led,
column_o => fp_led_column_o,
line_o => fp_led_line_o,
......@@ -1672,31 +1493,36 @@ begin
generic map (
g_width => 2500000)
port map (
clk_i => sys_clk_62_5,
rst_n_i => sys_rst_62_5_n,
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
pulse_i => cnx_slave_in(c_WB_MASTER_VME).cyc,
extended_o => vme_access
);
cmp_fmc0_trig_irq_led : gc_extend_pulse
generic map (
g_width => 2500000)
port map (
clk_i => sys_clk_62_5,
rst_n_i => sys_rst_62_5_n,
pulse_i => trig_irq_p(0),
extended_o => fmc0_trig_irq_led
);
cmp_fmc0_acq_end_irq_led : gc_extend_pulse
generic map (
g_width => 2500000)
port map (
clk_i => sys_clk_62_5,
rst_n_i => sys_rst_62_5_n,
pulse_i => acq_end_irq_p(0),
extended_o => fmc0_acq_end_irq_led
);
gen_fmc_irq_led : for I in 0 to c_NB_FMC_SLOTS - 1 generate
cmp_fmc_trig_irq_led : gc_extend_pulse
generic map (
g_width => 2500000)
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
pulse_i => trig_irq_p(I),
extended_o => fmc_trig_irq_led(I)
);
cmp_fmc_acq_end_irq_led : gc_extend_pulse
generic map (
g_width => 2500000)
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
pulse_i => acq_end_irq_p(0),
extended_o => fmc_acq_end_irq_led(I)
);
end generate gen_fmc_irq_led;
-- Logic OR of signals and CSR register for LED control
svec_led <= led_state or led_state_csr;
-- LED 1 : VME access
led_state(1 downto 0) <= c_led_green when vme_access = '1' else c_led_off;
......@@ -1708,29 +1534,45 @@ begin
led_state(5 downto 4) <= c_led_green when wr_led_link = '1' else c_led_off;
-- LED 4 :
led_state(7 downto 6) <= '0' & led_pwm;
led_state(7 downto 6) <= c_led_green when led_pwm = '1' else c_led_off;
-- LED 5 :
led_state(9 downto 8) <= fmc0_trig_irq_led & '0';
led_state(9 downto 8) <= c_led_red_green when fmc_trig_irq_led(0) = '1' else c_led_off;
-- LED 6 :
led_state(11 downto 10) <= fmc0_acq_end_irq_led & '0';
led_state(11 downto 10) <= c_led_red_green when fmc_acq_end_irq_led(0) = '1' else c_led_off;
-- LED 7 :
led_state(13 downto 12) <= '0' & fmc_irq(0);
led_state(13 downto 12) <= c_led_red_green when fmc_trig_irq_led(1) = '1' else c_led_off;
-- LED 8 :
led_state(15 downto 14) <= '0' & irq_to_vme;
led_state(15 downto 14) <= c_led_red_green when fmc_acq_end_irq_led(1) = '1' else c_led_off;
--led_state(15 downto 12) <= led_state_man(15 downto 12);
-- Div by 2 reference clock to LEMO connector
process(clk_ref_125m)
begin
if rising_edge(clk_ref_125m) then
clk_ref_div2 <= not clk_ref_div2;
end if;
end process;
-- Front panel IO configuration
fp_gpio1_o <= pps;
fp_gpio2_o <= clk_ref_div2;
clk_ext_ref <= fp_gpio3_i;
pps_ext_in <= fp_gpio4_i;
fp_term_en_o <= (others => '0');
fp_gpio1_a2b_o <= '1';
fp_gpio2_a2b_o <= '1';
fp_gpio34_a2b_o <= '0';
------------------------------------------------------------------------------
-- FPGA loaded led (heart beat)
------------------------------------------------------------------------------
p_led_pwn_update_cnt : process (sys_clk_62_5)
p_led_pwn_update_cnt : process (clk_sys_62m5)
begin
if rising_edge(sys_clk_62_5) then
if (sys_rst_62_5_n = '0') then
if rising_edge(clk_sys_62m5) then
if (rst_sys_62m5_n = '0') then
led_pwm_update_cnt <= (others => '0');
led_pwm_update <= '0';
elsif (led_pwm_update_cnt = to_unsigned(477, 10)) then
......@@ -1743,10 +1585,10 @@ begin
end if;
end process p_led_pwn_update_cnt;
p_led_pwn_val : process (sys_clk_62_5)
p_led_pwn_val : process (clk_sys_62m5)
begin
if rising_edge(sys_clk_62_5) then
if (sys_rst_62_5_n = '0') then
if rising_edge(clk_sys_62m5) then
if (rst_sys_62m5_n = '0') then
led_pwm_val <= (others => '0');
led_pwm_val_down <= '0';
elsif (led_pwm_update = '1') then
......@@ -1765,10 +1607,10 @@ begin
end if;
end process p_led_pwn_val;
p_led_pwn_cnt : process (sys_clk_62_5)
p_led_pwn_cnt : process (clk_sys_62m5)
begin
if rising_edge(sys_clk_62_5) then
if (sys_rst_62_5_n = '0') then
if rising_edge(clk_sys_62m5) then
if (rst_sys_62m5_n = '0') then
led_pwm_cnt <= (others => '0');
else
led_pwm_cnt <= led_pwm_cnt + 1;
......@@ -1776,10 +1618,10 @@ begin
end if;
end process p_led_pwn_cnt;
p_led_pwn : process (sys_clk_62_5)
p_led_pwn : process (clk_sys_62m5)
begin
if rising_edge(sys_clk_62_5) then
if (sys_rst_62_5_n = '0') then
if rising_edge(clk_sys_62m5) then
if (rst_sys_62m5_n = '0') then
led_pwm <= '0';
elsif (led_pwm_cnt = 0) then
led_pwm <= '1';
......@@ -1789,12 +1631,4 @@ begin
end if;
end process p_led_pwn;
-- LED pwm ready to be used
-- <= led_pwm;
------------------------------------------------------------------------------
-- Assign unused outputs
------------------------------------------------------------------------------
end rtl;
hdl/svec/svec_top_fmc_adc_100Ms.ucf
View file @ 07e7b7de
......@@ -24,14 +24,14 @@ NET "vme_berr_o" LOC = R3;
NET "vme_as_n_i" LOC = P6;
NET "vme_addr_oe_n_o" LOC = N4;
NET "vme_addr_dir_o" LOC = N5;
NET "vme_irq_n_o[7]" LOC = R7;
NET "vme_irq_n_o[6]" LOC = AH2;
NET "vme_irq_n_o[5]" LOC = AF2;
NET "vme_irq_n_o[4]" LOC = N9;
NET "vme_irq_n_o[3]" LOC = N10;
NET "vme_irq_n_o[2]" LOC = AH4;
NET "vme_irq_n_o[1]" LOC = AG4;
NET "vme_ga_i[5]" LOC = M6;
NET "vme_irq_o[7]" LOC = R7;
NET "vme_irq_o[6]" LOC = AH2;
NET "vme_irq_o[5]" LOC = AF2;
NET "vme_irq_o[4]" LOC = N9;
NET "vme_irq_o[3]" LOC = N10;
NET "vme_irq_o[2]" LOC = AH4;
NET "vme_irq_o[1]" LOC = AG4;
NET "vme_gap_i" LOC = M6;
NET "vme_ga_i[4]" LOC = V9;
NET "vme_ga_i[3]" LOC = V10;
NET "vme_ga_i[2]" LOC = AJ1;
......@@ -125,14 +125,14 @@ NET "vme_berr_o" IOSTANDARD = "LVCMOS33";
NET "vme_as_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_addr_oe_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_addr_dir_o" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[7]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[6]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[5]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[4]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[3]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[2]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[1]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[5]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[7]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[6]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[5]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[4]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[3]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[2]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[1]" IOSTANDARD = "LVCMOS33";
NET "vme_gap_i" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[4]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[3]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[2]" IOSTANDARD = "LVCMOS33";
......@@ -429,6 +429,12 @@ NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS33";
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_p_i" LOC = B19;
NET "clk_125m_gtp_n_i" LOC = A19;
NET "clk_125m_gtp_p_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_n_i" IOSTANDARD = "LVDS_25";
#----------------------------------------
# SFP slot
#----------------------------------------
......@@ -437,21 +443,18 @@ NET "sfp_txn_o" LOC = A23;
NET "sfp_rxp_i" LOC = D22;
NET "sfp_rxn_i" LOC = C22;
NET "clk_125m_gtp_p_i" LOC = B19;
NET "clk_125m_gtp_n_i" LOC = A19;
NET "sfp_los_i" LOC = W25;
NET "sfp_mod_def0_b" LOC = Y26;
NET "sfp_mod_def0_i" LOC = Y26;
NET "sfp_mod_def1_b" LOC = Y27;
NET "sfp_mod_def2_b" LOC = AA24;
NET "sfp_rate_select_b" LOC = W24;
NET "sfp_rate_select_o" LOC = W24;
NET "sfp_tx_disable_o" LOC = AA25;
NET "sfp_tx_fault_i" LOC = AA27;
NET "sfp_los_i" IOSTANDARD = "LVCMOS33";
NET "sfp_mod_def0_b" IOSTANDARD = "LVCMOS33";
NET "sfp_mod_def0_i" IOSTANDARD = "LVCMOS33";
NET "sfp_mod_def1_b" IOSTANDARD = "LVCMOS33";
NET "sfp_mod_def2_b" IOSTANDARD = "LVCMOS33";
NET "sfp_rate_select_b" IOSTANDARD = "LVCMOS33";
NET "sfp_rate_select_o" IOSTANDARD = "LVCMOS33";
NET "sfp_tx_disable_o" IOSTANDARD = "LVCMOS33";
NET "sfp_tx_fault_i" IOSTANDARD = "LVCMOS33";
......@@ -948,24 +951,26 @@ TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%;
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo_i";
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
#NET "U_GTP/ch1_gtp_clkout_int<1>" TNM_NET = U_GTP/ch1_gtp_clkout_int<1>;
#TIMESPEC TS_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "U_GTP/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
NET "cmp_xwrc_board_svec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = cmp_xwrc_board_svec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>;
TIMESPEC TS_cmp_xwrc_board_svec_cmp_xwrc_platform_gen_phy_spartan6_cmp_gtp_ch1_gtp_clkout_int_1_ = PERIOD "cmp_xwrc_board_svec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
# ADC
NET "adc0_dco_n_i" TNM_NET = adc0_dco_n_i;
TIMESPEC TS_adc0_dco_n_i = PERIOD "adc0_dco_n_i" 2 ns HIGH 50%;
NET "adc1_dco_n_i" TNM_NET = adc1_dco_n_i;
TIMESPEC TS_adc1_dco_n_i = PERIOD "adc1_dco_n_i" 2 ns HIGH 50%;
TIMESPEC TS_adc0_dco_n_i = PERIOD "adc0_dco_n_i" 2.5 ns HIGH 50%;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
TIMESPEC TS_ = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
#INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
#INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
#TIMESPEC TS_ = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
# external 10MHz clock input
NET "fp_gpio3_i" TNM_NET = fp_gpio3_i;
TIMESPEC TS_fp_gpio3_i = PERIOD "fp_gpio3_i" 100 ns HIGH 50%;
NET "clk_125m_pllref" TNM_NET = clk_125m_pllref;
NET "sys_clk_62_5" TNM_NET = sys_clk_62_5;
TIMESPEC TS_crossdomain_01 = FROM "clk_125m_pllref" TO "sys_clk_62_5" 4ns DATAPATHONLY;
TIMESPEC TS_crossdomain_02 = FROM "sys_clk_62_5" TO "clk_125m_pllref" 4ns DATAPATHONLY;
NET "clk_ddr_333m_buf" TNM_NET = clk_ddr_333m;
NET "clk_sys_62m5" TNM_NET = clk_sys_62m5;
TIMESPEC TS_crossdomain_01 = FROM "clk_sys_62m5" TO "clk_ddr_333m" 4ns DATAPATHONLY;
# Force PPS output to always be placed as IOB register
INST "cmp_xwrc_board_svec/cmp_board_common/cmp_xwr_core/wrpc/pps_gen/wrapped_ppsgen/pps_out_o" IOB = FORCE;
#===============================================================================
# False Path
......@@ -990,5 +995,5 @@ NET "cmp_powerup_reset/master_rstn" TIG;
# Async reset inputs to reset synchroniser
NET "rst_n_i" TIG;
NET "sys_clk_pll_locked" TIG;
#NET "sys_clk_pll_locked" TIG;
NET "vme_sysreset_n_i" TIG;
hdl/svec/syn/Manifest.py
View file @ 07e7b7de
......@@ -16,12 +16,14 @@ modules = {
"local" : [
"../rtl",
"../../adc/rtl",
"../../ip_cores/wr-cores/board/svec",
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git",
"git://ohwr.org/hdl-core-lib/vme64x-core.git",
"git://ohwr.org/hdl-core-lib/wr-cores.git",
"git://ohwr.org/hdl-core-lib/etherbone-core.git",
],
}
......
hdl/svec/wb_gen/carrier_csr.h
View file @ 07e7b7de
......@@ -3,7 +3,7 @@
* File : carrier_csr.h
* Author : auto-generated by wbgen2 from carrier_csr.wb
* Created : Thu Jun 16 17:11:57 2016
* Created : Fri Feb 23 15:39:10 2018
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
......@@ -80,9 +80,6 @@
#define CARRIER_CSR_CTRL_FP_LEDS_MAN_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define CARRIER_CSR_CTRL_FP_LEDS_MAN_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: White Rabbit enable in reg: Control */
#define CARRIER_CSR_CTRL_WRABBIT_EN WBGEN2_GEN_MASK(16, 1)
/* definitions for register: Reset Register */
/* definitions for field: State of the FMC 1 reset line in reg: Reset Register */
......
hdl/svec/wb_gen/carrier_csr.htm
View file @ 07e7b7de
......@@ -373,23 +373,6 @@ carrier_csr_ctrl_fp_leds_man_o[15:0]
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_ctrl_wrabbit_en_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
......@@ -1134,8 +1117,8 @@ CTRL
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
WRABBIT_EN
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -1252,10 +1235,6 @@ FP_LEDS_MAN[7:0]
FP_LEDS_MAN
</b>[<i>read/write</i>]: Front panel LED manual control
<br>Height front panel LED, two bits per LED.<br>00 = OFF<br>01 = Green<br>10 = Red<br>11 = Orange
<li><b>
WRABBIT_EN
</b>[<i>read/write</i>]: White Rabbit enable
<br>Enable White Rabbit features
</ul>
<a name="RST"></a>
<h3><a name="sect_3_4">3.4. Reset Register</a></h3>
......
hdl/svec/wb_gen/carrier_csr.wb
View file @ 07e7b7de
......@@ -104,15 +104,6 @@ peripheral {
access_dev = READ_ONLY;
};
field {
name = "White Rabbit enable";
description = "Enable White Rabbit features";
prefix = "wrabbit_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
......
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