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FMC ADC 100M 14b 4cha - Gateware
Commit 1233efd9 authored by mcattin's avatar mcattin
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Add utc core registers generated with wbgen2. 

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@83 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
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hdl/spec/rtl/utc_core_regs.vhd 0 → 100644
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---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for UTC core registers
---------------------------------------------------------------------------------------
-- File : ../rtl/utc_core_regs.vhd
-- Author : auto-generated by wbgen2 from utc_core_regs.wb
-- Created : Thu Nov 17 14:30:00 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE utc_core_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity utc_core_regs is
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(3 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
-- Port for std_logic_vector field: 'UTC seconds' in reg: 'UTC seconds register'
utc_core_seconds_o : out std_logic_vector(31 downto 0);
utc_core_seconds_i : in std_logic_vector(31 downto 0);
utc_core_seconds_load_o : out std_logic;
-- Port for std_logic_vector field: 'UTC coarse time' in reg: 'UTC coarse time register, system clock ticks (125MHz)'
utc_core_coarse_o : out std_logic_vector(31 downto 0);
utc_core_coarse_i : in std_logic_vector(31 downto 0);
utc_core_coarse_load_o : out std_logic;
-- Port for std_logic_vector field: 'Trigger time-tag metadata' in reg: 'Trigger time-tag metadata register'
utc_core_trig_tag_meta_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Trigger time-tag UTC seconds' in reg: 'Trigger time-tag UTC seconds register'
utc_core_trig_tag_seconds_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Trigger time-tag coarse time' in reg: 'Trigger time-tag coarse time (system clock ticks 125MHz) register'
utc_core_trig_tag_coarse_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Trigger time-tag fine time' in reg: 'Trigger time-tag fine time register, always 0 (used for time-tag format compatibility)'
utc_core_trig_tag_fine_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Acquisition start time-tag metadata' in reg: 'Acquisition start time-tag metadata register'
utc_core_acq_start_tag_meta_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Acquisition start time-tag UTC seconds' in reg: 'Acquisition start time-tag UTC seconds register'
utc_core_acq_start_tag_seconds_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Acquisition start time-tag coarse time' in reg: 'Acquisition start time-tag coarse time (system clock ticks 125MHz) register'
utc_core_acq_start_tag_coarse_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Acquisition start time-tag fine time' in reg: 'Acquisition start time-tag fine time register, always 0 (used for time-tag format compatibility)'
utc_core_acq_start_tag_fine_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Acquisition stop time-tag metadata' in reg: 'Acquisition stop time-tag metadata register'
utc_core_acq_stop_tag_meta_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Acquisition stop time-tag UTC seconds' in reg: 'Acquisition stop time-tag UTC seconds register'
utc_core_acq_stop_tag_seconds_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Acquisition stop time-tag coarse time' in reg: 'Acquisition stop time-tag coarse time (system clock ticks 125MHz) register'
utc_core_acq_stop_tag_coarse_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Acquisition stop time-tag fine time' in reg: 'Acquisition stop time-tag fine time register, always 0 (used for time-tag format compatibility)'
utc_core_acq_stop_tag_fine_i : in std_logic_vector(31 downto 0)
);
end utc_core_regs;
architecture syn of utc_core_regs is
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(3 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal bus_clock_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_data_i;
bwsel_reg <= wb_sel_i;
bus_clock_int <= wb_clk_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (bus_clock_int, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
utc_core_seconds_load_o <= '0';
utc_core_coarse_load_o <= '0';
elsif rising_edge(bus_clock_int) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
utc_core_seconds_load_o <= '0';
utc_core_coarse_load_o <= '0';
ack_in_progress <= '0';
else
utc_core_seconds_load_o <= '0';
utc_core_coarse_load_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(3 downto 0) is
when "0000" =>
if (wb_we_i = '1') then
utc_core_seconds_load_o <= '1';
else
rddata_reg(31 downto 0) <= utc_core_seconds_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0001" =>
if (wb_we_i = '1') then
utc_core_coarse_load_o <= '1';
else
rddata_reg(31 downto 0) <= utc_core_coarse_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0010" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_trig_tag_meta_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_trig_tag_seconds_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0100" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_trig_tag_coarse_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0101" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_trig_tag_fine_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0110" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_start_tag_meta_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0111" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_start_tag_seconds_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1000" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_start_tag_coarse_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1001" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_start_tag_fine_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1010" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_stop_tag_meta_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1011" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_stop_tag_seconds_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1100" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_stop_tag_coarse_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1101" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_stop_tag_fine_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_data_o <= rddata_reg;
-- UTC seconds
utc_core_seconds_o <= wrdata_reg(31 downto 0);
-- UTC coarse time
utc_core_coarse_o <= wrdata_reg(31 downto 0);
-- Trigger time-tag metadata
-- Trigger time-tag UTC seconds
-- Trigger time-tag coarse time
-- Trigger time-tag fine time
-- Acquisition start time-tag metadata
-- Acquisition start time-tag UTC seconds
-- Acquisition start time-tag coarse time
-- Acquisition start time-tag fine time
-- Acquisition stop time-tag metadata
-- Acquisition stop time-tag UTC seconds
-- Acquisition stop time-tag coarse time
-- Acquisition stop time-tag fine time
rwaddr_reg <= wb_addr_i;
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/spec/wb_gen/Makefile
View file @ 1233efd9
......@@ -3,3 +3,6 @@ RTL=../rtl/
carrier_csr:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -D $@.htm -C $@.h $@.wb
utc_core_regs:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -D $@.htm -C $@.h $@.wb
hdl/spec/wb_gen/utc_core_regs.h 0 → 100644
View file @ 1233efd9
/*
Register definitions for slave core: UTC core registers
* File : utc_core_regs.h
* Author : auto-generated by wbgen2 from utc_core_regs.wb
* Created : Thu Nov 17 14:30:00 2011
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE utc_core_regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_UTC_CORE_REGS_WB
#define __WBGEN2_REGDEFS_UTC_CORE_REGS_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: UTC seconds register */
/* definitions for register: UTC coarse time register, system clock ticks (125MHz) */
/* definitions for register: Trigger time-tag metadata register */
/* definitions for register: Trigger time-tag UTC seconds register */
/* definitions for register: Trigger time-tag coarse time (system clock ticks 125MHz) register */
/* definitions for register: Trigger time-tag fine time register, always 0 (used for time-tag format compatibility) */
/* definitions for register: Acquisition start time-tag metadata register */
/* definitions for register: Acquisition start time-tag UTC seconds register */
/* definitions for register: Acquisition start time-tag coarse time (system clock ticks 125MHz) register */
/* definitions for register: Acquisition start time-tag fine time register, always 0 (used for time-tag format compatibility) */
/* definitions for register: Acquisition stop time-tag metadata register */
/* definitions for register: Acquisition stop time-tag UTC seconds register */
/* definitions for register: Acquisition stop time-tag coarse time (system clock ticks 125MHz) register */
/* definitions for register: Acquisition stop time-tag fine time register, always 0 (used for time-tag format compatibility) */
PACKED struct UTC_CORE_WB {
/* [0x0]: REG UTC seconds register */
uint32_t SECONDS;
/* [0x4]: REG UTC coarse time register, system clock ticks (125MHz) */
uint32_t COARSE;
/* [0x8]: REG Trigger time-tag metadata register */
uint32_t TRIG_TAG_META;
/* [0xc]: REG Trigger time-tag UTC seconds register */
uint32_t TRIG_TAG_SECONDS;
/* [0x10]: REG Trigger time-tag coarse time (system clock ticks 125MHz) register */
uint32_t TRIG_TAG_COARSE;
/* [0x14]: REG Trigger time-tag fine time register, always 0 (used for time-tag format compatibility) */
uint32_t TRIG_TAG_FINE;
/* [0x18]: REG Acquisition start time-tag metadata register */
uint32_t ACQ_START_TAG_META;
/* [0x1c]: REG Acquisition start time-tag UTC seconds register */
uint32_t ACQ_START_TAG_SECONDS;
/* [0x20]: REG Acquisition start time-tag coarse time (system clock ticks 125MHz) register */
uint32_t ACQ_START_TAG_COARSE;
/* [0x24]: REG Acquisition start time-tag fine time register, always 0 (used for time-tag format compatibility) */
uint32_t ACQ_START_TAG_FINE;
/* [0x28]: REG Acquisition stop time-tag metadata register */
uint32_t ACQ_STOP_TAG_META;
/* [0x2c]: REG Acquisition stop time-tag UTC seconds register */
uint32_t ACQ_STOP_TAG_SECONDS;
/* [0x30]: REG Acquisition stop time-tag coarse time (system clock ticks 125MHz) register */
uint32_t ACQ_STOP_TAG_COARSE;
/* [0x34]: REG Acquisition stop time-tag fine time register, always 0 (used for time-tag format compatibility) */
uint32_t ACQ_STOP_TAG_FINE;
};
#endif
hdl/spec/wb_gen/utc_core_regs.htm 0 → 100644
View file @ 1233efd9
<HTML>
<HEAD>
<TITLE>utc_core_regs</TITLE>
<STYLE TYPE="text/css" MEDIA="all">
<!--
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font-family: Arial,Helvetica; font-size:12; }
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h2 { font-family: Trebuchet MS,Arial,Helvetica; font-size:22; color:#404040; }
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-->
</STYLE>
</HEAD>
<BODY>
<h1 class="heading">utc_core_regs</h1>
<h3>UTC core registers</h3>
<p>Wishbone slave for registers related to UTC core</p>
<h3>Contents:</h3>
<span style="margin-left: 0px; ">1. <A href="#sect_1_0">Memory map summary</a></span><br/>
<span style="margin-left: 0px; ">2. <A href="#sect_2_0">HDL symbol</a></span><br/>
<span style="margin-left: 0px; ">3. <A href="#sect_3_0">Register description</a></span><br/>
<span style="margin-left: 20px; ">3.1. <A href="#sect_3_1">UTC seconds register</a></span><br/>
<span style="margin-left: 20px; ">3.2. <A href="#sect_3_2">UTC coarse time register, system clock ticks (125MHz)</a></span><br/>
<span style="margin-left: 20px; ">3.3. <A href="#sect_3_3">Trigger time-tag metadata register</a></span><br/>
<span style="margin-left: 20px; ">3.4. <A href="#sect_3_4">Trigger time-tag UTC seconds register</a></span><br/>
<span style="margin-left: 20px; ">3.5. <A href="#sect_3_5">Trigger time-tag coarse time (system clock ticks 125MHz) register</a></span><br/>
<span style="margin-left: 20px; ">3.6. <A href="#sect_3_6">Trigger time-tag fine time register, always 0 (used for time-tag format compatibility)</a></span><br/>
<span style="margin-left: 20px; ">3.7. <A href="#sect_3_7">Acquisition start time-tag metadata register</a></span><br/>
<span style="margin-left: 20px; ">3.8. <A href="#sect_3_8">Acquisition start time-tag UTC seconds register</a></span><br/>
<span style="margin-left: 20px; ">3.9. <A href="#sect_3_9">Acquisition start time-tag coarse time (system clock ticks 125MHz) register</a></span><br/>
<span style="margin-left: 20px; ">3.10. <A href="#sect_3_10">Acquisition start time-tag fine time register, always 0 (used for time-tag format compatibility)</a></span><br/>
<span style="margin-left: 20px; ">3.11. <A href="#sect_3_11">Acquisition stop time-tag metadata register</a></span><br/>
<span style="margin-left: 20px; ">3.12. <A href="#sect_3_12">Acquisition stop time-tag UTC seconds register</a></span><br/>
<span style="margin-left: 20px; ">3.13. <A href="#sect_3_13">Acquisition stop time-tag coarse time (system clock ticks 125MHz) register</a></span><br/>
<span style="margin-left: 20px; ">3.14. <A href="#sect_3_14">Acquisition stop time-tag fine time register, always 0 (used for time-tag format compatibility)</a></span><br/>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<th >
H/W Address
</th>
<th >
Type
</th>
<th >
Name
</th>
<th >
VHDL/Verilog prefix
</th>
<th >
C prefix
</th>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x0
</td>
<td >
REG
</td>
<td >
<A href="#SECONDS">UTC seconds register</a>
</td>
<td class="td_code">
utc_core_seconds
</td>
<td class="td_code">
SECONDS
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x1
</td>
<td >
REG
</td>
<td >
<A href="#COARSE">UTC coarse time register, system clock ticks (125MHz)</a>
</td>
<td class="td_code">
utc_core_coarse
</td>
<td class="td_code">
COARSE
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x2
</td>
<td >
REG
</td>
<td >
<A href="#TRIG_TAG_META">Trigger time-tag metadata register</a>
</td>
<td class="td_code">
utc_core_trig_tag_meta
</td>
<td class="td_code">
TRIG_TAG_META
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x3
</td>
<td >
REG
</td>
<td >
<A href="#TRIG_TAG_SECONDS">Trigger time-tag UTC seconds register</a>
</td>
<td class="td_code">
utc_core_trig_tag_seconds
</td>
<td class="td_code">
TRIG_TAG_SECONDS
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x4
</td>
<td >
REG
</td>
<td >
<A href="#TRIG_TAG_COARSE">Trigger time-tag coarse time (system clock ticks 125MHz) register</a>
</td>
<td class="td_code">
utc_core_trig_tag_coarse
</td>
<td class="td_code">
TRIG_TAG_COARSE
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x5
</td>
<td >
REG
</td>
<td >
<A href="#TRIG_TAG_FINE">Trigger time-tag fine time register, always 0 (used for time-tag format compatibility)</a>
</td>
<td class="td_code">
utc_core_trig_tag_fine
</td>
<td class="td_code">
TRIG_TAG_FINE
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x6
</td>
<td >
REG
</td>
<td >
<A href="#ACQ_START_TAG_META">Acquisition start time-tag metadata register</a>
</td>
<td class="td_code">
utc_core_acq_start_tag_meta
</td>
<td class="td_code">
ACQ_START_TAG_META
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x7
</td>
<td >
REG
</td>
<td >
<A href="#ACQ_START_TAG_SECONDS">Acquisition start time-tag UTC seconds register</a>
</td>
<td class="td_code">
utc_core_acq_start_tag_seconds
</td>
<td class="td_code">
ACQ_START_TAG_SECONDS
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x8
</td>
<td >
REG
</td>
<td >
<A href="#ACQ_START_TAG_COARSE">Acquisition start time-tag coarse time (system clock ticks 125MHz) register</a>
</td>
<td class="td_code">
utc_core_acq_start_tag_coarse
</td>
<td class="td_code">
ACQ_START_TAG_COARSE
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x9
</td>
<td >
REG
</td>
<td >
<A href="#ACQ_START_TAG_FINE">Acquisition start time-tag fine time register, always 0 (used for time-tag format compatibility)</a>
</td>
<td class="td_code">
utc_core_acq_start_tag_fine
</td>
<td class="td_code">
ACQ_START_TAG_FINE
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0xa
</td>
<td >
REG
</td>
<td >
<A href="#ACQ_STOP_TAG_META">Acquisition stop time-tag metadata register</a>
</td>
<td class="td_code">
utc_core_acq_stop_tag_meta
</td>
<td class="td_code">
ACQ_STOP_TAG_META
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0xb
</td>
<td >
REG
</td>
<td >
<A href="#ACQ_STOP_TAG_SECONDS">Acquisition stop time-tag UTC seconds register</a>
</td>
<td class="td_code">
utc_core_acq_stop_tag_seconds
</td>
<td class="td_code">
ACQ_STOP_TAG_SECONDS
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0xc
</td>
<td >
REG
</td>
<td >
<A href="#ACQ_STOP_TAG_COARSE">Acquisition stop time-tag coarse time (system clock ticks 125MHz) register</a>
</td>
<td class="td_code">
utc_core_acq_stop_tag_coarse
</td>
<td class="td_code">
ACQ_STOP_TAG_COARSE
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0xd
</td>
<td >
REG
</td>
<td >
<A href="#ACQ_STOP_TAG_FINE">Acquisition stop time-tag fine time register, always 0 (used for time-tag format compatibility)</a>
</td>
<td class="td_code">
utc_core_acq_stop_tag_fine
</td>
<td class="td_code">
ACQ_STOP_TAG_FINE
</td>
</tr>
</table>
<h3><a name="sect_2_0">2. HDL symbol</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
rst_n_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>UTC seconds register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_clk_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_seconds_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_addr_i[3:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_seconds_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_data_i[31:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_seconds_load_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&lArr;
</td>
<td class="td_pblock_left">
wb_data_o[31:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_cyc_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>UTC coarse time register, system clock ticks (125MHz):</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_sel_i[3:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_coarse_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_stb_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_coarse_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_we_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_coarse_load_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_ack_o
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Trigger time-tag metadata register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_trig_tag_meta_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Trigger time-tag UTC seconds register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_trig_tag_seconds_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Trigger time-tag coarse time (system clock ticks 125MHz) register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_trig_tag_coarse_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Trigger time-tag fine time register, always 0 (used for time-tag format compatibility):</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_trig_tag_fine_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Acquisition start time-tag metadata register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_acq_start_tag_meta_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Acquisition start time-tag UTC seconds register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_acq_start_tag_seconds_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Acquisition start time-tag coarse time (system clock ticks 125MHz) register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_acq_start_tag_coarse_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Acquisition start time-tag fine time register, always 0 (used for time-tag format compatibility):</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_acq_start_tag_fine_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Acquisition stop time-tag metadata register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_acq_stop_tag_meta_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Acquisition stop time-tag UTC seconds register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_acq_stop_tag_seconds_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Acquisition stop time-tag coarse time (system clock ticks 125MHz) register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_acq_stop_tag_coarse_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Acquisition stop time-tag fine time register, always 0 (used for time-tag format compatibility):</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_acq_stop_tag_fine_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
</table>
<h3><a name="sect_3_0">3. Register description</a></h3>
<a name="SECONDS"></a>
<h3><a name="sect_3_1">3.1. UTC seconds register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
utc_core_seconds
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x0
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
SECONDS
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x0
</td>
</tr>
</table>
<p>
UTC seconds counter. Incremented everytime the UTC coarse counter overflows.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SECONDS[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SECONDS[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SECONDS[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SECONDS[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
SECONDS
</b>[<i>read/write</i>]: UTC seconds
</ul>
<a name="COARSE"></a>
<h3><a name="sect_3_2">3.2. UTC coarse time register, system clock ticks (125MHz)</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
utc_core_coarse
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x1
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
COARSE
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x4
</td>
</tr>
</table>
<p>
UTC coarse time counter clocked by 125MHz system clock.<br>Counts from 0 to 125000000.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
COARSE[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
COARSE[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
COARSE[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
COARSE[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
COARSE
</b>[<i>read/write</i>]: UTC coarse time
</ul>
<a name="TRIG_TAG_META"></a>
<h3><a name="sect_3_3">3.3. Trigger time-tag metadata register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
utc_core_trig_tag_meta
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x2
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
TRIG_TAG_META
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x8
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_META[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_META[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_META[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_META[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
TRIG_TAG_META
</b>[<i>read-only</i>]: Trigger time-tag metadata
<br>Holds time-tag metadata of the last trigger event
</ul>
<a name="TRIG_TAG_SECONDS"></a>
<h3><a name="sect_3_4">3.4. Trigger time-tag UTC seconds register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
utc_core_trig_tag_seconds
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x3
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
TRIG_TAG_SECONDS
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0xc
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_SECONDS[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_SECONDS[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_SECONDS[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_SECONDS[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
TRIG_TAG_SECONDS
</b>[<i>read-only</i>]: Trigger time-tag UTC seconds
<br>Holds time-tag UTC seconds of the last trigger event
</ul>
<a name="TRIG_TAG_COARSE"></a>
<h3><a name="sect_3_5">3.5. Trigger time-tag coarse time (system clock ticks 125MHz) register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
utc_core_trig_tag_coarse
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x4
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
TRIG_TAG_COARSE
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x10
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_COARSE[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_COARSE[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_COARSE[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_COARSE[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
TRIG_TAG_COARSE
</b>[<i>read-only</i>]: Trigger time-tag coarse time
<br>Holds time-tag coarse time of the last trigger event
</ul>
<a name="TRIG_TAG_FINE"></a>
<h3><a name="sect_3_6">3.6. Trigger time-tag fine time register, always 0 (used for time-tag format compatibility)</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
utc_core_trig_tag_fine
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x5
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
TRIG_TAG_FINE
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x14
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_FINE[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_FINE[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_FINE[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_FINE[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
TRIG_TAG_FINE
</b>[<i>read-only</i>]: Trigger time-tag fine time
<br>Holds time-tag fine time of the last trigger event
</ul>
<a name="ACQ_START_TAG_META"></a>
<h3><a name="sect_3_7">3.7. Acquisition start time-tag metadata register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
utc_core_acq_start_tag_meta
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x6
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
ACQ_START_TAG_META
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x18
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_META[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_META[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_META[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_META[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
ACQ_START_TAG_META
</b>[<i>read-only</i>]: Acquisition start time-tag metadata
<br>Holds time-tag metadata of the last acquisition start event
</ul>
<a name="ACQ_START_TAG_SECONDS"></a>
<h3><a name="sect_3_8">3.8. Acquisition start time-tag UTC seconds register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
utc_core_acq_start_tag_seconds
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x7
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
ACQ_START_TAG_SECONDS
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x1c
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_SECONDS[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_SECONDS[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_SECONDS[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_SECONDS[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
ACQ_START_TAG_SECONDS
</b>[<i>read-only</i>]: Acquisition start time-tag UTC seconds
<br>Holds time-tag UTC seconds of the last acquisition start event
</ul>
<a name="ACQ_START_TAG_COARSE"></a>
<h3><a name="sect_3_9">3.9. Acquisition start time-tag coarse time (system clock ticks 125MHz) register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
utc_core_acq_start_tag_coarse
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x8
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
ACQ_START_TAG_COARSE
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x20
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_COARSE[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_COARSE[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_COARSE[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_COARSE[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
ACQ_START_TAG_COARSE
</b>[<i>read-only</i>]: Acquisition start time-tag coarse time
<br>Holds time-tag coarse time of the last acquisition start event
</ul>
<a name="ACQ_START_TAG_FINE"></a>
<h3><a name="sect_3_10">3.10. Acquisition start time-tag fine time register, always 0 (used for time-tag format compatibility)</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
utc_core_acq_start_tag_fine
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x9
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
ACQ_START_TAG_FINE
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x24
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_FINE[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_FINE[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_FINE[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_FINE[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
ACQ_START_TAG_FINE
</b>[<i>read-only</i>]: Acquisition start time-tag fine time
<br>Holds time-tag fine time of the last acquisition start event
</ul>
<a name="ACQ_STOP_TAG_META"></a>
<h3><a name="sect_3_11">3.11. Acquisition stop time-tag metadata register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
utc_core_acq_stop_tag_meta
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0xa
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
ACQ_STOP_TAG_META
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x28
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_META[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_META[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_META[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_META[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
ACQ_STOP_TAG_META
</b>[<i>read-only</i>]: Acquisition stop time-tag metadata
<br>Holds time-tag metadata of the last acquisition stop event
</ul>
<a name="ACQ_STOP_TAG_SECONDS"></a>
<h3><a name="sect_3_12">3.12. Acquisition stop time-tag UTC seconds register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
utc_core_acq_stop_tag_seconds
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0xb
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
ACQ_STOP_TAG_SECONDS
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x2c
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_SECONDS[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_SECONDS[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_SECONDS[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_SECONDS[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
ACQ_STOP_TAG_SECONDS
</b>[<i>read-only</i>]: Acquisition stop time-tag UTC seconds
<br>Holds time-tag UTC seconds of the last acquisition stop event
</ul>
<a name="ACQ_STOP_TAG_COARSE"></a>
<h3><a name="sect_3_13">3.13. Acquisition stop time-tag coarse time (system clock ticks 125MHz) register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
utc_core_acq_stop_tag_coarse
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0xc
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
ACQ_STOP_TAG_COARSE
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x30
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_COARSE[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_COARSE[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_COARSE[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_COARSE[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
ACQ_STOP_TAG_COARSE
</b>[<i>read-only</i>]: Acquisition stop time-tag coarse time
<br>Holds time-tag coarse time of the last acquisition stop event
</ul>
<a name="ACQ_STOP_TAG_FINE"></a>
<h3><a name="sect_3_14">3.14. Acquisition stop time-tag fine time register, always 0 (used for time-tag format compatibility)</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
utc_core_acq_stop_tag_fine
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0xd
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
ACQ_STOP_TAG_FINE
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x34
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_FINE[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_FINE[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_FINE[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_FINE[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
ACQ_STOP_TAG_FINE
</b>[<i>read-only</i>]: Acquisition stop time-tag fine time
<br>Holds time-tag fine time of the last acquisition stop event
</ul>
</BODY>
</HTML>
hdl/spec/wb_gen/utc_core_regs.wb 0 → 100644
View file @ 1233efd9
peripheral {
name = "UTC core registers";
description = "Wishbone slave for registers related to UTC core";
hdl_entity = "utc_core_regs";
prefix = "utc_core";
reg {
name = "UTC seconds register";
description = "UTC seconds counter. Incremented everytime the UTC coarse counter overflows.";
prefix = "seconds";
field {
name = "UTC seconds";
type = SLV;
load = LOAD_EXT;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
};
reg {
name = "UTC coarse time register, system clock ticks (125MHz)";
description = "UTC coarse time counter clocked by 125MHz system clock.\nCounts from 0 to 125000000.";
prefix = "coarse";
field {
name = "UTC coarse time";
type = SLV;
load = LOAD_EXT;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
};
reg {
name = "Trigger time-tag metadata register";
prefix = "trig_tag_meta";
field {
name = "Trigger time-tag metadata";
description = "Holds time-tag metadata of the last trigger event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Trigger time-tag UTC seconds register";
prefix = "trig_tag_seconds";
field {
name = "Trigger time-tag UTC seconds";
description = "Holds time-tag UTC seconds of the last trigger event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Trigger time-tag coarse time (system clock ticks 125MHz) register";
prefix = "trig_tag_coarse";
field {
name = "Trigger time-tag coarse time";
description = "Holds time-tag coarse time of the last trigger event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Trigger time-tag fine time register, always 0 (used for time-tag format compatibility)";
prefix = "trig_tag_fine";
field {
name = "Trigger time-tag fine time";
description = "Holds time-tag fine time of the last trigger event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition start time-tag metadata register";
prefix = "acq_start_tag_meta";
field {
name = "Acquisition start time-tag metadata";
description = "Holds time-tag metadata of the last acquisition start event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition start time-tag UTC seconds register";
prefix = "acq_start_tag_seconds";
field {
name = "Acquisition start time-tag UTC seconds";
description = "Holds time-tag UTC seconds of the last acquisition start event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition start time-tag coarse time (system clock ticks 125MHz) register";
prefix = "acq_start_tag_coarse";
field {
name = "Acquisition start time-tag coarse time";
description = "Holds time-tag coarse time of the last acquisition start event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition start time-tag fine time register, always 0 (used for time-tag format compatibility)";
prefix = "acq_start_tag_fine";
field {
name = "Acquisition start time-tag fine time";
description = "Holds time-tag fine time of the last acquisition start event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition stop time-tag metadata register";
prefix = "acq_stop_tag_meta";
field {
name = "Acquisition stop time-tag metadata";
description = "Holds time-tag metadata of the last acquisition stop event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition stop time-tag UTC seconds register";
prefix = "acq_stop_tag_seconds";
field {
name = "Acquisition stop time-tag UTC seconds";
description = "Holds time-tag UTC seconds of the last acquisition stop event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition stop time-tag coarse time (system clock ticks 125MHz) register";
prefix = "acq_stop_tag_coarse";
field {
name = "Acquisition stop time-tag coarse time";
description = "Holds time-tag coarse time of the last acquisition stop event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition stop time-tag fine time register, always 0 (used for time-tag format compatibility)";
prefix = "acq_stop_tag_fine";
field {
name = "Acquisition stop time-tag fine time";
description = "Holds time-tag fine time of the last acquisition stop event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
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