Commit f513a2b9 authored by mcattin's avatar mcattin

Add a BUFG on the adc serdes PLL feedback path, add termination on LVDS data line from ADC.

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@82 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
parent 1fb0e23d
......@@ -266,6 +266,7 @@ architecture rtl of fmc_adc_100Ms_core is
-- Clocks and PLL
signal dco_clk : std_logic;
signal clk_fb : std_logic;
signal clk_fb_buf : std_logic;
signal locked_in : std_logic;
signal locked_out : std_logic;
signal serdes_clk : std_logic;
......@@ -473,7 +474,7 @@ begin
REF_JITTER => 0.010)
port map (
-- Output clocks
CLKFBOUT => clk_fb,
CLKFBOUT => clk_fb_buf,
CLKOUT0 => serdes_clk,
CLKOUT1 => fs_clk_buf,
CLKOUT2 => open,
......@@ -493,6 +494,12 @@ begin
I => fs_clk_buf
);
cmp_fb_clk_buf : BUFG
port map (
O => clk_fb,
I => clk_fb_buf
);
------------------------------------------------------------------------------
-- ADC data and frame SerDes
------------------------------------------------------------------------------
......
......@@ -137,7 +137,7 @@ begin
-- Instantiate a buffer for every bit of the data bus
ibufds_inst : IBUFDS
generic map (
DIFF_TERM => FALSE, -- Differential termination
DIFF_TERM => TRUE, -- Differential termination
IOSTANDARD => "LVDS_25")
port map (
I => DATA_IN_FROM_PINS_P (pin_count),
......
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