hdl: reorder trigger tag bits to make it easier for software parsing

15459ed7 · Dimitris Lampridis · 11cc1b6d · 15459ed7
Commit 15459ed7 authored Jan 31, 2018 by Dimitris Lampridis
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fmc_adc_100Ms_core.vhd hdl/adc/rtl/fmc_adc_100Ms_core.vhd +4 -2

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--- a/hdl/adc/rtl/fmc_adc_100Ms_core.vhd
+++ b/hdl/adc/rtl/fmc_adc_100Ms_core.vhd
@@ -9,7 +9,7 @@
 --              Dimitrios Lampridis  <dimitrios.lampridis@cern.ch>
 -- Company    : CERN (BE-CO-HT)
 -- Created    : 2011-02-24
-- Last update: 2018-01-26
+-- Last update: 2018-01-30
 -- Standard   : VHDL'93/02
 -------------------------------------------------------------------------------
 -- Description: FMC ADC 100Ms/s core.
@@ -1387,7 +1387,9 @@ begin

  trig_tag_done <= acq_in_trig_tag and acq_in_trig_tag_d;

-  trig_tag_data <= X"0" & trig_storage & trigger_tag_i.coarse when trig_tag_done = '1' else
+  -- We first send "ACCE55" followed by trigger tag seconds, and then the trigger status
+  -- followed by trigger tag clock ticks.
+  trig_tag_data <= trig_storage & X"0" & trigger_tag_i.coarse when trig_tag_done = '1' else
                   X"ACCE55" & trigger_tag_i.seconds;

  ------------------------------------------------------------------------------