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FMC ADC 100M 14b 4cha - Gateware
Commit 235c95da authored by mcattin's avatar mcattin
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Add UTC core, IRQ controller and 1-wire for carrier ID/temp to design. 

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@86 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
parent 0e9e8084
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Showing with 977 additions and 802 deletions
hdl/adc/rtl/fmc_adc_100Ms_core.vhd
View file @ 235c95da
......@@ -34,8 +34,8 @@ use UNISIM.vcomponents.all;
entity fmc_adc_100Ms_core is
port (
-- Clock, reset
sys_clk_i : std_logic;
sys_rst_n_i : std_logic;
sys_clk_i : in std_logic;
sys_rst_n_i : in std_logic;
-- CSR wishbone interface
wb_csr_adr_i : in std_logic_vector(4 downto 0);
......@@ -58,6 +58,11 @@ entity fmc_adc_100Ms_core is
wb_ddr_ack_i : in std_logic;
wb_ddr_stall_i : in std_logic;
-- Events output pulses
trigger_p_o : out std_logic;
acq_start_p_o : out std_logic;
acq_stop_p_o : out std_logic;
-- FMC interface
ext_trigger_p_i : in std_logic; -- External trigger
ext_trigger_n_i : in std_logic;
......@@ -866,6 +871,11 @@ begin
-- Aqcuisition FSM
------------------------------------------------------------------------------
-- Event pulses to time-tag
trigger_p_o <= acq_trig;
acq_start_p_o <= acq_start;
acq_stop_p_o <= acq_stop;
-- FSM commands
acq_start <= '1' when fsm_cmd_wr = '1' and fsm_cmd = "01" else '0';
acq_stop <= '1' when fsm_cmd_wr = '1' and fsm_cmd = "10" else '0';
......@@ -1086,78 +1096,78 @@ begin
wb_ddr_fifo_din <= (others => '0');
wb_ddr_fifo_wr_en <= '0';
elsif rising_edge(sys_clk_i) then
if single_shot = '1' then
wb_ddr_fifo_din <= sync_fifo_dout(63 downto 0);
wb_ddr_fifo_wr_en <= samples_wr_en;
else
wb_ddr_fifo_din <= dpram_dout;
wb_ddr_fifo_wr_en <= dpram_valid;
end if;
if single_shot = '1' then
wb_ddr_fifo_din <= sync_fifo_dout(63 downto 0);
wb_ddr_fifo_wr_en <= samples_wr_en;
else
wb_ddr_fifo_din <= dpram_dout;
wb_ddr_fifo_wr_en <= dpram_valid;
end if;
end process p_wb_ddr_fifo_input;
end if;
end process p_wb_ddr_fifo_input;
--wb_ddr_fifo_din <= sync_fifo_dout(63 downto 0) when single_shot = '1' else dpram_dout;
--wb_ddr_fifo_wr_en <= samples_wr_en when single_shot = '1' else dpram_valid;
wb_ddr_fifo_wr <= wb_ddr_fifo_wr_en and sync_fifo_valid and not(wb_ddr_fifo_full);
wb_ddr_fifo_wr <= wb_ddr_fifo_wr_en and sync_fifo_valid and not(wb_ddr_fifo_full);
wb_ddr_fifo_rd <= wb_ddr_fifo_dreq and not(wb_ddr_fifo_empty) and not(wb_ddr_stall_t);
wb_ddr_fifo_dreq <= '1';
wb_ddr_fifo_rd <= wb_ddr_fifo_dreq and not(wb_ddr_fifo_empty) and not(wb_ddr_stall_t);
wb_ddr_fifo_dreq <= '1';
------------------------------------------------------------------------------
-- RAM address counter (32-bit word address)
------------------------------------------------------------------------------
p_ram_addr_cnt : process (wb_ddr_clk_i, sys_rst_n_i)
begin
if sys_rst_n_i = '0' then
ram_addr_cnt <= (others => '0');
elsif rising_edge(wb_ddr_clk_i) then
if acq_start = '1' then
p_ram_addr_cnt : process (wb_ddr_clk_i, sys_rst_n_i)
begin
if sys_rst_n_i = '0' then
ram_addr_cnt <= (others => '0');
elsif wb_ddr_fifo_valid = '1' then
ram_addr_cnt <= ram_addr_cnt + 1;
elsif rising_edge(wb_ddr_clk_i) then
if acq_start = '1' then
ram_addr_cnt <= (others => '0');
elsif wb_ddr_fifo_valid = '1' then
ram_addr_cnt <= ram_addr_cnt + 1;
end if;
end if;
end if;
end process p_ram_addr_cnt;
end process p_ram_addr_cnt;
------------------------------------------------------------------------------
-- Wishbone master (to DDR)
------------------------------------------------------------------------------
p_wb_master : process (wb_ddr_clk_i, sys_rst_n_i)
begin
if sys_rst_n_i = '0' then
wb_ddr_cyc_o <= '0';
wb_ddr_we_o <= '0';
wb_ddr_stb_o <= '0';
wb_ddr_adr_o <= (others => '0');
wb_ddr_dat_o <= (others => '0');
wb_ddr_stall_t <= '0';
elsif rising_edge(wb_ddr_clk_i) then
if wb_ddr_fifo_valid = '1' then --if (wb_ddr_fifo_valid = '1') and (wb_ddr_stall_i = '0') then
wb_ddr_stb_o <= '1';
wb_ddr_adr_o <= "0000000" & std_logic_vector(ram_addr_cnt);
if test_data_en = '1' then
wb_ddr_dat_o <= x"00000000" & "0000000" & std_logic_vector(ram_addr_cnt);
p_wb_master : process (wb_ddr_clk_i, sys_rst_n_i)
begin
if sys_rst_n_i = '0' then
wb_ddr_cyc_o <= '0';
wb_ddr_we_o <= '0';
wb_ddr_stb_o <= '0';
wb_ddr_adr_o <= (others => '0');
wb_ddr_dat_o <= (others => '0');
wb_ddr_stall_t <= '0';
elsif rising_edge(wb_ddr_clk_i) then
if wb_ddr_fifo_valid = '1' then --if (wb_ddr_fifo_valid = '1') and (wb_ddr_stall_i = '0') then
wb_ddr_stb_o <= '1';
wb_ddr_adr_o <= "0000000" & std_logic_vector(ram_addr_cnt);
if test_data_en = '1' then
wb_ddr_dat_o <= x"00000000" & "0000000" & std_logic_vector(ram_addr_cnt);
else
wb_ddr_dat_o <= wb_ddr_fifo_dout;
end if;
else
wb_ddr_dat_o <= wb_ddr_fifo_dout;
wb_ddr_stb_o <= '0';
end if;
else
wb_ddr_stb_o <= '0';
end if;
if wb_ddr_fifo_valid = '1' then
wb_ddr_cyc_o <= '1';
wb_ddr_we_o <= '1';
--elsif (wb_ddr_fifo_empty = '1') and (acq_end = '1') then
elsif (wb_ddr_fifo_empty = '1') and (acq_fsm_state = "001") then
wb_ddr_cyc_o <= '0';
wb_ddr_we_o <= '0';
end if;
if wb_ddr_fifo_valid = '1' then
wb_ddr_cyc_o <= '1';
wb_ddr_we_o <= '1';
--elsif (wb_ddr_fifo_empty = '1') and (acq_end = '1') then
elsif (wb_ddr_fifo_empty = '1') and (acq_fsm_state = "001") then
wb_ddr_cyc_o <= '0';
wb_ddr_we_o <= '0';
end if;
wb_ddr_stall_t <= wb_ddr_stall_i;
wb_ddr_stall_t <= wb_ddr_stall_i;
end if;
end process p_wb_master;
end if;
end process p_wb_master;
wb_ddr_sel_o <= X"FF";
wb_ddr_sel_o <= X"FF";
end rtl;
hdl/spec/rtl/Manifest.py
View file @ 235c95da
files = [
"spec_top_fmc_adc_100Ms.vhd",
"carrier_csr.vhd"];
"carrier_csr.vhd",
"utc_core_regs.vhd",
"utc_core.vhd",
"irq_controller_regs.vhd",
"irq_controller.vhd"];
modules = {
"local" : "../../adc/rtl",
......
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
View file @ 235c95da
This diff is collapsed.
hdl/spec/spec_top_fmc_adc_100Ms.ucf
View file @ 235c95da
......@@ -55,8 +55,8 @@ NET "clk20_vcxo_i" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# 1-wire thermometer w/ ID
#----------------------------------------
#NET "THERMO_ID" LOC = D4;
#NET "THERMO_ID" IOSTANDARD = "LVCMOS25";
NET "CARRIER_ONE_WIRE_B" LOC = D4;
NET "CARRIER_ONE_WIRE_B" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# GN4124 interface
......@@ -331,8 +331,8 @@ NET "si570_scl_b" IOSTANDARD = "LVCMOS25";
NET "si570_sda_b" LOC = T12; # LA18_P
NET "si570_sda_b" IOSTANDARD = "LVCMOS25";
NET "one_wire_b" LOC = Y18; # LA29_N
NET "one_wire_b" IOSTANDARD = "LVCMOS25";
NET "mezz_one_wire_b" LOC = Y18; # LA29_N
NET "mezz_one_wire_b" IOSTANDARD = "LVCMOS25";
NET "prsnt_m2c_n_i" LOC = AB14; # PRSNT_M2C_L
NET "prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
......
hdl/spec/syn/spec_fmc_adc_100Ms.xise
View file @ 235c95da
This diff is collapsed.
hdl/spec/wb_gen/Makefile
View file @ 235c95da
......@@ -6,3 +6,6 @@ carrier_csr:
utc_core_regs:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -D $@.htm -C $@.h $@.wb
irq_controller_regs:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -D $@.htm -C $@.h $@.wb
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