Maintenance scheduled 24th July -- expect downtime along that day

Commit 2f92c67d authored by Matthieu Cattin's avatar Matthieu Cattin

Merging sdb enabled design to master.

parents e73d48b6 9a65c3a9
hdl/spec/ip_cores/ddr3-sp6-core/
hdl/spec/ip_cores/general-cores/
hdl/spec/ip_cores/gn4124-core/
hdl/spec/sim/modelsim.ini
hdl/spec/sim/work/
hdl/spec/syn/_ngo/
hdl/spec/syn/_xmsgs/
hdl/spec/syn/par_usage_statistics.html
hdl/spec/syn/run.tcl
hdl/spec/syn/*.gise
hdl/spec/syn/*.bgn
hdl/spec/syn/*.bld
hdl/spec/syn/*.cmd_log
hdl/spec/syn/*.drc
hdl/spec/syn/*.lso
hdl/spec/syn/*.ncd
hdl/spec/syn/*.ngc
hdl/spec/syn/*.ngd
hdl/spec/syn/*.ngr
hdl/spec/syn/*.pad
hdl/spec/syn/*.pcf
hdl/spec/syn/*.prj
hdl/spec/syn/*.ptwx
hdl/spec/syn/*.stx
hdl/spec/syn/*.twx
hdl/spec/syn/*.unroutes
hdl/spec/syn/*.ut
hdl/spec/syn/*.xpi
hdl/spec/syn/*.xst
hdl/spec/syn/*_bitgen.xwbt
hdl/spec/syn/*_guide.ncd
hdl/spec/syn/*_map.map
hdl/spec/syn/*_map.ncd
hdl/spec/syn/*_map.ngm
hdl/spec/syn/*_map.xrpt
hdl/spec/syn/*_ngdbuild.xrpt
hdl/spec/syn/*_pad.csv
hdl/spec/syn/*_pad.txt
hdl/spec/syn/*_par.xrpt
hdl/spec/syn/*_summary.xml
hdl/spec/syn/*_usage.xml
hdl/spec/syn/*_xst.xrpt
hdl/spec/syn/webtalk.log
hdl/spec/syn/webtalk_pn.xml
hdl/spec/syn/xlnx_auto_0_xdb/
hdl/spec/syn/xst/
\ No newline at end of file
......@@ -69,6 +69,8 @@ Here's an overview of the fmcadc100m14b4cha board...
\subsection{Trigger}
Software and/or hardware trigger. Internal or external hardware trigger, polarity selection.
Optional additional delay on the final trigger (in sampling clock ticks).
\begin{figure}[h!]
\includegraphics[width=\textwidth]{figures/trigger_unit.pdf}
......@@ -101,6 +103,7 @@ V\subscript{out} = V\subscript{in} - (gain\subscript{dac} \cdot V\subscript{dac}
\subsection{Time-stamping}
%===============================================================================
\section{Acquisition}
......@@ -137,6 +140,7 @@ V\subscript{out} = V\subscript{in} - (gain\subscript{dac} \cdot V\subscript{dac}
%===============================================================================
\newpage
\section{Calibration}
The calibration is done once during the prodoction tests.
......@@ -145,9 +149,33 @@ The calibration process gives four values per channel and per input range:
ADC gain correction, ADC offset correction, DAC gain correction and DAC offset correction.
The temperature during the calibration process is also measured.
All the calibration values are stored in the FmcAdc100m14b4cha EEPROM.
More precisely they are stored in the "Internal Use Area" as defined in the IPMI standard\footnote{Platform Management FRU Information Storage Definition v1.0}.
Tables \ref{tab:adc_calibr_data_eeprom} and \ref{tab:dac_calibr_data_eeprom} shows the calibration data types and the arrangement in the EEPROM.
The first column "Byte offset" represents the offset within the "Internal Use Area".
The EEPROM holds a sdbfs\footnote{http://www.ohwr.org/attachments/download/1594/sdbfs-2012-09-19.pdf} file system.
In addition to the calibration values, the EEPROM also contains mandatory IPMI\footnote{Platform Management FRU Information Storage Definition v1.0}
records described in the FMC Standard VITA 57.1 (see table \ref{tab:eeprom_sdbfs} for mapping).
\begin{table}[ht]
\centering
\begin{tabularx}{\textwidth}{| l | l | l | X |}
\hline
\textbf{Byte offset} & \textbf{File name} & \textbf{File Type} & \textbf{Description} \\
\hline
0x0 & ipmi.sdb & binary & IPMI records \\
\hline
0x100 & calibration.sdb & binary & Calibration values \\
\hline
0x1000 & . & binary & Directory \\
& & & vendor = 0xCE42 \\
& & & device = 0xC5BE045E \\
\hline
\end{tabularx}
\caption{EEPROM sdbfs}
\label{tab:eeprom_sdbfs}
\end{table}
Note that the vendor value 0xCE42 corresponds to CERN. While the device value 0xC5BE045E corresponds to the first 32-bit of the md5 sum of "fmc-adc-100m14b4cha".
Tables \ref{tab:adc_calibr_data_eeprom} and \ref{tab:dac_calibr_data_eeprom} shows the calibration data types and the arrangement in the binary file.
The first column "Byte offset" represents the offset within the binary file.
\begin{table}[ht]
\centering
......@@ -253,6 +281,13 @@ Below is the pseudo-code to calculate the DAC corrected value, applying gain and
\begin{verbatim}
c_val = ((((val-0x8000+offset) << 15) * gain) >> 30)+0x8000
\end{verbatim}
where:
\begin{verbatim}
c_val = corrected value to write to DAC
val = value from user
offset = DAC offset calibration value from EEPROM
gain = DAC gain calibration value from EEPROM
\end{verbatim}
......
files = ["fmc_adc_100Ms_core.vhd",
"fmc_adc_100Ms_core_pkg.vhd",
"fmc_adc_100Ms_csr.vhd",
"offset_gain_s.vhd"]
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--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Top level entity for Simple PCIe FMC Carrier
-- http://www.ohwr.org/projects/spec
--------------------------------------------------------------------------------
--
-- unit name: fmc_adc_100Ms_core_pkg (fmc_adc_100Ms_core_pkg.vhd)
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 16-11-2012
--
-- version: 1.0
--
-- description: Package for FMC ADC 100Ms/s core
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see svn log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
package fmc_adc_100Ms_core_pkg is
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component fmc_adc_100Ms_core
generic(
g_multishot_ram_size : natural := 2048
);
port (
-- Clock, reset
sys_clk_i : in std_logic;
sys_rst_n_i : in std_logic;
-- CSR wishbone interface
wb_csr_adr_i : in std_logic_vector(4 downto 0);
wb_csr_dat_i : in std_logic_vector(31 downto 0);
wb_csr_dat_o : out std_logic_vector(31 downto 0);
wb_csr_cyc_i : in std_logic;
wb_csr_sel_i : in std_logic_vector(3 downto 0);
wb_csr_stb_i : in std_logic;
wb_csr_we_i : in std_logic;
wb_csr_ack_o : out std_logic;
-- DDR wishbone interface
wb_ddr_clk_i : in std_logic;
wb_ddr_adr_o : out std_logic_vector(31 downto 0);
wb_ddr_dat_o : out std_logic_vector(63 downto 0);
wb_ddr_sel_o : out std_logic_vector(7 downto 0);
wb_ddr_stb_o : out std_logic;
wb_ddr_we_o : out std_logic;
wb_ddr_cyc_o : out std_logic;
wb_ddr_ack_i : in std_logic;
wb_ddr_stall_i : in std_logic;
-- Events output pulses
trigger_p_o : out std_logic;
acq_start_p_o : out std_logic;
acq_stop_p_o : out std_logic;
acq_end_p_o : out std_logic;
-- FMC interface
ext_trigger_p_i : in std_logic; -- External trigger
ext_trigger_n_i : in std_logic;
adc_dco_p_i : in std_logic; -- ADC data clock
adc_dco_n_i : in std_logic;
adc_fr_p_i : in std_logic; -- ADC frame start
adc_fr_n_i : in std_logic;
adc_outa_p_i : in std_logic_vector(3 downto 0); -- ADC serial data (odd bits)
adc_outa_n_i : in std_logic_vector(3 downto 0);
adc_outb_p_i : in std_logic_vector(3 downto 0); -- ADC serial data (even bits)
adc_outb_n_i : in std_logic_vector(3 downto 0);
gpio_dac_clr_n_o : out std_logic; -- offset DACs clear (active low)
gpio_led_acq_o : out std_logic; -- Mezzanine front panel power LED (PWR)
gpio_led_trig_o : out std_logic; -- Mezzanine front panel trigger LED (TRIG)
gpio_ssr_ch1_o : out std_logic_vector(6 downto 0); -- Channel 1 solid state relays control
gpio_ssr_ch2_o : out std_logic_vector(6 downto 0); -- Channel 2 solid state relays control
gpio_ssr_ch3_o : out std_logic_vector(6 downto 0); -- Channel 3 solid state relays control
gpio_ssr_ch4_o : out std_logic_vector(6 downto 0); -- Channel 4 solid state relays control
gpio_si570_oe_o : out std_logic -- Si570 (programmable oscillator) output enable
);
end component fmc_adc_100Ms_core;
end fmc_adc_100Ms_core_pkg;
package body fmc_adc_100Ms_core_pkg is
end fmc_adc_100Ms_core_pkg;
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......@@ -4,13 +4,13 @@ files = [
"utc_core_regs.vhd",
"utc_core.vhd",
"irq_controller_regs.vhd",
"irq_controller.vhd"];
"irq_controller.vhd",
"sdb_meta_pkg.vhd"];
modules = {
"local" : "../../adc/rtl",
"svn" : [ "http://svn.ohwr.org/ddr3-sp6-core/trunk/hdl",
"http://svn.ohwr.org/gn4124-core/trunk/hdl/gn4124core/rtl",
"http://svn.ohwr.org/gn4124-core/trunk/hdl/common/rtl"],
"git" : "git://ohwr.org/hdl-core-lib/general-cores.git"}
"git" : ["git://ohwr.org/hdl-core-lib/general-cores.git::sdb_extension",
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git::spec_bank3_64b_32b",
"git://ohwr.org/hdl-core-lib/gn4124-core.git::master"]}
fetchto="../ip_cores"
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Wed Nov 23 09:30:44 2011
-- Created : Mon Mar 11 17:11:09 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
......@@ -18,7 +18,7 @@ entity carrier_csr is
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(2 downto 0);
wb_addr_i : in std_logic_vector(1 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......@@ -32,10 +32,6 @@ entity carrier_csr is
carrier_csr_carrier_reserved_i : in std_logic_vector(11 downto 0);
-- Port for std_logic_vector field: 'Carrier type' in reg: 'Carrier type and PCB version'
carrier_csr_carrier_type_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Bitstream type' in reg: 'Bitstream type'
carrier_csr_bitstream_type_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Bitstream date' in reg: 'Bitstream date'
carrier_csr_bitstream_date_i : in std_logic_vector(31 downto 0);
-- Port for BIT field: 'FMC presence' in reg: 'Status'
carrier_csr_stat_fmc_pres_i : in std_logic;
-- Port for BIT field: 'GN4142 core P2L PLL status' in reg: 'Status'
......@@ -67,7 +63,7 @@ signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(2 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
......@@ -107,8 +103,8 @@ begin
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(2 downto 0) is
when "000" =>
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
else
rddata_reg(3 downto 0) <= carrier_csr_carrier_pcb_rev_i;
......@@ -117,22 +113,12 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= carrier_csr_bitstream_type_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= carrier_csr_bitstream_date_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011" =>
when "01" =>
if (wb_we_i = '1') then
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
else
rddata_reg(0) <= carrier_csr_stat_fmc_pres_i;
rddata_reg(1) <= carrier_csr_stat_p2l_pll_lck_i;
......@@ -142,10 +128,13 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100" =>
when "10" =>
if (wb_we_i = '1') then
rddata_reg(0) <= 'X';
carrier_csr_ctrl_led_green_int <= wrdata_reg(0);
rddata_reg(1) <= 'X';
carrier_csr_ctrl_led_red_int <= wrdata_reg(1);
rddata_reg(2) <= 'X';
carrier_csr_ctrl_dac_clr_n_int <= wrdata_reg(2);
carrier_csr_ctrl_reserved_int <= wrdata_reg(31 downto 3);
else
......@@ -172,8 +161,6 @@ begin
-- PCB revision
-- Reserved register
-- Carrier type
-- Bitstream type
-- Bitstream date
-- FMC presence
-- GN4142 core P2L PLL status
-- System clock PLL status
......
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
package sdb_meta_pkg is
------------------------------------------------------------------------------
-- Meta-information sdb records
------------------------------------------------------------------------------
-- Top module repository url
constant c_REPO_URL : t_sdb_repo_url := (
-- url (string, 63 char)
repo_url => "git://ohwr.org/fmc-projects/fmc-adc-100m14b4cha.git ");
-- Synthesis informations
constant c_SYNTHESIS : t_sdb_synthesis := (
-- Top module name (string, 16 char)
syn_module_name => "spec_top_fmc_adc",
-- Commit ID (hex string, 128-bit = 32 char)
-- git log -1 --format="%H" | cut -c1-31
syn_commit_id => "150b83db8fa9e0ff9050166b7695ee9a",
-- Synthesis tool name (string, 8 char)
syn_tool_name => "ISE ",
-- Synthesis tool version (bcd encoded, 32-bit)
syn_tool_version => x"00000133",
-- Synthesis date (bcd encoded, 32-bit)
syn_date => x"20130307",
-- Synthesised by (string, 15 char)
syn_username => "mcattin ");
-- Integration record
constant c_INTEGRATION : t_sdb_integration := (
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"47c786a2", -- echo "spec_fmc-adc-100m14b4cha" | md5sum | cut -c1-8
version => x"00010000", -- bcd encoded, [31:16] = major, [15:0] = minor
date => x"20130307", -- yyyymmdd
name => "spec_fmcadc100m14b "));
end sdb_meta_pkg;
package body sdb_meta_pkg is
end sdb_meta_pkg;
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......@@ -165,162 +165,176 @@ wr 0000000020000028 F 00000000
-- DMA length
wr 000000002000002C F 00001000
-- Next item address (lsb)
wr 0000000020000030 F 20000030
wr 0000000020000030 F 20000040
-- Next item address (msb)
wr 0000000020000034 F 00000000
-- DMA attributes (from carrier to host, last item)
wr 0000000020000038 F 00000000
wr 0000000020000038 F 00000001
wait %d2000
-- DMA item stored in host memory
------------------------------
-- Carrier start address
wr 0000000020000040 F 00003000
-- Host start address (lsb)
wr 0000000020000044 F 40003000
-- Host start address (msb)
wr 0000000020000048 F 00000000
-- DMA length
wr 000000002000004C F 00001000
-- Next item address (lsb)
wr 0000000020000050 F 20000060
-- Next item address (msb)
wr 0000000020000054 F 00000000
-- DMA attributes (from carrier to host, last item)
wr 0000000020000058 F 00000001
-- DMA
-- DMA item stored in host memory
------------------------------
-- Carrier start address
wr FF00000000000008 F 00000000
wr 0000000020000060 F 00004000
-- Host start address (lsb)
wr FF0000000000000C F 40000000
wr 0000000020000064 F 40004000
-- Host start address (msb)
wr FF00000000000010 F 00000000
wr 0000000020000068 F 00000000
-- DMA length
wr FF00000000000014 F 00001000
wr 000000002000006C F 00001000
-- Next item address (lsb)
wr FF00000000000018 F 20000000
wr 0000000020000070 F 20000080
-- Next item address (msb)
wr FF0000000000001C F 00000000
wr 0000000020000074 F 00000000
-- DMA attributes (from carrier to host, last item)
wr FF00000000000020 F 00000001
-- Start DMA
--wr FF00000000000000 F 00000001
wr 0000000020000078 F 00000000
wait %d2000
wait %d100
-- onewire config
wr FF000000000A0004 F 007C0270
wr FF00000000001A04 F 007C0270
wait %d100
wr FF000000000A0000 F 0000000A
wr FF00000000001A00 F 0000000A
wait %d100
-- trigger config (sw trig enable)
--wr FF00000000090008 F 00000008
wr FF00000000001908 F 00000008
-- trigger config (hw int trig enable)
--wr FF00000000090008 F 00000004
--wr FF00000000001908 F 00000004
-- trigger config (int trig)
wr FF00000000090008 F 02600004
--wr FF00000000001908 F 02600004
-- decimation factor = 1
wr FF0000000009001C F 00000001
wr FF0000000000191C F 00000001
-- pre-trig samples
wr FF00000000090020 F 0000000A
wr FF00000000001920 F 0000000A
-- post-trig samples
wr FF00000000090024 F 00000100
wr FF00000000001924 F 00000100
-- number of shots
wr FF00000000090014 F 00000001
wr FF00000000001914 F 00000003
-- Channel 1 gain
wr FF00000000090034 F 00008000
wr FF00000000001934 F 00008000
-- Channel 1 offset
wr FF00000000090038 F 00000000
wr FF00000000001938 F 00000000
-- Channel 2 gain
wr FF00000000090044 F 00008000
wr FF00000000001944 F 00008000
-- Channel 2 offset
wr FF00000000090048 F 00000000
wr FF00000000001948 F 00000000
-- Channel 3 gain
wr FF00000000090054 F 00008000
wr FF00000000001954 F 00008000
-- Channel 3 offset
wr FF00000000090058 F 00000000
wr FF00000000001958 F 00000000
-- Channel 4 gain
wr FF00000000090064 F 00008000
wr FF00000000001964 F 00008000
-- Channel 4 offset
wr FF00000000090068 F 00000000
wr FF00000000001968 F 00000000
-- Enable test data and sampling clock
--wr FF00000000090000 F 00000024
wr FF00000000001900 F 00000024
-- Enable sampling clock
wr FF00000000090000 F 00000004
--wr FF00000000001900 F 00000004
-- start acquisition
--wr FF00000000090000 F 00000025
wr FF00000000090000 F 00000005
wr FF00000000001900 F 00000025
--wr FF00000000001900 F 00000005
wait %d800
-- sw trigger
--wr FF00000000090010 F FFFFFFFF
wr FF00000000001910 F FFFFFFFF
--wait %d800
wait %d800
-- sw trigger
--wr FF00000000090010 F FFFFFFFF
wr FF00000000001910 F FFFFFFFF
--wait %d800
wait %d800
-- sw trigger
-wr FF00000000090010 F FFFFFFFF
wr FF00000000001910 F FFFFFFFF
--wait %d800
-- sw trigger
--wr FF00000000090010 F FFFFFFFF
--wr FF00000000001910 F FFFFFFFF
--wait %d800
-- sw trigger
--wr FF00000000090010 F FFFFFFFF
--wr FF00000000001910 F FFFFFFFF
wait %d700
wait %d1000
-- DMA
------------------------------
-- Carrier start address
wr FF00000000000008 F 00000000
wr FF00000000001008 F 00000000
-- Host start address (lsb)
wr FF0000000000000C F 40000000
wr FF0000000000100C F 40000000
-- Host start address (msb)
wr FF00000000000010 F 00000000
wr FF00000000001010 F 00000000
-- DMA length
wr FF00000000000014 F 00001000
wr FF00000000001014 F 00001000
-- Next item address (lsb)
wr FF00000000000018 F 00000000
wr FF00000000001018 F 20000000
-- Next item address (msb)
wr FF0000000000001C F 00000000
wr FF0000000000101C F 00000000
-- DMA attributes (from carrier to host, last item)
wr FF00000000000020 F 00000000
wr FF00000000001020 F 00000001
-- Start DMA
wr FF00000000000000 F 00000001
wr FF00000000001000 F 00000001
wait %d3000
---------------------------------------------
---------------------------------------------
-- start acquisition
wr FF00000000090000 F 00000001
--wr FF00000000001900 F 00000001
wait %d500
-- sw trigger
wr FF00000000090010 F FFFFFFFF
--wr FF00000000001910 F FFFFFFFF
wait %d400
-- DMA
------------------------------
-- Carrier start address
wr FF00000000000008 F 00000000
--wr FF00000000001008 F 00000000
-- Host start address (lsb)
wr FF0000000000000C F 40000000
--wr FF0000000000100C F 40000000
-- Host start address (msb)
wr FF00000000000010 F 00000000
--wr FF00000000001010 F 00000000
-- DMA length
wr FF00000000000014 F 00000200
--wr FF00000000001014 F 00000200
-- Next item address (lsb)
wr FF00000000000018 F 20000000
--wr FF00000000001018 F 20000000
-- Next item address (msb)
wr FF0000000000001C F 00000000
--wr FF0000000000101C F 00000000
-- DMA attributes (from carrier to host, last item)
wr FF00000000000020 F 00000000
--wr FF00000000001020 F 00000000
-- Start DMA
wr FF00000000000000 F 00000001
--wr FF00000000001000 F 00000001
wait %d1000
......@@ -332,49 +346,29 @@ wait %d1000
-- FMC I2C (prescaler)
wr FF00000000080000 F 000000F9
rd FF00000000080000 F 000000F9 FFFFFFFF
--wr FF00000000080000 F 000000F9
--rd FF00000000080000 F 000000F9 FFFFFFFF
wait %d640
-- Carrier CSR (read carrier type and PCB version)
rd FF00000000030000 F 00010001 FFFFFFFF
--rd FF00000000030000 F 00010001 FFFFFFFF
-- Carrier CSR (switch front panel LED ON)
wr FF00000000030010 F 00000003
rd FF00000000030010 F 00000003 FFFFFFFF
--wr FF00000000030010 F 00000003
--rd FF00000000030010 F 00000003 FFFFFFFF
wait %d640
-- FMC SPI (divider = 100)
wr FF00000000070014 F 00000064
--wr FF00000000070014 F 00000064
-- FMC SPI (select ADC)
wr FF00000000070018 F 00000001
--wr FF00000000070018 F 00000001
-- FMC SPI (data)
wr FF00000000070000 F 000081FF
--wr FF00000000070000 F 000081FF
-- FMC SPI (ass, tx_neg, go, len=16)
wr FF00000000070010 F 00002510
--wr FF00000000070010 F 00002510
wait %d300
-- DDR access trough DMA wishbone
wr 0000000020000000 F 00000000
wr 0000000020000004 F 40000000
wr 0000000020000008 F 00000000
-- DMA length
wr 000000002000000C F 000000C0
wr 0000000020000010 F 00000000
wr 0000000020000014 F 00000000
wr 0000000020000018 F 00000000
-- wrb FF00000010004004 F 00000000
wr FF00000000000008 F 00000000
wr FF0000000000000C F 40000000
wr FF00000000000010 F 00000000
-- DMA length
wr FF00000000000014 F 000000C0
wr FF00000000000018 F 20000000
wr FF0000000000001C F 00000000
wr FF00000000000020 F 00000003
wr FF00000000000000 F 00000001
-- Now read back what was just written
-- the following three reads will go out as a single request
......
......@@ -820,7 +820,7 @@
parameter RZQ = 240; // termination resistance
parameter PRE_DEF_PAT = 8'hAA; // value returned during mpr pre-defined pattern readout
parameter STOP_ON_ERROR = 1; // If set to 1, the model will halt on command sequence/major errors
parameter DEBUG = 1; // Turn on Debug messages
parameter DEBUG = 0; // Turn on Debug messages
parameter BUS_DELAY = 0; // delay in nanoseconds
parameter RANDOM_OUT_DELAY = 0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads
parameter RANDOM_SEED = 711689044; //seed value for random generator.
......
......@@ -5,14 +5,15 @@ log -r /*
##do wave_datapath.do
##do wave_multishot.do
##do wave_onewire.do
##do wave_adc_core.do