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FMC ADC 100M 14b 4cha - Gateware
Commit 57a89ed9 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: reverse logic of wishbone masters/slave signal naming on crossbars

parent 540f3fe9
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hdl/rtl/fmc_adc_mezzanine.vhd
View file @ 57a89ed9
...@@ -138,11 +138,11 @@ architecture rtl of fmc_adc_mezzanine is ...@@ -138,11 +138,11 @@ architecture rtl of fmc_adc_mezzanine is
-- SDB crossbar constants declaration -- SDB crossbar constants declaration
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Number of master port(s) on the wishbone crossbar -- Number of masters on the wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 7; constant c_NUM_WB_MASTERS : integer := 1;
-- Number of slave port(s) on the wishbone crossbar -- Number of slaves on the wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 1; constant c_NUM_WB_SLAVES : integer := 7;
-- Wishbone master(s) -- Wishbone master(s)
constant c_WB_MASTER : integer := 0; constant c_WB_MASTER : integer := 0;
...@@ -209,15 +209,15 @@ architecture rtl of fmc_adc_mezzanine is ...@@ -209,15 +209,15 @@ architecture rtl of fmc_adc_mezzanine is
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000"; constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
-- Wishbone crossbar layout -- Wishbone crossbar layout
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(6 downto 0) := constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES - 1 downto 0) :=
( (
0 => f_sdb_embed_device(c_wb_adc_csr_sdb, x"00001000"), c_WB_SLAVE_FMC_ADC => f_sdb_embed_device(c_wb_adc_csr_sdb, x"00001000"),
1 => f_sdb_embed_device(c_xwb_i2c_master_sdb, x"00001400"), c_WB_SLAVE_FMC_SYS_I2C => f_sdb_embed_device(c_xwb_i2c_master_sdb, x"00001400"),
2 => f_sdb_embed_device(c_wb_fmc_adc_eic_sdb, x"00001500"), c_WB_SLAVE_FMC_EIC => f_sdb_embed_device(c_wb_fmc_adc_eic_sdb, x"00001500"),
3 => f_sdb_embed_device(c_xwb_i2c_master_sdb, x"00001600"), c_WB_SLAVE_FMC_I2C => f_sdb_embed_device(c_xwb_i2c_master_sdb, x"00001600"),
4 => f_sdb_embed_device(c_xwb_onewire_master_sdb, x"00001700"), c_WB_SLAVE_FMC_ONEWIRE => f_sdb_embed_device(c_xwb_onewire_master_sdb, x"00001700"),
5 => f_sdb_embed_device(c_xwb_spi_sdb, x"00001800"), c_WB_SLAVE_FMC_SPI => f_sdb_embed_device(c_xwb_spi_sdb, x"00001800"),
6 => f_sdb_embed_device(c_wb_timetag_sdb, x"00001900") c_WB_SLAVE_TIMETAG => f_sdb_embed_device(c_wb_timetag_sdb, x"00001900")
); );
...@@ -225,11 +225,11 @@ architecture rtl of fmc_adc_mezzanine is ...@@ -225,11 +225,11 @@ architecture rtl of fmc_adc_mezzanine is
-- Signals declaration -- Signals declaration
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Wishbone buse(s) from crossbar master port(s) -- Wishbone buse(s) from master(s) to crossbar slave port(s)
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0); signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0); signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
-- Wishbone buse(s) to crossbar slave port(s) -- Wishbone buse(s) from crossbar master port(s) to slave(s)
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0); signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0); signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
...@@ -274,7 +274,7 @@ architecture rtl of fmc_adc_mezzanine is ...@@ -274,7 +274,7 @@ architecture rtl of fmc_adc_mezzanine is
begin begin
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- CSR wishbone crossbar -- Main wishbone crossbar for mezzanine
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Additional register to help timing -- Additional register to help timing
...@@ -284,13 +284,13 @@ begin ...@@ -284,13 +284,13 @@ begin
rst_n_i => sys_rst_n_i, rst_n_i => sys_rst_n_i,
slave_i => wb_csr_slave_i, slave_i => wb_csr_slave_i,
slave_o => wb_csr_slave_o, slave_o => wb_csr_slave_o,
master_i => cnx_slave_out(c_WB_MASTER), master_i => cnx_master_in(c_WB_MASTER),
master_o => cnx_slave_in(c_WB_MASTER)); master_o => cnx_master_out(c_WB_MASTER));
cmp_sdb_crossbar : xwb_sdb_crossbar cmp_sdb_crossbar : xwb_sdb_crossbar
generic map ( generic map (
g_num_masters => c_NUM_WB_SLAVES, g_num_masters => c_NUM_WB_MASTERS,
g_num_slaves => c_NUM_WB_MASTERS, g_num_slaves => c_NUM_WB_SLAVES,
g_registered => TRUE, g_registered => TRUE,
g_wraparound => TRUE, g_wraparound => TRUE,
g_layout => c_INTERCONNECT_LAYOUT, g_layout => c_INTERCONNECT_LAYOUT,
...@@ -298,10 +298,10 @@ begin ...@@ -298,10 +298,10 @@ begin
port map ( port map (
clk_sys_i => sys_clk_i, clk_sys_i => sys_clk_i,
rst_n_i => sys_rst_n_i, rst_n_i => sys_rst_n_i,
slave_i => cnx_slave_in, slave_i => cnx_master_out,
slave_o => cnx_slave_out, slave_o => cnx_master_in,
master_i => cnx_master_in, master_i => cnx_slave_out,
master_o => cnx_master_out); master_o => cnx_slave_in);
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Mezzanine system managment I2C master -- Mezzanine system managment I2C master
...@@ -316,8 +316,8 @@ begin ...@@ -316,8 +316,8 @@ begin
clk_sys_i => sys_clk_i, clk_sys_i => sys_clk_i,
rst_n_i => sys_rst_n_i, rst_n_i => sys_rst_n_i,
slave_i => cnx_master_out(c_WB_SLAVE_FMC_SYS_I2C), slave_i => cnx_slave_in(c_WB_SLAVE_FMC_SYS_I2C),
slave_o => cnx_master_in(c_WB_SLAVE_FMC_SYS_I2C), slave_o => cnx_slave_out(c_WB_SLAVE_FMC_SYS_I2C),
desc_o => open, desc_o => open,
scl_pad_i(0) => sys_scl_in, scl_pad_i(0) => sys_scl_in,
...@@ -349,8 +349,8 @@ begin ...@@ -349,8 +349,8 @@ begin
clk_sys_i => sys_clk_i, clk_sys_i => sys_clk_i,
rst_n_i => sys_rst_n_i, rst_n_i => sys_rst_n_i,
slave_i => cnx_master_out(c_WB_SLAVE_FMC_SPI), slave_i => cnx_slave_in(c_WB_SLAVE_FMC_SPI),
slave_o => cnx_master_in(c_WB_SLAVE_FMC_SPI), slave_o => cnx_slave_out(c_WB_SLAVE_FMC_SPI),
desc_o => open, desc_o => open,
pad_cs_o => spi_ss_t, pad_cs_o => spi_ss_t,
...@@ -393,8 +393,8 @@ begin ...@@ -393,8 +393,8 @@ begin
clk_sys_i => sys_clk_i, clk_sys_i => sys_clk_i,
rst_n_i => sys_rst_n_i, rst_n_i => sys_rst_n_i,
slave_i => cnx_master_out(c_WB_SLAVE_FMC_I2C), slave_i => cnx_slave_in(c_WB_SLAVE_FMC_I2C),
slave_o => cnx_master_in(c_WB_SLAVE_FMC_I2C), slave_o => cnx_slave_out(c_WB_SLAVE_FMC_I2C),
desc_o => open, desc_o => open,
scl_pad_i(0) => si570_scl_in, scl_pad_i(0) => si570_scl_in,
...@@ -427,8 +427,8 @@ begin ...@@ -427,8 +427,8 @@ begin
sys_clk_i => sys_clk_i, sys_clk_i => sys_clk_i,
sys_rst_n_i => sys_rst_n_i, sys_rst_n_i => sys_rst_n_i,
wb_csr_slave_i => cnx_master_out(c_WB_SLAVE_FMC_ADC), wb_csr_slave_i => cnx_slave_in(c_WB_SLAVE_FMC_ADC),
wb_csr_slave_o => cnx_master_in(c_WB_SLAVE_FMC_ADC), wb_csr_slave_o => cnx_slave_out(c_WB_SLAVE_FMC_ADC),
wb_ddr_clk_i => wb_ddr_clk_i, wb_ddr_clk_i => wb_ddr_clk_i,
wb_ddr_rst_n_i => wb_ddr_rst_n_i, wb_ddr_rst_n_i => wb_ddr_rst_n_i,
...@@ -481,8 +481,8 @@ begin ...@@ -481,8 +481,8 @@ begin
clk_sys_i => sys_clk_i, clk_sys_i => sys_clk_i,
rst_n_i => sys_rst_n_i, rst_n_i => sys_rst_n_i,
slave_i => cnx_master_out(c_WB_SLAVE_FMC_ONEWIRE), slave_i => cnx_slave_in(c_WB_SLAVE_FMC_ONEWIRE),
slave_o => cnx_master_in(c_WB_SLAVE_FMC_ONEWIRE), slave_o => cnx_slave_out(c_WB_SLAVE_FMC_ONEWIRE),
desc_o => open, desc_o => open,
owr_pwren_o => open, owr_pwren_o => open,
...@@ -500,23 +500,23 @@ begin ...@@ -500,23 +500,23 @@ begin
port map( port map(
rst_n_i => sys_rst_n_i, rst_n_i => sys_rst_n_i,
clk_sys_i => sys_clk_i, clk_sys_i => sys_clk_i,
wb_adr_i => cnx_master_out(c_WB_SLAVE_FMC_EIC).adr(3 downto 2), -- cnx_master_out.adr is byte address wb_adr_i => cnx_slave_in(c_WB_SLAVE_FMC_EIC).adr(3 downto 2), -- cnx_slave_in.adr is byte address
wb_dat_i => cnx_master_out(c_WB_SLAVE_FMC_EIC).dat, wb_dat_i => cnx_slave_in(c_WB_SLAVE_FMC_EIC).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_FMC_EIC).dat, wb_dat_o => cnx_slave_out(c_WB_SLAVE_FMC_EIC).dat,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_FMC_EIC).cyc, wb_cyc_i => cnx_slave_in(c_WB_SLAVE_FMC_EIC).cyc,
wb_sel_i => cnx_master_out(c_WB_SLAVE_FMC_EIC).sel, wb_sel_i => cnx_slave_in(c_WB_SLAVE_FMC_EIC).sel,
wb_stb_i => cnx_master_out(c_WB_SLAVE_FMC_EIC).stb, wb_stb_i => cnx_slave_in(c_WB_SLAVE_FMC_EIC).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_FMC_EIC).we, wb_we_i => cnx_slave_in(c_WB_SLAVE_FMC_EIC).we,
wb_ack_o => cnx_master_in(c_WB_SLAVE_FMC_EIC).ack, wb_ack_o => cnx_slave_out(c_WB_SLAVE_FMC_EIC).ack,
wb_stall_o => cnx_master_in(c_WB_SLAVE_FMC_EIC).stall, wb_stall_o => cnx_slave_out(c_WB_SLAVE_FMC_EIC).stall,
wb_int_o => eic_irq_o, wb_int_o => eic_irq_o,
irq_trig_i => trigger_p, irq_trig_i => trigger_p,
irq_acq_end_i => acq_end_irq_p irq_acq_end_i => acq_end_irq_p
); );
-- Unused wishbone signals -- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_FMC_EIC).err <= '0'; cnx_slave_out(c_WB_SLAVE_FMC_EIC).err <= '0';
cnx_master_in(c_WB_SLAVE_FMC_EIC).rty <= '0'; cnx_slave_out(c_WB_SLAVE_FMC_EIC).rty <= '0';
-- Detects end of adc core writing to ddr -- Detects end of adc core writing to ddr
p_ddr_wr_fifo_empty : process (sys_clk_i) p_ddr_wr_fifo_empty : process (sys_clk_i)
...@@ -569,19 +569,19 @@ begin ...@@ -569,19 +569,19 @@ begin
trig_tag_o => trigger_tag, trig_tag_o => trigger_tag,
time_trig_o => time_trigger, time_trig_o => time_trigger,
wb_adr_i => cnx_master_out(c_WB_SLAVE_TIMETAG).adr(6 downto 2), -- cnx_master_out.adr is byte address wb_adr_i => cnx_slave_in(c_WB_SLAVE_TIMETAG).adr(6 downto 2), -- cnx_slave_in.adr is byte address
wb_dat_i => cnx_master_out(c_WB_SLAVE_TIMETAG).dat, wb_dat_i => cnx_slave_in(c_WB_SLAVE_TIMETAG).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_TIMETAG).dat, wb_dat_o => cnx_slave_out(c_WB_SLAVE_TIMETAG).dat,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_TIMETAG).cyc, wb_cyc_i => cnx_slave_in(c_WB_SLAVE_TIMETAG).cyc,
wb_sel_i => cnx_master_out(c_WB_SLAVE_TIMETAG).sel, wb_sel_i => cnx_slave_in(c_WB_SLAVE_TIMETAG).sel,
wb_stb_i => cnx_master_out(c_WB_SLAVE_TIMETAG).stb, wb_stb_i => cnx_slave_in(c_WB_SLAVE_TIMETAG).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_TIMETAG).we, wb_we_i => cnx_slave_in(c_WB_SLAVE_TIMETAG).we,
wb_ack_o => cnx_master_in(c_WB_SLAVE_TIMETAG).ack wb_ack_o => cnx_slave_out(c_WB_SLAVE_TIMETAG).ack
); );
-- Unused wishbone signals -- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_TIMETAG).err <= '0'; cnx_slave_out(c_WB_SLAVE_TIMETAG).err <= '0';
cnx_master_in(c_WB_SLAVE_TIMETAG).rty <= '0'; cnx_slave_out(c_WB_SLAVE_TIMETAG).rty <= '0';
cnx_master_in(c_WB_SLAVE_TIMETAG).stall <= '0'; cnx_slave_out(c_WB_SLAVE_TIMETAG).stall <= '0';
end rtl; end rtl;
hdl/top/spec_ref_design/spec_ref_fmc_adc_100Ms.vhd
View file @ 57a89ed9
...@@ -203,11 +203,11 @@ architecture rtl of spec_ref_fmc_adc_100Ms is ...@@ -203,11 +203,11 @@ architecture rtl of spec_ref_fmc_adc_100Ms is
-- SDB crossbar constants declaration -- SDB crossbar constants declaration
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Number of master port(s) on the wishbone crossbar -- Number of masters on the wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 6; constant c_NUM_WB_MASTERS : integer := 1;
-- Number of slave port(s) on the wishbone crossbar -- Number of slaves on the wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 1; constant c_NUM_WB_SLAVES : integer := 6;
-- Wishbone master(s) -- Wishbone master(s)
constant c_MASTER_GENNUM : integer := 0; constant c_MASTER_GENNUM : integer := 0;
...@@ -221,9 +221,9 @@ architecture rtl of spec_ref_fmc_adc_100Ms is ...@@ -221,9 +221,9 @@ architecture rtl of spec_ref_fmc_adc_100Ms is
constant c_WB_SLAVE_WR_CORE : integer := 5; -- WR PTP core constant c_WB_SLAVE_WR_CORE : integer := 5; -- WR PTP core
-- SDB meta info -- SDB meta info
constant c_SDB_GIT_REPO_URL : integer := c_NUM_WB_MASTERS; constant c_SDB_GIT_REPO_URL : integer := c_NUM_WB_SLAVES;
constant c_SDB_SYNTHESIS : integer := c_NUM_WB_MASTERS + 1; constant c_SDB_SYNTHESIS : integer := c_NUM_WB_SLAVES + 1;
constant c_SDB_INTEGRATE : integer := c_NUM_WB_MASTERS + 2; constant c_SDB_INTEGRATE : integer := c_NUM_WB_SLAVES + 2;
-- Devices sdb description -- Devices sdb description
constant c_wb_dma_ctrl_sdb : t_sdb_device := ( constant c_wb_dma_ctrl_sdb : t_sdb_device := (
...@@ -292,7 +292,7 @@ architecture rtl of spec_ref_fmc_adc_100Ms is ...@@ -292,7 +292,7 @@ architecture rtl of spec_ref_fmc_adc_100Ms is
name => "spec_fmcadc100m14b ")); name => "spec_fmcadc100m14b "));
-- Wishbone crossbar layout -- Wishbone crossbar layout
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_MASTERS + 2 downto 0) := constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES + 2 downto 0) :=
( (
c_WB_SLAVE_DMA => f_sdb_embed_device(c_wb_dma_ctrl_sdb, x"00001000"), c_WB_SLAVE_DMA => f_sdb_embed_device(c_wb_dma_ctrl_sdb, x"00001000"),
c_WB_SLAVE_SPEC_CSR => f_sdb_embed_device(c_wb_spec_csr_sdb, x"00001200"), c_WB_SLAVE_SPEC_CSR => f_sdb_embed_device(c_wb_spec_csr_sdb, x"00001200"),
...@@ -372,11 +372,11 @@ architecture rtl of spec_ref_fmc_adc_100Ms is ...@@ -372,11 +372,11 @@ architecture rtl of spec_ref_fmc_adc_100Ms is
signal pll_arst : std_logic; signal pll_arst : std_logic;
signal arst_edge_ppulse : std_logic; signal arst_edge_ppulse : std_logic;
-- Wishbone buse(s) from crossbar master port(s) -- Wishbone buse(s) from master(s) to crossbar slave port(s)
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0); signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0); signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
-- Wishbone buse(s) to crossbar slave port(s) -- Wishbone buse(s) from crossbar master port(s) to slave(s)
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0); signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0); signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
...@@ -734,27 +734,27 @@ begin ...@@ -734,27 +734,27 @@ begin
-- DMA registers wishbone interface (slave classic) -- DMA registers wishbone interface (slave classic)
dma_reg_clk_i => sys_clk_62_5, dma_reg_clk_i => sys_clk_62_5,
dma_reg_adr_i => dma_ctrl_wb_adr, dma_reg_adr_i => dma_ctrl_wb_adr,
dma_reg_dat_i => cnx_master_out(c_WB_SLAVE_DMA).dat, dma_reg_dat_i => cnx_slave_in(c_WB_SLAVE_DMA).dat,
dma_reg_sel_i => cnx_master_out(c_WB_SLAVE_DMA).sel, dma_reg_sel_i => cnx_slave_in(c_WB_SLAVE_DMA).sel,
dma_reg_stb_i => cnx_master_out(c_WB_SLAVE_DMA).stb, dma_reg_stb_i => cnx_slave_in(c_WB_SLAVE_DMA).stb,
dma_reg_we_i => cnx_master_out(c_WB_SLAVE_DMA).we, dma_reg_we_i => cnx_slave_in(c_WB_SLAVE_DMA).we,
dma_reg_cyc_i => cnx_master_out(c_WB_SLAVE_DMA).cyc, dma_reg_cyc_i => cnx_slave_in(c_WB_SLAVE_DMA).cyc,
dma_reg_dat_o => cnx_master_in(c_WB_SLAVE_DMA).dat, dma_reg_dat_o => cnx_slave_out(c_WB_SLAVE_DMA).dat,
dma_reg_ack_o => cnx_master_in(c_WB_SLAVE_DMA).ack, dma_reg_ack_o => cnx_slave_out(c_WB_SLAVE_DMA).ack,
dma_reg_stall_o => cnx_master_in(c_WB_SLAVE_DMA).stall, dma_reg_stall_o => cnx_slave_out(c_WB_SLAVE_DMA).stall,
-- CSR wishbone interface (master pipelined) -- CSR wishbone interface (master pipelined)
csr_clk_i => sys_clk_62_5, csr_clk_i => sys_clk_62_5,
csr_adr_o => gn_wb_adr, csr_adr_o => gn_wb_adr,
csr_dat_o => cnx_slave_in(c_MASTER_GENNUM).dat, csr_dat_o => cnx_master_out(c_MASTER_GENNUM).dat,
csr_sel_o => cnx_slave_in(c_MASTER_GENNUM).sel, csr_sel_o => cnx_master_out(c_MASTER_GENNUM).sel,
csr_stb_o => cnx_slave_in(c_MASTER_GENNUM).stb, csr_stb_o => cnx_master_out(c_MASTER_GENNUM).stb,
csr_we_o => cnx_slave_in(c_MASTER_GENNUM).we, csr_we_o => cnx_master_out(c_MASTER_GENNUM).we,
csr_cyc_o => cnx_slave_in(c_MASTER_GENNUM).cyc, csr_cyc_o => cnx_master_out(c_MASTER_GENNUM).cyc,
csr_dat_i => cnx_slave_out(c_MASTER_GENNUM).dat, csr_dat_i => cnx_master_in(c_MASTER_GENNUM).dat,
csr_ack_i => cnx_slave_out(c_MASTER_GENNUM).ack, csr_ack_i => cnx_master_in(c_MASTER_GENNUM).ack,
csr_stall_i => cnx_slave_out(c_MASTER_GENNUM).stall, csr_stall_i => cnx_master_in(c_MASTER_GENNUM).stall,
csr_err_i => cnx_slave_out(c_MASTER_GENNUM).err, csr_err_i => cnx_master_in(c_MASTER_GENNUM).err,
csr_rty_i => cnx_slave_out(c_MASTER_GENNUM).rty, csr_rty_i => cnx_master_in(c_MASTER_GENNUM).rty,
-- DMA wishbone interface (pipelined) -- DMA wishbone interface (pipelined)
dma_clk_i => sys_clk_62_5, dma_clk_i => sys_clk_62_5,
dma_adr_o => wb_dma_adr, dma_adr_o => wb_dma_adr,
...@@ -773,14 +773,14 @@ begin ...@@ -773,14 +773,14 @@ begin
p2l_pll_locked <= gn4124_status(0); p2l_pll_locked <= gn4124_status(0);
-- Convert 32-bit word address into byte address for crossbar -- Convert 32-bit word address into byte address for crossbar
cnx_slave_in(c_MASTER_GENNUM).adr <= gn_wb_adr(29 downto 0) & "00"; cnx_master_out(c_MASTER_GENNUM).adr <= gn_wb_adr(29 downto 0) & "00";
-- Convert 32-bit byte address into word address for DMA controller -- Convert 32-bit byte address into word address for DMA controller
dma_ctrl_wb_adr <= "00" & cnx_master_out(c_WB_SLAVE_DMA).adr(31 downto 2); dma_ctrl_wb_adr <= "00" & cnx_slave_in(c_WB_SLAVE_DMA).adr(31 downto 2);
-- Unused wishbone signals -- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_DMA).err <= '0'; cnx_slave_out(c_WB_SLAVE_DMA).err <= '0';
cnx_master_in(c_WB_SLAVE_DMA).rty <= '0'; cnx_slave_out(c_WB_SLAVE_DMA).rty <= '0';
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- CSR wishbone crossbar -- CSR wishbone crossbar
...@@ -788,8 +788,8 @@ begin ...@@ -788,8 +788,8 @@ begin
cmp_sdb_crossbar : xwb_sdb_crossbar cmp_sdb_crossbar : xwb_sdb_crossbar
generic map ( generic map (
g_num_masters => c_NUM_WB_SLAVES, g_num_masters => c_NUM_WB_MASTERS,
g_num_slaves => c_NUM_WB_MASTERS, g_num_slaves => c_NUM_WB_SLAVES,
g_registered => TRUE, g_registered => TRUE,
g_wraparound => TRUE, g_wraparound => TRUE,
g_layout => c_INTERCONNECT_LAYOUT, g_layout => c_INTERCONNECT_LAYOUT,
...@@ -797,10 +797,10 @@ begin ...@@ -797,10 +797,10 @@ begin
port map ( port map (
clk_sys_i => sys_clk_62_5, clk_sys_i => sys_clk_62_5,
rst_n_i => sys_rst_62_5_n, rst_n_i => sys_rst_62_5_n,
slave_i => cnx_slave_in, slave_i => cnx_master_out,
slave_o => cnx_slave_out, slave_o => cnx_master_in,
master_i => cnx_master_in, master_i => cnx_slave_out,
master_o => cnx_master_out); master_o => cnx_slave_in);
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- 2x SPI DAC -- 2x SPI DAC
...@@ -877,8 +877,8 @@ begin ...@@ -877,8 +877,8 @@ begin
uart_txd_o => uart_txd_o, uart_txd_o => uart_txd_o,
owr_en_o => wrc_owr_en, owr_en_o => wrc_owr_en,
owr_i => wrc_owr_in, owr_i => wrc_owr_in,
wb_slave_i => cnx_master_out(c_WB_SLAVE_WR_CORE), wb_slave_i => cnx_slave_in(c_WB_SLAVE_WR_CORE),
wb_slave_o => cnx_master_in(c_WB_SLAVE_WR_CORE), wb_slave_o => cnx_slave_out(c_WB_SLAVE_WR_CORE),
tm_link_up_o => tm_link_up, tm_link_up_o => tm_link_up,
tm_time_valid_o => tm_time_valid, tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_tai, tm_tai_o => tm_tai,
...@@ -898,14 +898,14 @@ begin ...@@ -898,14 +898,14 @@ begin
port map( port map(
rst_n_i => sys_rst_62_5_n, rst_n_i => sys_rst_62_5_n,
clk_sys_i => sys_clk_62_5, clk_sys_i => sys_clk_62_5,
wb_adr_i => cnx_master_out(c_WB_SLAVE_SPEC_CSR).adr(3 downto 2), -- cnx_master_out.adr is byte address wb_adr_i => cnx_slave_in(c_WB_SLAVE_SPEC_CSR).adr(3 downto 2), -- cnx_slave_in.adr is byte address
wb_dat_i => cnx_master_out(c_WB_SLAVE_SPEC_CSR).dat, wb_dat_i => cnx_slave_in(c_WB_SLAVE_SPEC_CSR).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_SPEC_CSR).dat, wb_dat_o => cnx_slave_out(c_WB_SLAVE_SPEC_CSR).dat,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_SPEC_CSR).cyc, wb_cyc_i => cnx_slave_in(c_WB_SLAVE_SPEC_CSR).cyc,
wb_sel_i => cnx_master_out(c_WB_SLAVE_SPEC_CSR).sel, wb_sel_i => cnx_slave_in(c_WB_SLAVE_SPEC_CSR).sel,
wb_stb_i => cnx_master_out(c_WB_SLAVE_SPEC_CSR).stb, wb_stb_i => cnx_slave_in(c_WB_SLAVE_SPEC_CSR).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_SPEC_CSR).we, wb_we_i => cnx_slave_in(c_WB_SLAVE_SPEC_CSR).we,
wb_ack_o => cnx_master_in(c_WB_SLAVE_SPEC_CSR).ack, wb_ack_o => cnx_slave_out(c_WB_SLAVE_SPEC_CSR).ack,
wb_stall_o => open, wb_stall_o => open,
regs_i => csr_regin, regs_i => csr_regin,
regs_o => csr_regout); regs_o => csr_regout);
...@@ -921,9 +921,9 @@ begin ...@@ -921,9 +921,9 @@ begin
sw_rst_fmc0 <= csr_regout.rst_fmc0_o; sw_rst_fmc0 <= csr_regout.rst_fmc0_o;
-- Unused wishbone signals -- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_SPEC_CSR).err <= '0'; cnx_slave_out(c_WB_SLAVE_SPEC_CSR).err <= '0';
cnx_master_in(c_WB_SLAVE_SPEC_CSR).rty <= '0'; cnx_slave_out(c_WB_SLAVE_SPEC_CSR).rty <= '0';
cnx_master_in(c_WB_SLAVE_SPEC_CSR).stall <= '0'; cnx_slave_out(c_WB_SLAVE_SPEC_CSR).stall <= '0';
-- SPEC front panel leds -- SPEC front panel leds
led_red_o <= led_red or csr_regout.ctrl_led_red_o; led_red_o <= led_red or csr_regout.ctrl_led_red_o;
...@@ -941,9 +941,9 @@ begin ...@@ -941,9 +941,9 @@ begin
port map ( port map (
clk_sys_i => sys_clk_62_5, clk_sys_i => sys_clk_62_5,
rst_n_i => sys_rst_62_5_n, rst_n_i => sys_rst_62_5_n,
slave_i => cnx_master_out(c_WB_SLAVE_VIC),
slave_o => cnx_master_in(c_WB_SLAVE_VIC),
irqs_i(0) => fmc0_eic_irq, irqs_i(0) => fmc0_eic_irq,
slave_i => cnx_slave_in(c_WB_SLAVE_VIC),
slave_o => cnx_slave_out(c_WB_SLAVE_VIC),
irqs_i(1) => dma_eic_irq, irqs_i(1) => dma_eic_irq,
irq_master_o => irq_to_gn4124); irq_master_o => irq_to_gn4124);
...@@ -954,23 +954,23 @@ begin ...@@ -954,23 +954,23 @@ begin
port map( port map(
rst_n_i => sys_rst_62_5_n, rst_n_i => sys_rst_62_5_n,
clk_sys_i => sys_clk_62_5, clk_sys_i => sys_clk_62_5,
wb_adr_i => cnx_master_out(c_WB_SLAVE_DMA_EIC).adr(3 downto 2), -- cnx_master_out.adr is byte address wb_adr_i => cnx_slave_in(c_WB_SLAVE_DMA_EIC).adr(3 downto 2), -- cnx_slave_in.adr is byte address
wb_dat_i => cnx_master_out(c_WB_SLAVE_DMA_EIC).dat, wb_dat_i => cnx_slave_in(c_WB_SLAVE_DMA_EIC).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_DMA_EIC).dat, wb_dat_o => cnx_slave_out(c_WB_SLAVE_DMA_EIC).dat,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_DMA_EIC).cyc, wb_cyc_i => cnx_slave_in(c_WB_SLAVE_DMA_EIC).cyc,
wb_sel_i => cnx_master_out(c_WB_SLAVE_DMA_EIC).sel, wb_sel_i => cnx_slave_in(c_WB_SLAVE_DMA_EIC).sel,
wb_stb_i => cnx_master_out(c_WB_SLAVE_DMA_EIC).stb, wb_stb_i => cnx_slave_in(c_WB_SLAVE_DMA_EIC).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_DMA_EIC).we, wb_we_i => cnx_slave_in(c_WB_SLAVE_DMA_EIC).we,
wb_ack_o => cnx_master_in(c_WB_SLAVE_DMA_EIC).ack, wb_ack_o => cnx_slave_out(c_WB_SLAVE_DMA_EIC).ack,
wb_stall_o => cnx_master_in(c_WB_SLAVE_DMA_EIC).stall, wb_stall_o => cnx_slave_out(c_WB_SLAVE_DMA_EIC).stall,
wb_int_o => dma_eic_irq, wb_int_o => dma_eic_irq,
irq_dma_done_i => dma_irq(0), irq_dma_done_i => dma_irq(0),
irq_dma_error_i => dma_irq(1) irq_dma_error_i => dma_irq(1)
); );
-- Unused wishbone signals -- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_DMA_EIC).err <= '0'; cnx_slave_out(c_WB_SLAVE_DMA_EIC).err <= '0';
cnx_master_in(c_WB_SLAVE_DMA_EIC).rty <= '0'; cnx_slave_out(c_WB_SLAVE_DMA_EIC).rty <= '0';
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- FMC ADC mezzanine (wb bridge with cross-clocking) -- FMC ADC mezzanine (wb bridge with cross-clocking)
...@@ -990,8 +990,8 @@ begin ...@@ -990,8 +990,8 @@ begin
port map( port map(
slave_clk_i => sys_clk_62_5, slave_clk_i => sys_clk_62_5,
slave_rst_n_i => sys_rst_62_5_n, slave_rst_n_i => sys_rst_62_5_n,
slave_i => cnx_master_out(c_WB_SLAVE_FMC_ADC), slave_i => cnx_slave_in(c_WB_SLAVE_FMC_ADC),
slave_o => cnx_master_in(c_WB_SLAVE_FMC_ADC), slave_o => cnx_slave_out(c_WB_SLAVE_FMC_ADC),
master_clk_i => sys_clk_125, master_clk_i => sys_clk_125,
master_rst_n_i => sys_rst_125_n, master_rst_n_i => sys_rst_125_n,
master_i => cnx_fmc0_sync_master_in, master_i => cnx_fmc0_sync_master_in,
......
hdl/top/svec_ref_design/svec_ref_fmc_adc_100Ms.vhd
View file @ 57a89ed9
...@@ -289,11 +289,11 @@ architecture rtl of svec_ref_fmc_adc_100Ms is ...@@ -289,11 +289,11 @@ architecture rtl of svec_ref_fmc_adc_100Ms is
-- SDB crossbar constants declaration -- SDB crossbar constants declaration
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Number of master port(s) on the wishbone crossbar -- Number of masters on the wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 9; constant c_NUM_WB_MASTERS : integer := 1;
-- Number of slave port(s) on the wishbone crossbar -- Number of slaves on the wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 1; constant c_NUM_WB_SLAVES : integer := 9;
-- Wishbone master(s) -- Wishbone master(s)
constant c_WB_MASTER_VME : integer := 0; constant c_WB_MASTER_VME : integer := 0;
...@@ -310,9 +310,9 @@ architecture rtl of svec_ref_fmc_adc_100Ms is ...@@ -310,9 +310,9 @@ architecture rtl of svec_ref_fmc_adc_100Ms is
constant c_WB_SLAVE_WR_CORE : integer := 8; -- WR PTP core constant c_WB_SLAVE_WR_CORE : integer := 8; -- WR PTP core
-- SDB meta info -- SDB meta info
constant c_SDB_GIT_REPO_URL : integer := c_NUM_WB_MASTERS; constant c_SDB_GIT_REPO_URL : integer := c_NUM_WB_SLAVES;
constant c_SDB_SYNTHESIS : integer := c_NUM_WB_MASTERS + 1; constant c_SDB_SYNTHESIS : integer := c_NUM_WB_SLAVES + 1;
constant c_SDB_INTEGRATE : integer := c_NUM_WB_MASTERS + 2; constant c_SDB_INTEGRATE : integer := c_NUM_WB_SLAVES + 2;
-- Devices sdb description -- Devices sdb description
constant c_wb_svec_csr_sdb : t_sdb_device := ( constant c_wb_svec_csr_sdb : t_sdb_device := (
...@@ -382,7 +382,7 @@ architecture rtl of svec_ref_fmc_adc_100Ms is ...@@ -382,7 +382,7 @@ architecture rtl of svec_ref_fmc_adc_100Ms is
name => "svec_fmcadc100m14b ")); name => "svec_fmcadc100m14b "));
-- Wishbone crossbar layout -- Wishbone crossbar layout
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_MASTERS + 2 downto 0) := constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES + 2 downto 0) :=
( (
c_WB_SLAVE_SVEC_CSR => f_sdb_embed_device(c_wb_svec_csr_sdb, x"00001200"), c_WB_SLAVE_SVEC_CSR => f_sdb_embed_device(c_wb_svec_csr_sdb, x"00001200"),
c_WB_SLAVE_VIC => f_sdb_embed_device(c_xwb_vic_sdb, x"00001300"), c_WB_SLAVE_VIC => f_sdb_embed_device(c_xwb_vic_sdb, x"00001300"),
...@@ -469,11 +469,11 @@ architecture rtl of svec_ref_fmc_adc_100Ms is ...@@ -469,11 +469,11 @@ architecture rtl of svec_ref_fmc_adc_100Ms is
signal vme_irq_n : std_logic_vector(7 downto 1); signal vme_irq_n : std_logic_vector(7 downto 1);
signal vme_access : std_logic; signal vme_access : std_logic;
-- Wishbone buse(s) from crossbar master port(s) -- Wishbone buse(s) from master(s) to crossbar slave port(s)
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0); signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0); signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
-- Wishbone buse(s) to crossbar slave port(s) -- Wishbone buse(s) from crossbar master port(s) to slave(s)
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0); signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0); signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
...@@ -694,8 +694,8 @@ begin ...@@ -694,8 +694,8 @@ begin
vme_o.data_oe_n => vme_data_oe_n_o, vme_o.data_oe_n => vme_data_oe_n_o,
vme_o.addr_dir => vme_addr_dir_int, vme_o.addr_dir => vme_addr_dir_int,
vme_o.addr_oe_n => vme_addr_oe_n_o, vme_o.addr_oe_n => vme_addr_oe_n_o,
wb_o => cnx_slave_in(c_WB_MASTER_VME), wb_o => cnx_master_out(c_WB_MASTER_VME),
wb_i => cnx_slave_out(c_WB_MASTER_VME), wb_i => cnx_master_in(c_WB_MASTER_VME),
int_i => irq_to_vme); int_i => irq_to_vme);
...@@ -716,8 +716,8 @@ begin ...@@ -716,8 +716,8 @@ begin
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
cmp_sdb_crossbar : xwb_sdb_crossbar cmp_sdb_crossbar : xwb_sdb_crossbar
generic map ( generic map (
g_num_masters => c_NUM_WB_SLAVES, g_num_masters => c_NUM_WB_MASTERS,
g_num_slaves => c_NUM_WB_MASTERS, g_num_slaves => c_NUM_WB_SLAVES,
g_registered => TRUE, g_registered => TRUE,
g_wraparound => TRUE, g_wraparound => TRUE,
g_layout => c_INTERCONNECT_LAYOUT, g_layout => c_INTERCONNECT_LAYOUT,
...@@ -725,10 +725,10 @@ begin ...@@ -725,10 +725,10 @@ begin
port map ( port map (
clk_sys_i => clk_sys_62m5, clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n, rst_n_i => rst_sys_62m5_n,
slave_i => cnx_slave_in, slave_i => cnx_master_out,
slave_o => cnx_slave_out, slave_o => cnx_master_in,
master_i => cnx_master_in, master_i => cnx_slave_out,
master_o => cnx_master_out); master_o => cnx_slave_in);
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- White Rabbit Core (SVEC board package) -- White Rabbit Core (SVEC board package)
...@@ -797,8 +797,8 @@ begin ...@@ -797,8 +797,8 @@ begin
spi_ncs_o => spi_ncs_o, spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o, spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i, spi_miso_i => spi_miso_i,
wb_slave_o => cnx_master_in(c_WB_SLAVE_WR_CORE), wb_slave_o => cnx_slave_out(c_WB_SLAVE_WR_CORE),
wb_slave_i => cnx_master_out(c_WB_SLAVE_WR_CORE), wb_slave_i => cnx_slave_in(c_WB_SLAVE_WR_CORE),
tm_link_up_o => tm_link_up, tm_link_up_o => tm_link_up,
tm_time_valid_o => tm_time_valid, tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_tai, tm_tai_o => tm_tai,
...@@ -819,14 +819,14 @@ begin ...@@ -819,14 +819,14 @@ begin
port map( port map(
rst_n_i => rst_sys_62m5_n, rst_n_i => rst_sys_62m5_n,
clk_sys_i => clk_sys_62m5, clk_sys_i => clk_sys_62m5,
wb_adr_i => cnx_master_out(c_WB_SLAVE_SVEC_CSR).adr(3 downto 2), -- cnx_master_out.adr is byte address wb_adr_i => cnx_slave_in(c_WB_SLAVE_SVEC_CSR).adr(3 downto 2), -- cnx_slave_in.adr is byte address
wb_dat_i => cnx_master_out(c_WB_SLAVE_SVEC_CSR).dat, wb_dat_i => cnx_slave_in(c_WB_SLAVE_SVEC_CSR).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_SVEC_CSR).dat, wb_dat_o => cnx_slave_out(c_WB_SLAVE_SVEC_CSR).dat,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_SVEC_CSR).cyc, wb_cyc_i => cnx_slave_in(c_WB_SLAVE_SVEC_CSR).cyc,
wb_sel_i => cnx_master_out(c_WB_SLAVE_SVEC_CSR).sel, wb_sel_i => cnx_slave_in(c_WB_SLAVE_SVEC_CSR).sel,
wb_stb_i => cnx_master_out(c_WB_SLAVE_SVEC_CSR).stb, wb_stb_i => cnx_slave_in(c_WB_SLAVE_SVEC_CSR).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_SVEC_CSR).we, wb_we_i => cnx_slave_in(c_WB_SLAVE_SVEC_CSR).we,
wb_ack_o => cnx_master_in(c_WB_SLAVE_SVEC_CSR).ack, wb_ack_o => cnx_slave_out(c_WB_SLAVE_SVEC_CSR).ack,
wb_stall_o => open, wb_stall_o => open,
regs_i => csr_regin, regs_i => csr_regin,
regs_o => csr_regout); regs_o => csr_regout);
...@@ -845,9 +845,9 @@ begin ...@@ -845,9 +845,9 @@ begin
sw_rst_fmc1 <= csr_regout.rst_fmc1_o; sw_rst_fmc1 <= csr_regout.rst_fmc1_o;
-- Unused wishbone signals -- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_SVEC_CSR).err <= '0'; cnx_slave_out(c_WB_SLAVE_SVEC_CSR).err <= '0';
cnx_master_in(c_WB_SLAVE_SVEC_CSR).rty <= '0'; cnx_slave_out(c_WB_SLAVE_SVEC_CSR).rty <= '0';
cnx_master_in(c_WB_SLAVE_SVEC_CSR).stall <= '0'; cnx_slave_out(c_WB_SLAVE_SVEC_CSR).stall <= '0';
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Vectored interrupt controller (VIC) -- Vectored interrupt controller (VIC)
...@@ -861,10 +861,10 @@ begin ...@@ -861,10 +861,10 @@ begin
port map ( port map (
clk_sys_i => clk_sys_62m5, clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n, rst_n_i => rst_sys_62m5_n,
slave_i => cnx_master_out(c_WB_SLAVE_VIC),
slave_o => cnx_master_in(c_WB_SLAVE_VIC),
irqs_i(0) => fmc_irq(0), irqs_i(0) => fmc_irq(0),
irqs_i(1) => fmc_irq(1), irqs_i(1) => fmc_irq(1),
slave_i => cnx_slave_in(c_WB_SLAVE_VIC),
slave_o => cnx_slave_out(c_WB_SLAVE_VIC),
irq_master_o => irq_to_vme); irq_master_o => irq_to_vme);
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
...@@ -883,8 +883,8 @@ begin ...@@ -883,8 +883,8 @@ begin
port map( port map(
slave_clk_i => clk_sys_62m5, slave_clk_i => clk_sys_62m5,
slave_rst_n_i => rst_sys_62m5_n, slave_rst_n_i => rst_sys_62m5_n,
slave_i => cnx_master_out(c_WB_SLAVE_FMC0_ADC), slave_i => cnx_slave_in(c_WB_SLAVE_FMC0_ADC),
slave_o => cnx_master_in(c_WB_SLAVE_FMC0_ADC), slave_o => cnx_slave_out(c_WB_SLAVE_FMC0_ADC),
master_clk_i => clk_ref_125m, master_clk_i => clk_ref_125m,
master_rst_n_i => fmc0_rst_n, master_rst_n_i => fmc0_rst_n,
master_i => cnx_fmc0_sync_master_in, master_i => cnx_fmc0_sync_master_in,
...@@ -974,8 +974,8 @@ begin ...@@ -974,8 +974,8 @@ begin
port map( port map(
slave_clk_i => clk_sys_62m5, slave_clk_i => clk_sys_62m5,
slave_rst_n_i => rst_sys_62m5_n, slave_rst_n_i => rst_sys_62m5_n,
slave_i => cnx_master_out(c_WB_SLAVE_FMC1_ADC), slave_i => cnx_slave_in(c_WB_SLAVE_FMC1_ADC),
slave_o => cnx_master_in(c_WB_SLAVE_FMC1_ADC), slave_o => cnx_slave_out(c_WB_SLAVE_FMC1_ADC),
master_clk_i => clk_ref_125m, master_clk_i => clk_ref_125m,
master_rst_n_i => fmc1_rst_n, master_rst_n_i => fmc1_rst_n,
master_i => cnx_fmc1_sync_master_in, master_i => cnx_fmc1_sync_master_in,
...@@ -1116,15 +1116,15 @@ begin ...@@ -1116,15 +1116,15 @@ begin
wb1_rst_n_i => rst_sys_62m5_n, wb1_rst_n_i => rst_sys_62m5_n,
wb1_clk_i => clk_sys_62m5, wb1_clk_i => clk_sys_62m5,
wb1_sel_i => cnx_master_out(c_WB_SLAVE_FMC0_DDR_DAT).sel, wb1_sel_i => cnx_slave_in(c_WB_SLAVE_FMC0_DDR_DAT).sel,
wb1_cyc_i => cnx_master_out(c_WB_SLAVE_FMC0_DDR_DAT).cyc, wb1_cyc_i => cnx_slave_in(c_WB_SLAVE_FMC0_DDR_DAT).cyc,
wb1_stb_i => cnx_master_out(c_WB_SLAVE_FMC0_DDR_DAT).stb, wb1_stb_i => cnx_slave_in(c_WB_SLAVE_FMC0_DDR_DAT).stb,
wb1_we_i => cnx_master_out(c_WB_SLAVE_FMC0_DDR_DAT).we, wb1_we_i => cnx_slave_in(c_WB_SLAVE_FMC0_DDR_DAT).we,
wb1_addr_i => std_logic_vector(ddr0_addr_cnt), wb1_addr_i => std_logic_vector(ddr0_addr_cnt),
wb1_data_i => cnx_master_out(c_WB_SLAVE_FMC0_DDR_DAT).dat, wb1_data_i => cnx_slave_in(c_WB_SLAVE_FMC0_DDR_DAT).dat,
wb1_data_o => cnx_master_in(c_WB_SLAVE_FMC0_DDR_DAT).dat, wb1_data_o => cnx_slave_out(c_WB_SLAVE_FMC0_DDR_DAT).dat,
wb1_ack_o => cnx_master_in(c_WB_SLAVE_FMC0_DDR_DAT).ack, wb1_ack_o => cnx_slave_out(c_WB_SLAVE_FMC0_DDR_DAT).ack,
wb1_stall_o => cnx_master_in(c_WB_SLAVE_FMC0_DDR_DAT).stall, wb1_stall_o => cnx_slave_out(c_WB_SLAVE_FMC0_DDR_DAT).stall,
p1_cmd_empty_o => open, p1_cmd_empty_o => open,
p1_cmd_full_o => open, p1_cmd_full_o => open,
...@@ -1158,12 +1158,12 @@ begin ...@@ -1158,12 +1158,12 @@ begin
if (rst_sys_62m5_n = '0' or sw_rst_fmc0 = '1') then if (rst_sys_62m5_n = '0' or sw_rst_fmc0 = '1') then
ddr0_dat_cyc_d <= '0'; ddr0_dat_cyc_d <= '0';
else else
ddr0_dat_cyc_d <= cnx_master_out(c_WB_SLAVE_FMC0_DDR_DAT).cyc; ddr0_dat_cyc_d <= cnx_slave_in(c_WB_SLAVE_FMC0_DDR_DAT).cyc;
end if; end if;
end if; end if;
end process p_ddr0_dat_cyc; end process p_ddr0_dat_cyc;
ddr0_addr_cnt_en <= not(cnx_master_out(c_WB_SLAVE_FMC0_DDR_DAT).cyc) and ddr0_dat_cyc_d; ddr0_addr_cnt_en <= not(cnx_slave_in(c_WB_SLAVE_FMC0_DDR_DAT).cyc) and ddr0_dat_cyc_d;
-- address counter -- address counter
p_ddr0_addr_cnt : process (clk_sys_62m5) p_ddr0_addr_cnt : process (clk_sys_62m5)
...@@ -1171,10 +1171,10 @@ begin ...@@ -1171,10 +1171,10 @@ begin
if rising_edge(clk_sys_62m5) then if rising_edge(clk_sys_62m5) then
if (rst_sys_62m5_n = '0' or sw_rst_fmc0 = '1') then if (rst_sys_62m5_n = '0' or sw_rst_fmc0 = '1') then
ddr0_addr_cnt <= (others => '0'); ddr0_addr_cnt <= (others => '0');
elsif (cnx_master_out(c_WB_SLAVE_FMC0_DDR_ADR).we = '1' and elsif (cnx_slave_in(c_WB_SLAVE_FMC0_DDR_ADR).we = '1' and
cnx_master_out(c_WB_SLAVE_FMC0_DDR_ADR).stb = '1' and cnx_slave_in(c_WB_SLAVE_FMC0_DDR_ADR).stb = '1' and
cnx_master_out(c_WB_SLAVE_FMC0_DDR_ADR).cyc = '1') then cnx_slave_in(c_WB_SLAVE_FMC0_DDR_ADR).cyc = '1') then
ddr0_addr_cnt <= unsigned(cnx_master_out(c_WB_SLAVE_FMC0_DDR_ADR).dat); ddr0_addr_cnt <= unsigned(cnx_slave_in(c_WB_SLAVE_FMC0_DDR_ADR).dat);
elsif (ddr0_addr_cnt_en = '1') then elsif (ddr0_addr_cnt_en = '1') then
ddr0_addr_cnt <= ddr0_addr_cnt + 1; ddr0_addr_cnt <= ddr0_addr_cnt + 1;
end if; end if;
...@@ -1186,25 +1186,25 @@ begin ...@@ -1186,25 +1186,25 @@ begin
begin begin
if rising_edge(clk_sys_62m5) then if rising_edge(clk_sys_62m5) then
if (rst_sys_62m5_n = '0' or sw_rst_fmc0 = '1') then if (rst_sys_62m5_n = '0' or sw_rst_fmc0 = '1') then
cnx_master_in(c_WB_SLAVE_FMC0_DDR_ADR).ack <= '0'; cnx_slave_out(c_WB_SLAVE_FMC0_DDR_ADR).ack <= '0';
elsif (cnx_master_out(c_WB_SLAVE_FMC0_DDR_ADR).stb = '1' and elsif (cnx_slave_in(c_WB_SLAVE_FMC0_DDR_ADR).stb = '1' and
cnx_master_out(c_WB_SLAVE_FMC0_DDR_ADR).cyc = '1') then cnx_slave_in(c_WB_SLAVE_FMC0_DDR_ADR).cyc = '1') then
cnx_master_in(c_WB_SLAVE_FMC0_DDR_ADR).ack <= '1'; cnx_slave_out(c_WB_SLAVE_FMC0_DDR_ADR).ack <= '1';
else else
cnx_master_in(c_WB_SLAVE_FMC0_DDR_ADR).ack <= '0'; cnx_slave_out(c_WB_SLAVE_FMC0_DDR_ADR).ack <= '0';
end if; end if;
end if; end if;
end process p_ddr0_addr_ack; end process p_ddr0_addr_ack;
-- Address counter read back -- Address counter read back
cnx_master_in(c_WB_SLAVE_FMC0_DDR_ADR).dat <= std_logic_vector(ddr0_addr_cnt); cnx_slave_out(c_WB_SLAVE_FMC0_DDR_ADR).dat <= std_logic_vector(ddr0_addr_cnt);
-- Unused wishbone signals -- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_FMC0_DDR_DAT).err <= '0'; cnx_slave_out(c_WB_SLAVE_FMC0_DDR_DAT).err <= '0';
cnx_master_in(c_WB_SLAVE_FMC0_DDR_DAT).rty <= '0'; cnx_slave_out(c_WB_SLAVE_FMC0_DDR_DAT).rty <= '0';
cnx_master_in(c_WB_SLAVE_FMC0_DDR_ADR).err <= '0'; cnx_slave_out(c_WB_SLAVE_FMC0_DDR_ADR).err <= '0';
cnx_master_in(c_WB_SLAVE_FMC0_DDR_ADR).rty <= '0'; cnx_slave_out(c_WB_SLAVE_FMC0_DDR_ADR).rty <= '0';
cnx_master_in(c_WB_SLAVE_FMC0_DDR_ADR).stall <= '0'; cnx_slave_out(c_WB_SLAVE_FMC0_DDR_ADR).stall <= '0';
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- DDR1 controller (bank 5) -- DDR1 controller (bank 5)
...@@ -1273,15 +1273,15 @@ begin ...@@ -1273,15 +1273,15 @@ begin
wb1_rst_n_i => rst_sys_62m5_n, wb1_rst_n_i => rst_sys_62m5_n,
wb1_clk_i => clk_sys_62m5, wb1_clk_i => clk_sys_62m5,
wb1_sel_i => cnx_master_out(c_WB_SLAVE_FMC1_DDR_DAT).sel, wb1_sel_i => cnx_slave_in(c_WB_SLAVE_FMC1_DDR_DAT).sel,
wb1_cyc_i => cnx_master_out(c_WB_SLAVE_FMC1_DDR_DAT).cyc, wb1_cyc_i => cnx_slave_in(c_WB_SLAVE_FMC1_DDR_DAT).cyc,
wb1_stb_i => cnx_master_out(c_WB_SLAVE_FMC1_DDR_DAT).stb, wb1_stb_i => cnx_slave_in(c_WB_SLAVE_FMC1_DDR_DAT).stb,
wb1_we_i => cnx_master_out(c_WB_SLAVE_FMC1_DDR_DAT).we, wb1_we_i => cnx_slave_in(c_WB_SLAVE_FMC1_DDR_DAT).we,
wb1_addr_i => std_logic_vector(ddr1_addr_cnt), wb1_addr_i => std_logic_vector(ddr1_addr_cnt),
wb1_data_i => cnx_master_out(c_WB_SLAVE_FMC1_DDR_DAT).dat, wb1_data_i => cnx_slave_in(c_WB_SLAVE_FMC1_DDR_DAT).dat,
wb1_data_o => cnx_master_in(c_WB_SLAVE_FMC1_DDR_DAT).dat, wb1_data_o => cnx_slave_out(c_WB_SLAVE_FMC1_DDR_DAT).dat,
wb1_ack_o => cnx_master_in(c_WB_SLAVE_FMC1_DDR_DAT).ack, wb1_ack_o => cnx_slave_out(c_WB_SLAVE_FMC1_DDR_DAT).ack,
wb1_stall_o => cnx_master_in(c_WB_SLAVE_FMC1_DDR_DAT).stall, wb1_stall_o => cnx_slave_out(c_WB_SLAVE_FMC1_DDR_DAT).stall,
p1_cmd_empty_o => open, p1_cmd_empty_o => open,
p1_cmd_full_o => open, p1_cmd_full_o => open,
...@@ -1315,12 +1315,12 @@ begin ...@@ -1315,12 +1315,12 @@ begin
if (rst_sys_62m5_n = '0' or sw_rst_fmc1 = '1') then if (rst_sys_62m5_n = '0' or sw_rst_fmc1 = '1') then
ddr1_dat_cyc_d <= '0'; ddr1_dat_cyc_d <= '0';
else else
ddr1_dat_cyc_d <= cnx_master_out(c_WB_SLAVE_FMC1_DDR_DAT).cyc; ddr1_dat_cyc_d <= cnx_slave_in(c_WB_SLAVE_FMC1_DDR_DAT).cyc;
end if; end if;
end if; end if;
end process p_ddr1_dat_cyc; end process p_ddr1_dat_cyc;
ddr1_addr_cnt_en <= not(cnx_master_out(c_WB_SLAVE_FMC1_DDR_DAT).cyc) and ddr1_dat_cyc_d; ddr1_addr_cnt_en <= not(cnx_slave_in(c_WB_SLAVE_FMC1_DDR_DAT).cyc) and ddr1_dat_cyc_d;
-- address counter -- address counter
p_ddr1_addr_cnt : process (clk_sys_62m5) p_ddr1_addr_cnt : process (clk_sys_62m5)
...@@ -1328,10 +1328,10 @@ begin ...@@ -1328,10 +1328,10 @@ begin
if rising_edge(clk_sys_62m5) then if rising_edge(clk_sys_62m5) then
if (rst_sys_62m5_n = '0' or sw_rst_fmc1 = '1') then if (rst_sys_62m5_n = '0' or sw_rst_fmc1 = '1') then
ddr1_addr_cnt <= (others => '0'); ddr1_addr_cnt <= (others => '0');
elsif (cnx_master_out(c_WB_SLAVE_FMC1_DDR_ADR).we = '1' and elsif (cnx_slave_in(c_WB_SLAVE_FMC1_DDR_ADR).we = '1' and
cnx_master_out(c_WB_SLAVE_FMC1_DDR_ADR).stb = '1' and cnx_slave_in(c_WB_SLAVE_FMC1_DDR_ADR).stb = '1' and
cnx_master_out(c_WB_SLAVE_FMC1_DDR_ADR).cyc = '1') then cnx_slave_in(c_WB_SLAVE_FMC1_DDR_ADR).cyc = '1') then
ddr1_addr_cnt <= unsigned(cnx_master_out(c_WB_SLAVE_FMC1_DDR_ADR).dat); ddr1_addr_cnt <= unsigned(cnx_slave_in(c_WB_SLAVE_FMC1_DDR_ADR).dat);
elsif (ddr1_addr_cnt_en = '1') then elsif (ddr1_addr_cnt_en = '1') then
ddr1_addr_cnt <= ddr1_addr_cnt + 1; ddr1_addr_cnt <= ddr1_addr_cnt + 1;
end if; end if;
...@@ -1343,25 +1343,25 @@ begin ...@@ -1343,25 +1343,25 @@ begin
begin begin
if rising_edge(clk_sys_62m5) then if rising_edge(clk_sys_62m5) then
if (rst_sys_62m5_n = '0' or sw_rst_fmc1 = '1') then if (rst_sys_62m5_n = '0' or sw_rst_fmc1 = '1') then
cnx_master_in(c_WB_SLAVE_FMC1_DDR_ADR).ack <= '0'; cnx_slave_out(c_WB_SLAVE_FMC1_DDR_ADR).ack <= '0';
elsif (cnx_master_out(c_WB_SLAVE_FMC1_DDR_ADR).stb = '1' and elsif (cnx_slave_in(c_WB_SLAVE_FMC1_DDR_ADR).stb = '1' and
cnx_master_out(c_WB_SLAVE_FMC1_DDR_ADR).cyc = '1') then cnx_slave_in(c_WB_SLAVE_FMC1_DDR_ADR).cyc = '1') then
cnx_master_in(c_WB_SLAVE_FMC1_DDR_ADR).ack <= '1'; cnx_slave_out(c_WB_SLAVE_FMC1_DDR_ADR).ack <= '1';
else else
cnx_master_in(c_WB_SLAVE_FMC1_DDR_ADR).ack <= '0'; cnx_slave_out(c_WB_SLAVE_FMC1_DDR_ADR).ack <= '0';
end if; end if;
end if; end if;
end process p_ddr1_addr_ack; end process p_ddr1_addr_ack;
-- Address counter read back -- Address counter read back
cnx_master_in(c_WB_SLAVE_FMC1_DDR_ADR).dat <= std_logic_vector(ddr1_addr_cnt); cnx_slave_out(c_WB_SLAVE_FMC1_DDR_ADR).dat <= std_logic_vector(ddr1_addr_cnt);
-- Unused wishbone signals -- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_FMC1_DDR_DAT).err <= '0'; cnx_slave_out(c_WB_SLAVE_FMC1_DDR_DAT).err <= '0';
cnx_master_in(c_WB_SLAVE_FMC1_DDR_DAT).rty <= '0'; cnx_slave_out(c_WB_SLAVE_FMC1_DDR_DAT).rty <= '0';
cnx_master_in(c_WB_SLAVE_FMC1_DDR_ADR).err <= '0'; cnx_slave_out(c_WB_SLAVE_FMC1_DDR_ADR).err <= '0';
cnx_master_in(c_WB_SLAVE_FMC1_DDR_ADR).rty <= '0'; cnx_slave_out(c_WB_SLAVE_FMC1_DDR_ADR).rty <= '0';
cnx_master_in(c_WB_SLAVE_FMC1_DDR_ADR).stall <= '0'; cnx_slave_out(c_WB_SLAVE_FMC1_DDR_ADR).stall <= '0';
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Carrier front panel LEDs and LEMOs -- Carrier front panel LEDs and LEMOs
......
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