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FMC ADC 100M 14b 4cha - Gateware
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FMC ADC 100M 14b 4cha - Gateware
Commits
5a05ec75
Commit
5a05ec75
authored
Jul 31, 2019
by
Dimitris Lampridis
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[sw] generate cheby C headers
parent
3501364d
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5 changed files
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566 additions
and
2 deletions
+566
-2
Makefile
hdl/rtl/Makefile
+5
-2
fmc_adc_100Ms_csr.h
software/include/hw/fmc_adc_100Ms_csr.h
+351
-0
fmc_adc_alt_trigin.h
software/include/hw/fmc_adc_alt_trigin.h
+32
-0
fmc_adc_alt_trigout.h
software/include/hw/fmc_adc_alt_trigout.h
+40
-0
timetag_core_regs.h
software/include/hw/timetag_core_regs.h
+138
-0
No files found.
hdl/rtl/Makefile
View file @
5a05ec75
SIM
=
../testbench/include
DOC
=
../../doc/manual
SW
=
../../software/include/hw
SOURCES
=
$
(
wildcard
*
.cheby
)
TARGETS
=
$
(
SOURCES:.cheby
=
.vhd
)
...
...
@@ -11,5 +12,7 @@ all: $(TARGETS)
$(TARGETS)
:
%.vhd : %.cheby
@
echo
"
\n\0
33[34m
\0
33[1m-> Processing file
$<
\0
33[0m"
@
cheby
-i
$<
--gen-hdl
=
$@
@
cheby
-i
$<
--doc
=
md
--gen-doc
=
$(DOC)
/
$
(
@:.vhd
=
.adoc
)
@
cheby
-i
$<
--gen-consts
=
$(SIM)
/
$
(
@:.vhd
=
.v
)
@
cheby
-i
$<
\
--doc
=
md
--gen-doc
=
$(DOC)
/
$
(
@:.vhd
=
.adoc
)
\
--gen-consts
=
$(SIM)
/
$
(
@:.vhd
=
.v
)
\
--gen-c
=
$(SW)
/
$
(
@:.vhd
=
.h
)
software/include/hw/fmc_adc_100Ms_csr.h
0 → 100644
View file @
5a05ec75
This diff is collapsed.
Click to expand it.
software/include/hw/fmc_adc_alt_trigin.h
0 → 100644
View file @
5a05ec75
#ifndef __CHEBY__ALT_TRIGIN__H__
#define __CHEBY__ALT_TRIGIN__H__
/* Core version */
#define ALT_TRIGIN_VERSION 0x0UL
#define ALT_TRIGIN_VERSION_PRESET 0xadc10001UL
/* Control register */
#define ALT_TRIGIN_CTRL 0x4UL
#define ALT_TRIGIN_CTRL_ENABLE 0x1UL
/* Time (seconds) to trigger */
#define ALT_TRIGIN_SECONDS 0x8UL
/* Time (cycles) to trigger */
#define ALT_TRIGIN_CYCLES 0x10UL
struct
alt_trigin
{
/* [0x0]: REG (ro) Core version */
uint32_t
version
;
/* [0x4]: REG (rw) Control register */
uint32_t
ctrl
;
/* [0x8]: REG (rw) Time (seconds) to trigger */
uint64_t
seconds
;
/* [0x10]: REG (rw) Time (cycles) to trigger */
uint32_t
cycles
;
};
#endif
/* __CHEBY__ALT_TRIGIN__H__ */
software/include/hw/fmc_adc_alt_trigout.h
0 → 100644
View file @
5a05ec75
#ifndef __CHEBY__ALT_TRIGOUT__H__
#define __CHEBY__ALT_TRIGOUT__H__
/* Status register */
#define ALT_TRIGOUT_STATUS 0x0UL
#define ALT_TRIGOUT_WR_ENABLE 0x1UL
#define ALT_TRIGOUT_WR_LINK 0x2UL
#define ALT_TRIGOUT_WR_VALID 0x4UL
#define ALT_TRIGOUT_TS_PRESENT 0x100UL
/* Time (seconds) of the last event */
#define ALT_TRIGOUT_TS_MASK_SEC 0x8UL
#define ALT_TRIGOUT_TS_SEC_MASK 0xffffffffffULL
#define ALT_TRIGOUT_TS_SEC_SHIFT 0
#define ALT_TRIGOUT_CH1_MASK 0x1000000000000ULL
#define ALT_TRIGOUT_CH2_MASK 0x2000000000000ULL
#define ALT_TRIGOUT_CH3_MASK 0x4000000000000ULL
#define ALT_TRIGOUT_CH4_MASK 0x8000000000000ULL
#define ALT_TRIGOUT_EXT_MASK 0x100000000000000ULL
/* Cycles part of timestamp fifo. */
#define ALT_TRIGOUT_TS_CYCLES 0x10UL
#define ALT_TRIGOUT_CYCLES_MASK 0xfffffffUL
#define ALT_TRIGOUT_CYCLES_SHIFT 0
struct
alt_trigout
{
/* [0x0]: REG (ro) Status register */
uint32_t
status
;
/* padding to: 2 words */
uint32_t
__padding_0
[
1
];
/* [0x8]: REG (ro) Time (seconds) of the last event */
uint64_t
ts_mask_sec
;
/* [0x10]: REG (ro) Cycles part of timestamp fifo. */
uint32_t
ts_cycles
;
};
#endif
/* __CHEBY__ALT_TRIGOUT__H__ */
software/include/hw/timetag_core_regs.h
0 → 100644
View file @
5a05ec75
#ifndef __CHEBY__TIMETAG_CORE_REGS__H__
#define __CHEBY__TIMETAG_CORE_REGS__H__
/* Timetag seconds register (upper) */
#define TIMETAG_CORE_REGS_SECONDS_UPPER 0x0UL
#define TIMETAG_CORE_REGS_SECONDS_UPPER_MASK 0xffUL
#define TIMETAG_CORE_REGS_SECONDS_UPPER_SHIFT 0
/* Timetag seconds register (lower) */
#define TIMETAG_CORE_REGS_SECONDS_LOWER 0x4UL
/* Timetag coarse time register, system clock ticks (125MHz) */
#define TIMETAG_CORE_REGS_COARSE 0x8UL
#define TIMETAG_CORE_REGS_COARSE_MASK 0xfffffffUL
#define TIMETAG_CORE_REGS_COARSE_SHIFT 0
/* Time trigger seconds register (upper) */
#define TIMETAG_CORE_REGS_TIME_TRIG_SECONDS_UPPER 0xcUL
#define TIMETAG_CORE_REGS_TIME_TRIG_SECONDS_UPPER_MASK 0xffUL
#define TIMETAG_CORE_REGS_TIME_TRIG_SECONDS_UPPER_SHIFT 0
/* Time trigger seconds register (lower) */
#define TIMETAG_CORE_REGS_TIME_TRIG_SECONDS_LOWER 0x10UL
/* Time trigger coarse time register, system clock ticks (125MHz) */
#define TIMETAG_CORE_REGS_TIME_TRIG_COARSE 0x14UL
#define TIMETAG_CORE_REGS_TIME_TRIG_COARSE_MASK 0xfffffffUL
#define TIMETAG_CORE_REGS_TIME_TRIG_COARSE_SHIFT 0
/* Trigger time-tag seconds register (upper) */
#define TIMETAG_CORE_REGS_TRIG_TAG_SECONDS_UPPER 0x18UL
#define TIMETAG_CORE_REGS_TRIG_TAG_SECONDS_UPPER_MASK 0xffUL
#define TIMETAG_CORE_REGS_TRIG_TAG_SECONDS_UPPER_SHIFT 0
/* Trigger time-tag seconds register (lower) */
#define TIMETAG_CORE_REGS_TRIG_TAG_SECONDS_LOWER 0x1cUL
/* Trigger time-tag coarse time (system clock ticks 125MHz) register */
#define TIMETAG_CORE_REGS_TRIG_TAG_COARSE 0x20UL
#define TIMETAG_CORE_REGS_TRIG_TAG_COARSE_MASK 0xfffffffUL
#define TIMETAG_CORE_REGS_TRIG_TAG_COARSE_SHIFT 0
/* Acquisition start time-tag seconds register (upper) */
#define TIMETAG_CORE_REGS_ACQ_START_TAG_SECONDS_UPPER 0x24UL
#define TIMETAG_CORE_REGS_ACQ_START_TAG_SECONDS_UPPER_MASK 0xffUL
#define TIMETAG_CORE_REGS_ACQ_START_TAG_SECONDS_UPPER_SHIFT 0
/* Acquisition start time-tag seconds register (lower) */
#define TIMETAG_CORE_REGS_ACQ_START_TAG_SECONDS_LOWER 0x28UL
/* Acquisition start time-tag coarse time (system clock ticks 125MHz) register */
#define TIMETAG_CORE_REGS_ACQ_START_TAG_COARSE 0x2cUL
#define TIMETAG_CORE_REGS_ACQ_START_TAG_COARSE_MASK 0xfffffffUL
#define TIMETAG_CORE_REGS_ACQ_START_TAG_COARSE_SHIFT 0
/* Acquisition stop time-tag seconds register (upper) */
#define TIMETAG_CORE_REGS_ACQ_STOP_TAG_SECONDS_UPPER 0x30UL
#define TIMETAG_CORE_REGS_ACQ_STOP_TAG_SECONDS_UPPER_MASK 0xffUL
#define TIMETAG_CORE_REGS_ACQ_STOP_TAG_SECONDS_UPPER_SHIFT 0
/* Acquisition stop time-tag seconds register (lower) */
#define TIMETAG_CORE_REGS_ACQ_STOP_TAG_SECONDS_LOWER 0x34UL
/* Acquisition stop time-tag coarse time (system clock ticks 125MHz) register */
#define TIMETAG_CORE_REGS_ACQ_STOP_TAG_COARSE 0x38UL
#define TIMETAG_CORE_REGS_ACQ_STOP_TAG_COARSE_MASK 0xfffffffUL
#define TIMETAG_CORE_REGS_ACQ_STOP_TAG_COARSE_SHIFT 0
/* Acquisition end time-tag seconds register (upper) */
#define TIMETAG_CORE_REGS_ACQ_END_TAG_SECONDS_UPPER 0x3cUL
#define TIMETAG_CORE_REGS_ACQ_END_TAG_SECONDS_UPPER_MASK 0xffUL
#define TIMETAG_CORE_REGS_ACQ_END_TAG_SECONDS_UPPER_SHIFT 0
/* Acquisition end time-tag seconds register (lower) */
#define TIMETAG_CORE_REGS_ACQ_END_TAG_SECONDS_LOWER 0x40UL
/* Acquisition end time-tag coarse time (system clock ticks 125MHz) register */
#define TIMETAG_CORE_REGS_ACQ_END_TAG_COARSE 0x44UL
#define TIMETAG_CORE_REGS_ACQ_END_TAG_COARSE_MASK 0xfffffffUL
#define TIMETAG_CORE_REGS_ACQ_END_TAG_COARSE_SHIFT 0
struct
timetag_core_regs
{
/* [0x0]: REG (rw) Timetag seconds register (upper) */
uint32_t
seconds_upper
;
/* [0x4]: REG (rw) Timetag seconds register (lower) */
uint32_t
seconds_lower
;
/* [0x8]: REG (rw) Timetag coarse time register, system clock ticks (125MHz) */
uint32_t
coarse
;
/* [0xc]: REG (rw) Time trigger seconds register (upper) */
uint32_t
time_trig_seconds_upper
;
/* [0x10]: REG (rw) Time trigger seconds register (lower) */
uint32_t
time_trig_seconds_lower
;
/* [0x14]: REG (rw) Time trigger coarse time register, system clock ticks (125MHz) */
uint32_t
time_trig_coarse
;
/* [0x18]: REG (ro) Trigger time-tag seconds register (upper) */
uint32_t
trig_tag_seconds_upper
;
/* [0x1c]: REG (ro) Trigger time-tag seconds register (lower) */
uint32_t
trig_tag_seconds_lower
;
/* [0x20]: REG (ro) Trigger time-tag coarse time (system clock ticks 125MHz) register */
uint32_t
trig_tag_coarse
;
/* [0x24]: REG (ro) Acquisition start time-tag seconds register (upper) */
uint32_t
acq_start_tag_seconds_upper
;
/* [0x28]: REG (ro) Acquisition start time-tag seconds register (lower) */
uint32_t
acq_start_tag_seconds_lower
;
/* [0x2c]: REG (ro) Acquisition start time-tag coarse time (system clock ticks 125MHz) register */
uint32_t
acq_start_tag_coarse
;
/* [0x30]: REG (ro) Acquisition stop time-tag seconds register (upper) */
uint32_t
acq_stop_tag_seconds_upper
;
/* [0x34]: REG (ro) Acquisition stop time-tag seconds register (lower) */
uint32_t
acq_stop_tag_seconds_lower
;
/* [0x38]: REG (ro) Acquisition stop time-tag coarse time (system clock ticks 125MHz) register */
uint32_t
acq_stop_tag_coarse
;
/* [0x3c]: REG (ro) Acquisition end time-tag seconds register (upper) */
uint32_t
acq_end_tag_seconds_upper
;
/* [0x40]: REG (ro) Acquisition end time-tag seconds register (lower) */
uint32_t
acq_end_tag_seconds_lower
;
/* [0x44]: REG (ro) Acquisition end time-tag coarse time (system clock ticks 125MHz) register */
uint32_t
acq_end_tag_coarse
;
};
#endif
/* __CHEBY__TIMETAG_CORE_REGS__H__ */
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