Replace coregen-generated ADC serdes with own implementation.
This is done in order to: a) Stop using an extra PLL for the ADC serdes and follow the clocking scheme proposed in UG382, v1.10, page 32, Figure 1-15. b) Decouple the LTC2174-specific code, as a first step to a more generalized acquisition core. c) Not distribute coregen-generated sources.
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hdl/platform/Manifest.py
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