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FMC ADC 100M 14b 4cha - Gateware
Commit 6dee5c3b authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: introduced new hardware trigger source based on time

parent f2c83354
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doc/manual/fmc_adc_100Ms_csr.tex
View file @ 6dee5c3b
......@@ -218,41 +218,36 @@ Acquisition configuration status
@regsection @code{trig_cfg} - Trigger configuration
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@item @code{1...0}
@tab R/W @tab
@code{HW_TRIG_SEL}
@tab @code{0} @tab
Hardware trigger selection
@item @code{1}
@item @code{2}
@tab R/W @tab
@code{HW_TRIG_POL}
@tab @code{0} @tab
Hardware trigger polarity
@item @code{2}
@item @code{3}
@tab R/W @tab
@code{HW_TRIG_EN}
@tab @code{0} @tab
Hardware trigger enable
@item @code{3}
@item @code{4}
@tab R/W @tab
@code{SW_TRIG_EN}
@tab @code{0} @tab
Software trigger enable
@item @code{5...4}
@item @code{6...5}
@tab R/W @tab
@code{INT_TRIG_SEL}
@tab @code{0} @tab
Channel selection for internal trigger
@item @code{6}
@item @code{7}
@tab R/W @tab
@code{INT_TRIG_TEST_EN}
@tab @code{0} @tab
Enable internal trigger test mode
@item @code{7}
@tab R/W @tab
@code{RESERVED}
@tab @code{0} @tab
Reserved
@item @code{15...8}
@tab R/W @tab
@code{INT_TRIG_THRES_FILT}
......@@ -266,13 +261,12 @@ Threshold for internal trigger
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{hw_trig_sel} @tab 0: internal (data threshold)@*1: external (front panel trigger input)
@item @code{hw_trig_sel} @tab 00: internal (data threshold)@*01: external (front panel trigger input)@*10: trigger from timetag core@*11: reserved (for WR message-based trigger)
@item @code{hw_trig_pol} @tab 0: positive edge/slope@*1: negative edge/slope
@item @code{hw_trig_en} @tab 0: disable@*1: enable
@item @code{sw_trig_en} @tab 0: disable@*1: enable
@item @code{int_trig_sel} @tab 00: channel 1@*01: channel 2@*10: channel 3@*11: channel 4
@item @code{int_trig_test_en} @tab Test mode:@* ch1 = Channel 1 input(analogue)@* ch2 = Channel input over threshold (digital)@* ch3 = Channel input over threshold filtered (digital)@* ch4 = Trigger (digital)
@item @code{reserved} @tab Ignore on read, write with 0's
@item @code{int_trig_thres_filt} @tab Configures the internal trigger threshold glitch filter length.
@item @code{int_trig_thres} @tab Treated as binary two's complement and compared to raw ADC data.
@end multitable
......
doc/manual/timetag_core_regs.tex
View file @ 6dee5c3b
......@@ -15,49 +15,61 @@ REG @tab
Timetag coarse time register, system clock ticks (125MHz)
@item @code{0xc} @tab
REG @tab
@code{time_trig_seconds_upper} @tab
Time trigger seconds register (upper)
@item @code{0x10} @tab
REG @tab
@code{time_trig_seconds_lower} @tab
Timetag seconds register (lower)
@item @code{0x14} @tab
REG @tab
@code{time_trig_coarse} @tab
Timetag coarse time register, system clock ticks (125MHz)
@item @code{0x18} @tab
REG @tab
@code{trig_tag_seconds_upper} @tab
Trigger time-tag seconds register (upper)
@item @code{0x10} @tab
@item @code{0x1c} @tab
REG @tab
@code{trig_tag_seconds_lower} @tab
Trigger time-tag seconds register (lower)
@item @code{0x14} @tab
@item @code{0x20} @tab
REG @tab
@code{trig_tag_coarse} @tab
Trigger time-tag coarse time (system clock ticks 125MHz) register
@item @code{0x18} @tab
@item @code{0x24} @tab
REG @tab
@code{acq_start_tag_seconds_upper} @tab
Acquisition start time-tag seconds register (upper)
@item @code{0x1c} @tab
@item @code{0x28} @tab
REG @tab
@code{acq_start_tag_seconds_lower} @tab
Acquisition start time-tag seconds register (lower)
@item @code{0x20} @tab
@item @code{0x2c} @tab
REG @tab
@code{acq_start_tag_coarse} @tab
Acquisition start time-tag coarse time (system clock ticks 125MHz) register
@item @code{0x24} @tab
@item @code{0x30} @tab
REG @tab
@code{acq_stop_tag_seconds_upper} @tab
Acquisition stop time-tag seconds register (upper)
@item @code{0x28} @tab
@item @code{0x34} @tab
REG @tab
@code{acq_stop_tag_seconds_lower} @tab
Acquisition stop time-tag seconds register (lower)
@item @code{0x2c} @tab
@item @code{0x38} @tab
REG @tab
@code{acq_stop_tag_coarse} @tab
Acquisition stop time-tag coarse time (system clock ticks 125MHz) register
@item @code{0x30} @tab
@item @code{0x3c} @tab
REG @tab
@code{acq_end_tag_seconds_upper} @tab
Acquisition end time-tag seconds register (upper)
@item @code{0x34} @tab
@item @code{0x40} @tab
REG @tab
@code{acq_end_tag_seconds_lower} @tab
Acquisition end time-tag seconds register (lower)
@item @code{0x38} @tab
@item @code{0x44} @tab
REG @tab
@code{acq_end_tag_coarse} @tab
Acquisition end time-tag coarse time (system clock ticks 125MHz) register
......@@ -92,6 +104,36 @@ Coarse time counter clocked by 125MHz system clock.@*Counts from 0 to 125000000.
@tab @code{X} @tab
Timetag coarse time
@end multitable
@regsection @code{time_trig_seconds_upper} - Time trigger seconds register (upper)
8 upper bits of seconds used for timer trigger.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{7...0}
@tab R/W @tab
@code{TIME_TRIG_SECONDS_UPPER}
@tab @code{0} @tab
Time trigger seconds
@end multitable
@regsection @code{time_trig_seconds_lower} - Timetag seconds register (lower)
32 lower bits of seconds used for time trigger.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/W @tab
@code{TIME_TRIG_SECONDS_LOWER}
@tab @code{0} @tab
Time trigger seconds
@end multitable
@regsection @code{time_trig_coarse} - Timetag coarse time register, system clock ticks (125MHz)
Coarse time counter clocked by 125MHz system clock.@*Counts from 0 to 125000000.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{27...0}
@tab R/W @tab
@code{TIME_TRIG_COARSE}
@tab @code{0} @tab
Time trigger coarse value
@end multitable
@regsection @code{trig_tag_seconds_upper} - Trigger time-tag seconds register (upper)
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
......
hdl/adc/rtl/fmc_adc_100Ms_core.vhd
View file @ 6dee5c3b
......@@ -9,7 +9,7 @@
-- Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-02-24
-- Last update: 2016-06-08
-- Last update: 2016-06-15
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: FMC ADC 100Ms/s core.
......@@ -88,8 +88,9 @@ entity fmc_adc_100Ms_core is
acq_stop_p_o : out std_logic;
acq_end_p_o : out std_logic;
-- Trigger time-tag input
trigger_tag_i : t_timetag;
-- Trigger time-tag inputs
trigger_tag_i : in t_timetag;
time_trig_i : in std_logic;
-- FMC interface
ext_trigger_p_i : in std_logic; -- External trigger
......@@ -174,13 +175,12 @@ architecture rtl of fmc_adc_100Ms_core is
fmc_adc_core_sta_serdes_pll_i : in std_logic;
fmc_adc_core_sta_serdes_synced_i : in std_logic;
fmc_adc_core_sta_acq_cfg_i : in std_logic;
fmc_adc_core_trig_cfg_hw_trig_sel_o : out std_logic;
fmc_adc_core_trig_cfg_hw_trig_sel_o : out std_logic_vector(1 downto 0);
fmc_adc_core_trig_cfg_hw_trig_pol_o : out std_logic;
fmc_adc_core_trig_cfg_hw_trig_en_o : out std_logic;
fmc_adc_core_trig_cfg_sw_trig_en_o : out std_logic;
fmc_adc_core_trig_cfg_int_trig_sel_o : out std_logic_vector(1 downto 0);
fmc_adc_core_trig_cfg_int_trig_test_en_o : out std_logic;
fmc_adc_core_trig_cfg_reserved_o : out std_logic;
fmc_adc_core_trig_cfg_int_trig_thres_filt_o : out std_logic_vector(7 downto 0);
fmc_adc_core_trig_cfg_int_trig_thres_o : out std_logic_vector(15 downto 0);
fmc_adc_core_trig_dly_o : out std_logic_vector(31 downto 0);
......@@ -320,6 +320,7 @@ architecture rtl of fmc_adc_100Ms_core is
-- Trigger
signal ext_trig_a : std_logic;
signal ext_trig : std_logic;
signal time_trig : std_logic;
signal int_trig : std_logic;
signal int_trig_over_thres : std_logic;
signal int_trig_over_thres_d : std_logic;
......@@ -333,7 +334,7 @@ architecture rtl of fmc_adc_100Ms_core is
signal hw_trig_pol : std_logic;
signal hw_trig : std_logic;
signal hw_trig_t : std_logic;
signal hw_trig_sel : std_logic;
signal hw_trig_sel : std_logic_vector(1 downto 0);
signal hw_trig_en : std_logic;
signal sw_trig : std_logic;
signal sw_trig_t : std_logic;
......@@ -757,7 +758,6 @@ begin
fmc_adc_core_trig_cfg_sw_trig_en_o => sw_trig_en,
fmc_adc_core_trig_cfg_int_trig_sel_o => int_trig_sel,
fmc_adc_core_trig_cfg_int_trig_test_en_o => int_trig_test_en,
fmc_adc_core_trig_cfg_reserved_o => open,
fmc_adc_core_trig_cfg_int_trig_thres_filt_o => int_trig_thres_filt,
fmc_adc_core_trig_cfg_int_trig_thres_o => int_trig_thres,
fmc_adc_core_trig_dly_o => trig_delay,
......@@ -825,7 +825,7 @@ begin
);
-- External hardware trigger synchronization
cmp_trig_sync : ext_pulse_sync
cmp_ext_trig_sync : ext_pulse_sync
generic map(
g_MIN_PULSE_WIDTH => 1, -- clk_i ticks
g_CLK_FREQUENCY => 100, -- MHz
......@@ -841,6 +841,23 @@ begin
pulse_o => ext_trig
);
-- Time trigger synchronization (from 125MHz timetag core)
cmp_time_trig_sync : ext_pulse_sync
generic map(
g_MIN_PULSE_WIDTH => 1, -- clk_i ticks
g_CLK_FREQUENCY => 100, -- MHz
g_OUTPUT_POLARITY => '0', -- positive pulse
g_OUTPUT_RETRIG => FALSE,
g_OUTPUT_LENGTH => 1 -- clk_i tick
)
port map(
rst_n_i => fs_rst_n,
clk_i => fs_clk,
input_polarity_i => hw_trig_pol,
pulse_i => time_trig_i,
pulse_o => time_trig
);
-- Internal hardware trigger
int_trig_data <= data_calibr_out(15 downto 0) when int_trig_sel = "00" else -- CH1 selected
data_calibr_out(31 downto 16) when int_trig_sel = "01" else -- CH2 selected
......@@ -889,9 +906,16 @@ begin
not(int_trig_over_thres_filt) and int_trig_over_thres_filt_d; -- negative slope
-- Hardware trigger selection
-- internal = adc data threshold
-- external = pulse from front panel
hw_trig_t <= ext_trig when hw_trig_sel = '1' else int_trig;
-- 00: internal = adc data threshold
-- 01: external = pulse from front panel
-- 10: time = time trigger
-- 11: reserved = (for WR message-based interrupts)
with hw_trig_sel select
hw_trig_t <=
int_trig when "00",
ext_trig when "01",
time_trig when "10",
'0' when others;
-- Hardware trigger enable
hw_trig <= hw_trig_t and hw_trig_en;
......@@ -1047,7 +1071,7 @@ begin
trig_tst & int_trig_over_thres_filt_tst &
int_trig_over_thres_tst &
data_calibr_out_d(3)(15 downto 0)) when int_trig_test_en = '1' else
(trig_align & data_calibr_out_d(3)) when hw_trig_sel = '0' else
(trig_align & data_calibr_out_d(3)) when hw_trig_sel = "00" else
(trig_align & data_calibr_out);
-- FOR DEBUG: FR instead of CH1 and SerDes Synced instead of CH2
......
hdl/adc/rtl/fmc_adc_100Ms_core_pkg.vhd
View file @ 6dee5c3b
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- FMC ADC 100Ms/s core package
-- http://www.ohwr.org/projects/fmc-adc-100m14b4cha
--------------------------------------------------------------------------------
--
-- unit name: fmc_adc_100Ms_core_pkg (fmc_adc_100Ms_core_pkg.vhd)
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 16-11-2012
--
-- version: 1.0
--
-- description: Package for FMC ADC 100Ms/s core
--
-- dependencies:
--
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Title : FMC ADC 100Ms/s core package
-- Project : FMC ADC 100M 14B 4CHA gateware
-- URL : http://www.ohwr.org/projects/fmc-adc-100m14b4cha-gw
-------------------------------------------------------------------------------
-- File : fmc_adc_100Ms_core_pkg.vhd
-- Author(s) : Matthieu Cattin <matthieu.cattin@cern.ch>
-- Theodor Stana <t.stana@cern.ch>
-- Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2012-11-16
-- Last update: 2016-06-15
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Package for FMC ADC 100Ms/s core.
-------------------------------------------------------------------------------
-- Copyright (c) 2011-2016 CERN (BE-CO-HT)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
......@@ -28,11 +27,11 @@
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see svn log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2012-11-16 1.0 Matthieu Cattin
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
......@@ -88,10 +87,11 @@ package fmc_adc_100Ms_core_pkg is
acq_end_p_o : out std_logic;
-- Trigger time-tag input
trigger_tag_i : t_timetag;
trigger_tag_i : in t_timetag;
time_trig_i : in std_logic;
-- FMC interface
ext_trigger_p_i : in std_logic; -- External trigger
ext_trigger_p_i : in std_logic; -- External trigger
ext_trigger_n_i : in std_logic;
adc_dco_p_i : in std_logic; -- ADC data clock
......@@ -103,14 +103,14 @@ package fmc_adc_100Ms_core_pkg is
adc_outb_p_i : in std_logic_vector(3 downto 0); -- ADC serial data (even bits)
adc_outb_n_i : in std_logic_vector(3 downto 0);
gpio_dac_clr_n_o : out std_logic; -- offset DACs clear (active low)
gpio_led_acq_o : out std_logic; -- Mezzanine front panel power LED (PWR)
gpio_led_trig_o : out std_logic; -- Mezzanine front panel trigger LED (TRIG)
gpio_dac_clr_n_o : out std_logic; -- offset DACs clear (active low)
gpio_led_acq_o : out std_logic; -- Mezzanine front panel power LED (PWR)
gpio_led_trig_o : out std_logic; -- Mezzanine front panel trigger LED (TRIG)
gpio_ssr_ch1_o : out std_logic_vector(6 downto 0); -- Channel 1 solid state relays control
gpio_ssr_ch2_o : out std_logic_vector(6 downto 0); -- Channel 2 solid state relays control
gpio_ssr_ch3_o : out std_logic_vector(6 downto 0); -- Channel 3 solid state relays control
gpio_ssr_ch4_o : out std_logic_vector(6 downto 0); -- Channel 4 solid state relays control
gpio_si570_oe_o : out std_logic -- Si570 (programmable oscillator) output enable
gpio_si570_oe_o : out std_logic -- Si570 (programmable oscillator) output enable
);
end component fmc_adc_100Ms_core;
......
hdl/adc/rtl/fmc_adc_100Ms_csr.vhd
View file @ 6dee5c3b
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/fmc_adc_100Ms_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Created : Mon Apr 18 16:09:20 2016
-- Created : Thu Jun 16 15:16:07 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -51,8 +51,8 @@ entity fmc_adc_100Ms_csr is
fmc_adc_core_sta_serdes_synced_i : in std_logic;
-- Port for BIT field: 'Acquisition configuration status' in reg: 'Status register'
fmc_adc_core_sta_acq_cfg_i : in std_logic;
-- Port for asynchronous (clock: fs_clk_i) BIT field: 'Hardware trigger selection' in reg: 'Trigger configuration'
fmc_adc_core_trig_cfg_hw_trig_sel_o : out std_logic;
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Hardware trigger selection' in reg: 'Trigger configuration'
fmc_adc_core_trig_cfg_hw_trig_sel_o : out std_logic_vector(1 downto 0);
-- Port for asynchronous (clock: fs_clk_i) BIT field: 'Hardware trigger polarity' in reg: 'Trigger configuration'
fmc_adc_core_trig_cfg_hw_trig_pol_o : out std_logic;
-- Port for asynchronous (clock: fs_clk_i) BIT field: 'Hardware trigger enable' in reg: 'Trigger configuration'
......@@ -63,8 +63,6 @@ entity fmc_adc_100Ms_csr is
fmc_adc_core_trig_cfg_int_trig_sel_o : out std_logic_vector(1 downto 0);
-- Port for asynchronous (clock: fs_clk_i) BIT field: 'Enable internal trigger test mode' in reg: 'Trigger configuration'
fmc_adc_core_trig_cfg_int_trig_test_en_o : out std_logic;
-- Port for BIT field: 'Reserved' in reg: 'Trigger configuration'
fmc_adc_core_trig_cfg_reserved_o : out std_logic;
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Internal trigger threshold glitch filter' in reg: 'Trigger configuration'
fmc_adc_core_trig_cfg_int_trig_thres_filt_o : out std_logic_vector(7 downto 0);
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Threshold for internal trigger' in reg: 'Trigger configuration'
......@@ -147,9 +145,12 @@ signal fmc_adc_core_ctl_man_bitslip_sync2 : std_logic ;
signal fmc_adc_core_ctl_test_data_en_int : std_logic ;
signal fmc_adc_core_ctl_trig_led_int : std_logic ;
signal fmc_adc_core_ctl_acq_led_int : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_sel_int : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_sel_sync0 : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_sel_sync1 : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_sel_int : std_logic_vector(1 downto 0);
signal fmc_adc_core_trig_cfg_hw_trig_sel_swb : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_sel_swb_delay : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_sel_swb_s0 : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_sel_swb_s1 : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_sel_swb_s2 : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_pol_int : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_pol_sync0 : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_pol_sync1 : std_logic ;
......@@ -168,7 +169,6 @@ signal fmc_adc_core_trig_cfg_int_trig_sel_swb_s2 : std_logic ;
signal fmc_adc_core_trig_cfg_int_trig_test_en_int : std_logic ;
signal fmc_adc_core_trig_cfg_int_trig_test_en_sync0 : std_logic ;
signal fmc_adc_core_trig_cfg_int_trig_test_en_sync1 : std_logic ;
signal fmc_adc_core_trig_cfg_reserved_int : std_logic ;
signal fmc_adc_core_trig_cfg_int_trig_thres_filt_int : std_logic_vector(7 downto 0);
signal fmc_adc_core_trig_cfg_int_trig_thres_filt_swb : std_logic ;
signal fmc_adc_core_trig_cfg_int_trig_thres_filt_swb_delay : std_logic ;
......@@ -282,7 +282,9 @@ begin
fmc_adc_core_ctl_test_data_en_int <= '0';
fmc_adc_core_ctl_trig_led_int <= '0';
fmc_adc_core_ctl_acq_led_int <= '0';
fmc_adc_core_trig_cfg_hw_trig_sel_int <= '0';
fmc_adc_core_trig_cfg_hw_trig_sel_int <= "00";
fmc_adc_core_trig_cfg_hw_trig_sel_swb <= '0';
fmc_adc_core_trig_cfg_hw_trig_sel_swb_delay <= '0';
fmc_adc_core_trig_cfg_hw_trig_pol_int <= '0';
fmc_adc_core_trig_cfg_hw_trig_en_int <= '0';
fmc_adc_core_trig_cfg_sw_trig_en_int <= '0';
......@@ -290,7 +292,6 @@ begin
fmc_adc_core_trig_cfg_int_trig_sel_swb <= '0';
fmc_adc_core_trig_cfg_int_trig_sel_swb_delay <= '0';
fmc_adc_core_trig_cfg_int_trig_test_en_int <= '0';
fmc_adc_core_trig_cfg_reserved_int <= '0';
fmc_adc_core_trig_cfg_int_trig_thres_filt_int <= "00000000";
fmc_adc_core_trig_cfg_int_trig_thres_filt_swb <= '0';
fmc_adc_core_trig_cfg_int_trig_thres_filt_swb_delay <= '0';
......@@ -349,6 +350,8 @@ begin
fmc_adc_core_ctl_fsm_cmd_wr_o <= '0';
fmc_adc_core_ctl_man_bitslip_int <= fmc_adc_core_ctl_man_bitslip_int_delay;
fmc_adc_core_ctl_man_bitslip_int_delay <= '0';
fmc_adc_core_trig_cfg_hw_trig_sel_swb <= fmc_adc_core_trig_cfg_hw_trig_sel_swb_delay;
fmc_adc_core_trig_cfg_hw_trig_sel_swb_delay <= '0';
fmc_adc_core_trig_cfg_int_trig_sel_swb <= fmc_adc_core_trig_cfg_int_trig_sel_swb_delay;
fmc_adc_core_trig_cfg_int_trig_sel_swb_delay <= '0';
fmc_adc_core_trig_cfg_int_trig_thres_filt_swb <= fmc_adc_core_trig_cfg_int_trig_thres_filt_swb_delay;
......@@ -475,15 +478,16 @@ begin
ack_in_progress <= '1';
when "000010" =>
if (wb_we_i = '1') then
fmc_adc_core_trig_cfg_hw_trig_sel_int <= wrdata_reg(0);
fmc_adc_core_trig_cfg_hw_trig_pol_int <= wrdata_reg(1);
fmc_adc_core_trig_cfg_hw_trig_en_int <= wrdata_reg(2);
fmc_adc_core_trig_cfg_sw_trig_en_int <= wrdata_reg(3);
fmc_adc_core_trig_cfg_int_trig_sel_int <= wrdata_reg(5 downto 4);
fmc_adc_core_trig_cfg_hw_trig_sel_int <= wrdata_reg(1 downto 0);
fmc_adc_core_trig_cfg_hw_trig_sel_swb <= '1';
fmc_adc_core_trig_cfg_hw_trig_sel_swb_delay <= '1';
fmc_adc_core_trig_cfg_hw_trig_pol_int <= wrdata_reg(2);
fmc_adc_core_trig_cfg_hw_trig_en_int <= wrdata_reg(3);
fmc_adc_core_trig_cfg_sw_trig_en_int <= wrdata_reg(4);
fmc_adc_core_trig_cfg_int_trig_sel_int <= wrdata_reg(6 downto 5);
fmc_adc_core_trig_cfg_int_trig_sel_swb <= '1';
fmc_adc_core_trig_cfg_int_trig_sel_swb_delay <= '1';
fmc_adc_core_trig_cfg_int_trig_test_en_int <= wrdata_reg(6);
fmc_adc_core_trig_cfg_reserved_int <= wrdata_reg(7);
fmc_adc_core_trig_cfg_int_trig_test_en_int <= wrdata_reg(7);
fmc_adc_core_trig_cfg_int_trig_thres_filt_int <= wrdata_reg(15 downto 8);
fmc_adc_core_trig_cfg_int_trig_thres_filt_swb <= '1';
fmc_adc_core_trig_cfg_int_trig_thres_filt_swb_delay <= '1';
......@@ -491,13 +495,12 @@ begin
fmc_adc_core_trig_cfg_int_trig_thres_swb <= '1';
fmc_adc_core_trig_cfg_int_trig_thres_swb_delay <= '1';
end if;
rddata_reg(0) <= fmc_adc_core_trig_cfg_hw_trig_sel_int;
rddata_reg(1) <= fmc_adc_core_trig_cfg_hw_trig_pol_int;
rddata_reg(2) <= fmc_adc_core_trig_cfg_hw_trig_en_int;
rddata_reg(3) <= fmc_adc_core_trig_cfg_sw_trig_en_int;
rddata_reg(5 downto 4) <= fmc_adc_core_trig_cfg_int_trig_sel_int;
rddata_reg(6) <= fmc_adc_core_trig_cfg_int_trig_test_en_int;
rddata_reg(7) <= fmc_adc_core_trig_cfg_reserved_int;
rddata_reg(1 downto 0) <= fmc_adc_core_trig_cfg_hw_trig_sel_int;
rddata_reg(2) <= fmc_adc_core_trig_cfg_hw_trig_pol_int;
rddata_reg(3) <= fmc_adc_core_trig_cfg_hw_trig_en_int;
rddata_reg(4) <= fmc_adc_core_trig_cfg_sw_trig_en_int;
rddata_reg(6 downto 5) <= fmc_adc_core_trig_cfg_int_trig_sel_int;
rddata_reg(7) <= fmc_adc_core_trig_cfg_int_trig_test_en_int;
rddata_reg(15 downto 8) <= fmc_adc_core_trig_cfg_int_trig_thres_filt_int;
rddata_reg(31 downto 16) <= fmc_adc_core_trig_cfg_int_trig_thres_int;
ack_sreg(3) <= '1';
......@@ -1204,17 +1207,21 @@ begin
-- SerDes synchronization status
-- Acquisition configuration status
-- Hardware trigger selection
-- synchronizer chain for field : Hardware trigger selection (type RW/RO, clk_sys_i <-> fs_clk_i)
-- asynchronous std_logic_vector register : Hardware trigger selection (type RW/RO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_core_trig_cfg_hw_trig_sel_o <= '0';
fmc_adc_core_trig_cfg_hw_trig_sel_sync0 <= '0';
fmc_adc_core_trig_cfg_hw_trig_sel_sync1 <= '0';
fmc_adc_core_trig_cfg_hw_trig_sel_swb_s0 <= '0';
fmc_adc_core_trig_cfg_hw_trig_sel_swb_s1 <= '0';
fmc_adc_core_trig_cfg_hw_trig_sel_swb_s2 <= '0';
fmc_adc_core_trig_cfg_hw_trig_sel_o <= "00";
elsif rising_edge(fs_clk_i) then
fmc_adc_core_trig_cfg_hw_trig_sel_sync0 <= fmc_adc_core_trig_cfg_hw_trig_sel_int;
fmc_adc_core_trig_cfg_hw_trig_sel_sync1 <= fmc_adc_core_trig_cfg_hw_trig_sel_sync0;
fmc_adc_core_trig_cfg_hw_trig_sel_o <= fmc_adc_core_trig_cfg_hw_trig_sel_sync1;
fmc_adc_core_trig_cfg_hw_trig_sel_swb_s0 <= fmc_adc_core_trig_cfg_hw_trig_sel_swb;
fmc_adc_core_trig_cfg_hw_trig_sel_swb_s1 <= fmc_adc_core_trig_cfg_hw_trig_sel_swb_s0;
fmc_adc_core_trig_cfg_hw_trig_sel_swb_s2 <= fmc_adc_core_trig_cfg_hw_trig_sel_swb_s1;
if ((fmc_adc_core_trig_cfg_hw_trig_sel_swb_s2 = '0') and (fmc_adc_core_trig_cfg_hw_trig_sel_swb_s1 = '1')) then
fmc_adc_core_trig_cfg_hw_trig_sel_o <= fmc_adc_core_trig_cfg_hw_trig_sel_int;
end if;
end if;
end process;
......@@ -1303,8 +1310,6 @@ begin
end process;
-- Reserved
fmc_adc_core_trig_cfg_reserved_o <= fmc_adc_core_trig_cfg_reserved_int;
-- Internal trigger threshold glitch filter
-- asynchronous std_logic_vector register : Internal trigger threshold glitch filter (type RW/RO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
......
hdl/adc/rtl/fmc_adc_mezzanine.vhd
View file @ 6dee5c3b
......@@ -8,7 +8,7 @@
-- Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2013-05-07
-- Last update: 2016-06-09
-- Last update: 2016-06-15
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: The FMC ADC mezzanine is wrapper around the fmc-adc-100ms core
......@@ -121,7 +121,7 @@ entity fmc_adc_mezzanine is
sys_scl_b : inout std_logic; -- Mezzanine system I2C clock (EEPROM)
sys_sda_b : inout std_logic; -- Mezzanine system I2C data (EEPROM)
wr_enable_i : in std_logic -- enable white rabbit features on mezzanine
wr_enable_i : in std_logic -- enable white rabbit features on mezzanine
);
end fmc_adc_mezzanine;
......@@ -286,12 +286,12 @@ architecture rtl of fmc_adc_mezzanine is
signal acq_end_extend : std_logic;
-- Time-tagging core
signal trigger_p : std_logic;
signal acq_start_p : std_logic;
signal acq_stop_p : std_logic;
signal acq_end_p : std_logic;
signal trigger_tag : t_timetag;
signal trigger_p : std_logic;
signal acq_start_p : std_logic;
signal acq_stop_p : std_logic;
signal acq_end_p : std_logic;
signal trigger_tag : t_timetag;
signal time_trigger : std_logic;
begin
......@@ -487,6 +487,7 @@ begin
acq_end_p_o => acq_end_p,
trigger_tag_i => trigger_tag,
time_trig_i => time_trigger,
ext_trigger_p_i => ext_trigger_p_i,
ext_trigger_n_i => ext_trigger_n_i,
......@@ -618,9 +619,10 @@ begin
wr_tm_tai_i => X"123456789a",
wr_tm_cycles_i => X"edcba98",
trig_tag_o => trigger_tag,
trig_tag_o => trigger_tag,
time_trig_o => time_trigger,
wb_adr_i => cnx_master_out(c_WB_SLAVE_TIMETAG).adr(5 downto 2), -- cnx_master_out.adr is byte address
wb_adr_i => cnx_master_out(c_WB_SLAVE_TIMETAG).adr(6 downto 2), -- cnx_master_out.adr is byte address
wb_dat_i => cnx_master_out(c_WB_SLAVE_TIMETAG).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_TIMETAG).dat,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_TIMETAG).cyc,
......
hdl/adc/wb_gen/fmc_adc_100Ms_csr.h
View file @ 6dee5c3b
......@@ -3,7 +3,7 @@
* File : fmc_adc_100Ms_csr.h
* Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
* Created : Mon Apr 18 16:09:20 2016
* Created : Thu Jun 16 15:16:07 2016
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -77,28 +77,28 @@
/* definitions for register: Trigger configuration */
/* definitions for field: Hardware trigger selection in reg: Trigger configuration */
#define FMC_ADC_CORE_TRIG_CFG_HW_TRIG_SEL WBGEN2_GEN_MASK(0, 1)
#define FMC_ADC_CORE_TRIG_CFG_HW_TRIG_SEL_MASK WBGEN2_GEN_MASK(0, 2)
#define FMC_ADC_CORE_TRIG_CFG_HW_TRIG_SEL_SHIFT 0
#define FMC_ADC_CORE_TRIG_CFG_HW_TRIG_SEL_W(value) WBGEN2_GEN_WRITE(value, 0, 2)
#define FMC_ADC_CORE_TRIG_CFG_HW_TRIG_SEL_R(reg) WBGEN2_GEN_READ(reg, 0, 2)
/* definitions for field: Hardware trigger polarity in reg: Trigger configuration */
#define FMC_ADC_CORE_TRIG_CFG_HW_TRIG_POL WBGEN2_GEN_MASK(1, 1)
#define FMC_ADC_CORE_TRIG_CFG_HW_TRIG_POL WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Hardware trigger enable in reg: Trigger configuration */
#define FMC_ADC_CORE_TRIG_CFG_HW_TRIG_EN WBGEN2_GEN_MASK(2, 1)
#define FMC_ADC_CORE_TRIG_CFG_HW_TRIG_EN WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Software trigger enable in reg: Trigger configuration */
#define FMC_ADC_CORE_TRIG_CFG_SW_TRIG_EN WBGEN2_GEN_MASK(3, 1)
#define FMC_ADC_CORE_TRIG_CFG_SW_TRIG_EN WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Channel selection for internal trigger in reg: Trigger configuration */
#define FMC_ADC_CORE_TRIG_CFG_INT_TRIG_SEL_MASK WBGEN2_GEN_MASK(4, 2)
#define FMC_ADC_CORE_TRIG_CFG_INT_TRIG_SEL_SHIFT 4
#define FMC_ADC_CORE_TRIG_CFG_INT_TRIG_SEL_W(value) WBGEN2_GEN_WRITE(value, 4, 2)
#define FMC_ADC_CORE_TRIG_CFG_INT_TRIG_SEL_R(reg) WBGEN2_GEN_READ(reg, 4, 2)
#define FMC_ADC_CORE_TRIG_CFG_INT_TRIG_SEL_MASK WBGEN2_GEN_MASK(5, 2)
#define FMC_ADC_CORE_TRIG_CFG_INT_TRIG_SEL_SHIFT 5
#define FMC_ADC_CORE_TRIG_CFG_INT_TRIG_SEL_W(value) WBGEN2_GEN_WRITE(value, 5, 2)
#define FMC_ADC_CORE_TRIG_CFG_INT_TRIG_SEL_R(reg) WBGEN2_GEN_READ(reg, 5, 2)
/* definitions for field: Enable internal trigger test mode in reg: Trigger configuration */
#define FMC_ADC_CORE_TRIG_CFG_INT_TRIG_TEST_EN WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Reserved in reg: Trigger configuration */
#define FMC_ADC_CORE_TRIG_CFG_RESERVED WBGEN2_GEN_MASK(7, 1)
#define FMC_ADC_CORE_TRIG_CFG_INT_TRIG_TEST_EN WBGEN2_GEN_MASK(7, 1)
/* definitions for field: Internal trigger threshold glitch filter in reg: Trigger configuration */
#define FMC_ADC_CORE_TRIG_CFG_INT_TRIG_THRES_FILT_MASK WBGEN2_GEN_MASK(8, 8)
......
hdl/adc/wb_gen/fmc_adc_100Ms_csr.htm
View file @ 6dee5c3b
......@@ -969,10 +969,10 @@ fmc_adc_core_sta_acq_cfg_i
</td>
<td class="td_pblock_right">
fmc_adc_core_trig_cfg_hw_trig_sel_o
fmc_adc_core_trig_cfg_hw_trig_sel_o[1:0]
</td>
<td class="td_arrow_right">
&rarr;
&rArr;
</td>
</tr>
<tr>
......@@ -1069,23 +1069,6 @@ fmc_adc_core_trig_cfg_int_trig_test_en_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_trig_cfg_reserved_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_core_trig_cfg_int_trig_thres_filt_o[7:0]
......@@ -3488,9 +3471,6 @@ INT_TRIG_THRES_FILT[7:0]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=1 class="td_field">
RESERVED
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
INT_TRIG_TEST_EN
</td>
<td style="border: solid 1px black;" colspan=2 class="td_field">
......@@ -3505,8 +3485,11 @@ HW_TRIG_EN
<td style="border: solid 1px black;" colspan=1 class="td_field">
HW_TRIG_POL
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
HW_TRIG_SEL
<td style="border: solid 1px black;" colspan=2 class="td_field">
HW_TRIG_SEL[1:0]
</td>
<td >
</td>
<td >
......@@ -3517,7 +3500,7 @@ HW_TRIG_SEL
<li><b>
HW_TRIG_SEL
</b>[<i>read/write</i>]: Hardware trigger selection
<br>0: internal (data threshold)<br>1: external (front panel trigger input)
<br>00: internal (data threshold)<br>01: external (front panel trigger input)<br>10: trigger from timetag core<br>11: reserved (for WR message-based trigger)
<li><b>
HW_TRIG_POL
</b>[<i>read/write</i>]: Hardware trigger polarity
......@@ -3539,10 +3522,6 @@ INT_TRIG_TEST_EN
</b>[<i>read/write</i>]: Enable internal trigger test mode
<br>Test mode:<br> ch1 = Channel 1 input(analogue)<br> ch2 = Channel input over threshold (digital)<br> ch3 = Channel input over threshold filtered (digital)<br> ch4 = Trigger (digital)
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
<li><b>
INT_TRIG_THRES_FILT
</b>[<i>read/write</i>]: Internal trigger threshold glitch filter
<br>Configures the internal trigger threshold glitch filter length.
......
hdl/adc/wb_gen/fmc_adc_100Ms_csr.wb
View file @ 6dee5c3b
......@@ -141,9 +141,10 @@ peripheral {
field {
name = "Hardware trigger selection";
description = "0: internal (data threshold)\n1: external (front panel trigger input)";
description = "00: internal (data threshold)\n01: external (front panel trigger input)\n10: trigger from timetag core\n11: reserved (for WR message-based trigger)";
prefix = "hw_trig_sel";
type = BIT;
type = SLV;
size = 2;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
......@@ -200,15 +201,6 @@ peripheral {
clock = "fs_clk_i";
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Internal trigger threshold glitch filter";
description = "Configures the internal trigger threshold glitch filter length.";
......
hdl/ip_cores/timetag_core/rtl/timetag_core.vhd
View file @ 6dee5c3b
......@@ -8,7 +8,7 @@
-- : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-11-18
-- Last update: 2016-06-09
-- Last update: 2016-06-15
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Implements a UTC seconds counter and a 125MHz system clock
......@@ -59,10 +59,11 @@ entity timetag_core is
wr_tm_cycles_i : in std_logic_vector(27 downto 0);
-- Trigger time-tag output
trig_tag_o : out t_timetag;
trig_tag_o : out t_timetag;
time_trig_o : out std_logic;
-- Wishbone interface
wb_adr_i : in std_logic_vector(3 downto 0);
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......@@ -84,7 +85,7 @@ architecture rtl of timetag_core is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......@@ -102,6 +103,9 @@ architecture rtl of timetag_core is
timetag_core_coarse_o : out std_logic_vector(27 downto 0);
timetag_core_coarse_i : in std_logic_vector(27 downto 0);
timetag_core_coarse_load_o : out std_logic;
timetag_core_time_trig_seconds_upper_o : out std_logic_vector(7 downto 0);
timetag_core_time_trig_seconds_lower_o : out std_logic_vector(31 downto 0);
timetag_core_time_trig_coarse_o : out std_logic_vector(27 downto 0);
timetag_core_trig_tag_seconds_upper_i : in std_logic_vector(7 downto 0);
timetag_core_trig_tag_seconds_lower_i : in std_logic_vector(31 downto 0);
timetag_core_trig_tag_coarse_i : in std_logic_vector(27 downto 0);
......@@ -127,6 +131,7 @@ architecture rtl of timetag_core is
signal timetag_coarse_cnt : unsigned(27 downto 0);
signal timetag_coarse_load_value : std_logic_vector(27 downto 0);
signal timetag_coarse_load_en : std_logic;
signal time_trigger : t_timetag;
signal trig_tag : t_timetag;
signal acq_start_tag : t_timetag;
signal acq_stop_tag : t_timetag;
......@@ -166,6 +171,9 @@ begin
timetag_core_coarse_o => timetag_coarse_load_value,
timetag_core_coarse_i => timetag_coarse,
timetag_core_coarse_load_o => timetag_coarse_load_en,
timetag_core_time_trig_seconds_upper_o => time_trigger.seconds(39 downto 32),
timetag_core_time_trig_seconds_lower_o => time_trigger.seconds(31 downto 0),
timetag_core_time_trig_coarse_o => time_trigger.coarse,
timetag_core_trig_tag_seconds_upper_i => trig_tag.seconds(39 downto 32),
timetag_core_trig_tag_seconds_lower_i => trig_tag.seconds(31 downto 0),
timetag_core_trig_tag_coarse_i => trig_tag.coarse,
......@@ -199,7 +207,7 @@ begin
end if;
end process p_timetag_seconds_cnt;
timetag_seconds <= wr_tm_tai_i when wr_enabled_i = '1' else std_logic_vector(timetag_seconds_cnt);
timetag_seconds <= wr_tm_tai_i when wr_enabled = '1' else std_logic_vector(timetag_seconds_cnt);
------------------------------------------------------------------------------
-- UTC 125MHz clock ticks counter
......@@ -223,7 +231,14 @@ begin
end if;
end process p_timetag_coarse_cnt;
timetag_coarse <= wr_tm_cycles_i when wr_enabled_i = '1' else std_logic_vector(timetag_coarse_cnt);
timetag_coarse <= wr_tm_cycles_i when wr_enabled = '1' else std_logic_vector(timetag_coarse_cnt);
------------------------------------------------------------------------------
-- Time trigger signal generation
------------------------------------------------------------------------------
time_trig_o <= '1' when ((time_trigger.seconds = timetag_seconds) and
(time_trigger.coarse = timetag_coarse))
else '0';
------------------------------------------------------------------------------
-- Last trigger event time-tag
......
hdl/ip_cores/timetag_core/rtl/timetag_core_pkg.vhd
View file @ 6dee5c3b
......@@ -8,7 +8,7 @@
-- : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2013-07-05
-- Last update: 2016-06-09
-- Last update: 2016-06-15
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Package for timetag core
......@@ -66,7 +66,8 @@ package timetag_core_pkg is
wr_tm_tai_i : in std_logic_vector(39 downto 0);
wr_tm_cycles_i : in std_logic_vector(27 downto 0);
trig_tag_o : out t_timetag;
wb_adr_i : in std_logic_vector(3 downto 0);
time_trig_o : out std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......
hdl/ip_cores/timetag_core/rtl/timetag_core_regs.vhd
View file @ 6dee5c3b
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/timetag_core_regs.vhd
-- Author : auto-generated by wbgen2 from timetag_core_regs.wb
-- Created : Wed Jun 8 10:54:43 2016
-- Created : Wed Jun 15 15:54:40 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE timetag_core_regs.wb
......@@ -18,7 +18,7 @@ entity timetag_core_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......@@ -39,6 +39,12 @@ entity timetag_core_regs is
timetag_core_coarse_o : out std_logic_vector(27 downto 0);
timetag_core_coarse_i : in std_logic_vector(27 downto 0);
timetag_core_coarse_load_o : out std_logic;
-- Port for std_logic_vector field: 'Time trigger seconds' in reg: 'Time trigger seconds register (upper)'
timetag_core_time_trig_seconds_upper_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'Time trigger seconds' in reg: 'Timetag seconds register (lower)'
timetag_core_time_trig_seconds_lower_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Time trigger coarse value' in reg: 'Timetag coarse time register, system clock ticks (125MHz)'
timetag_core_time_trig_coarse_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'Trigger time-tag seconds' in reg: 'Trigger time-tag seconds register (upper)'
timetag_core_trig_tag_seconds_upper_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'Trigger time-tag seconds' in reg: 'Trigger time-tag seconds register (lower)'
......@@ -68,11 +74,14 @@ end timetag_core_regs;
architecture syn of timetag_core_regs is
signal timetag_core_time_trig_seconds_upper_int : std_logic_vector(7 downto 0);
signal timetag_core_time_trig_seconds_lower_int : std_logic_vector(31 downto 0);
signal timetag_core_time_trig_coarse_int : std_logic_vector(27 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(4 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
......@@ -98,6 +107,9 @@ begin
timetag_core_seconds_upper_load_o <= '0';
timetag_core_seconds_lower_load_o <= '0';
timetag_core_coarse_load_o <= '0';
timetag_core_time_trig_seconds_upper_int <= "00000000";
timetag_core_time_trig_seconds_lower_int <= "00000000000000000000000000000000";
timetag_core_time_trig_coarse_int <= "0000000000000000000000000000";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
......@@ -115,8 +127,8 @@ begin
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(3 downto 0) is
when "0000" =>
case rwaddr_reg(4 downto 0) is
when "00000" =>
if (wb_we_i = '1') then
timetag_core_seconds_upper_load_o <= '1';
end if;
......@@ -147,14 +159,14 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0001" =>
when "00001" =>
if (wb_we_i = '1') then
timetag_core_seconds_lower_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= timetag_core_seconds_lower_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0010" =>
when "00010" =>
if (wb_we_i = '1') then
timetag_core_coarse_load_o <= '1';
end if;
......@@ -165,7 +177,56 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011" =>
when "00011" =>
if (wb_we_i = '1') then
timetag_core_time_trig_seconds_upper_int <= wrdata_reg(7 downto 0);
end if;
rddata_reg(7 downto 0) <= timetag_core_time_trig_seconds_upper_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100" =>
if (wb_we_i = '1') then
timetag_core_time_trig_seconds_lower_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= timetag_core_time_trig_seconds_lower_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101" =>
if (wb_we_i = '1') then
timetag_core_time_trig_coarse_int <= wrdata_reg(27 downto 0);
end if;
rddata_reg(27 downto 0) <= timetag_core_time_trig_coarse_int;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= timetag_core_trig_tag_seconds_upper_i;
......@@ -195,13 +256,13 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0100" =>
when "00111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= timetag_core_trig_tag_seconds_lower_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0101" =>
when "01000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(27 downto 0) <= timetag_core_trig_tag_coarse_i;
......@@ -211,7 +272,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0110" =>
when "01001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= timetag_core_acq_start_tag_seconds_upper_i;
......@@ -241,13 +302,13 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0111" =>
when "01010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= timetag_core_acq_start_tag_seconds_lower_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1000" =>
when "01011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(27 downto 0) <= timetag_core_acq_start_tag_coarse_i;
......@@ -257,7 +318,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1001" =>
when "01100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= timetag_core_acq_stop_tag_seconds_upper_i;
......@@ -287,13 +348,13 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1010" =>
when "01101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= timetag_core_acq_stop_tag_seconds_lower_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1011" =>
when "01110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(27 downto 0) <= timetag_core_acq_stop_tag_coarse_i;
......@@ -303,7 +364,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1100" =>
when "01111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= timetag_core_acq_end_tag_seconds_upper_i;
......@@ -333,13 +394,13 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1101" =>
when "10000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= timetag_core_acq_end_tag_seconds_lower_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1110" =>
when "10001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(27 downto 0) <= timetag_core_acq_end_tag_coarse_i;
......@@ -368,6 +429,12 @@ begin
timetag_core_seconds_lower_o <= wrdata_reg(31 downto 0);
-- Timetag coarse time
timetag_core_coarse_o <= wrdata_reg(27 downto 0);
-- Time trigger seconds
timetag_core_time_trig_seconds_upper_o <= timetag_core_time_trig_seconds_upper_int;
-- Time trigger seconds
timetag_core_time_trig_seconds_lower_o <= timetag_core_time_trig_seconds_lower_int;
-- Time trigger coarse value
timetag_core_time_trig_coarse_o <= timetag_core_time_trig_coarse_int;
-- Trigger time-tag seconds
-- Trigger time-tag seconds
-- Trigger time-tag coarse time
......
hdl/ip_cores/timetag_core/wb_gen/timetag_core_regs.h
View file @ 6dee5c3b
......@@ -3,7 +3,7 @@
* File : timetag_core_regs.h
* Author : auto-generated by wbgen2 from timetag_core_regs.wb
* Created : Wed Jun 8 10:54:43 2016
* Created : Wed Jun 15 15:54:40 2016
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE timetag_core_regs.wb
......@@ -37,6 +37,12 @@
/* definitions for register: Timetag coarse time register, system clock ticks (125MHz) */
/* definitions for register: Time trigger seconds register (upper) */
/* definitions for register: Timetag seconds register (lower) */
/* definitions for register: Timetag coarse time register, system clock ticks (125MHz) */
/* definitions for register: Trigger time-tag seconds register (upper) */
/* definitions for register: Trigger time-tag seconds register (lower) */
......@@ -68,29 +74,35 @@ PACKED struct TIMETAG_CORE_WB {
uint32_t SECONDS_LOWER;
/* [0x8]: REG Timetag coarse time register, system clock ticks (125MHz) */
uint32_t COARSE;
/* [0xc]: REG Trigger time-tag seconds register (upper) */
/* [0xc]: REG Time trigger seconds register (upper) */
uint32_t TIME_TRIG_SECONDS_UPPER;
/* [0x10]: REG Timetag seconds register (lower) */
uint32_t TIME_TRIG_SECONDS_LOWER;
/* [0x14]: REG Timetag coarse time register, system clock ticks (125MHz) */
uint32_t TIME_TRIG_COARSE;
/* [0x18]: REG Trigger time-tag seconds register (upper) */
uint32_t TRIG_TAG_SECONDS_UPPER;
/* [0x10]: REG Trigger time-tag seconds register (lower) */
/* [0x1c]: REG Trigger time-tag seconds register (lower) */
uint32_t TRIG_TAG_SECONDS_LOWER;
/* [0x14]: REG Trigger time-tag coarse time (system clock ticks 125MHz) register */
/* [0x20]: REG Trigger time-tag coarse time (system clock ticks 125MHz) register */
uint32_t TRIG_TAG_COARSE;
/* [0x18]: REG Acquisition start time-tag seconds register (upper) */
/* [0x24]: REG Acquisition start time-tag seconds register (upper) */
uint32_t ACQ_START_TAG_SECONDS_UPPER;
/* [0x1c]: REG Acquisition start time-tag seconds register (lower) */
/* [0x28]: REG Acquisition start time-tag seconds register (lower) */
uint32_t ACQ_START_TAG_SECONDS_LOWER;
/* [0x20]: REG Acquisition start time-tag coarse time (system clock ticks 125MHz) register */
/* [0x2c]: REG Acquisition start time-tag coarse time (system clock ticks 125MHz) register */
uint32_t ACQ_START_TAG_COARSE;
/* [0x24]: REG Acquisition stop time-tag seconds register (upper) */
/* [0x30]: REG Acquisition stop time-tag seconds register (upper) */
uint32_t ACQ_STOP_TAG_SECONDS_UPPER;
/* [0x28]: REG Acquisition stop time-tag seconds register (lower) */
/* [0x34]: REG Acquisition stop time-tag seconds register (lower) */
uint32_t ACQ_STOP_TAG_SECONDS_LOWER;
/* [0x2c]: REG Acquisition stop time-tag coarse time (system clock ticks 125MHz) register */
/* [0x38]: REG Acquisition stop time-tag coarse time (system clock ticks 125MHz) register */
uint32_t ACQ_STOP_TAG_COARSE;
/* [0x30]: REG Acquisition end time-tag seconds register (upper) */
/* [0x3c]: REG Acquisition end time-tag seconds register (upper) */
uint32_t ACQ_END_TAG_SECONDS_UPPER;
/* [0x34]: REG Acquisition end time-tag seconds register (lower) */
/* [0x40]: REG Acquisition end time-tag seconds register (lower) */
uint32_t ACQ_END_TAG_SECONDS_LOWER;
/* [0x38]: REG Acquisition end time-tag coarse time (system clock ticks 125MHz) register */
/* [0x44]: REG Acquisition end time-tag coarse time (system clock ticks 125MHz) register */
uint32_t ACQ_END_TAG_COARSE;
};
......
hdl/ip_cores/timetag_core/wb_gen/timetag_core_regs.htm
View file @ 6dee5c3b
......@@ -37,18 +37,21 @@
<span style="margin-left: 20px; ">3.1. <A href="#sect_3_1">Timetag seconds register (upper)</a></span><br/>
<span style="margin-left: 20px; ">3.2. <A href="#sect_3_2">Timetag seconds register (lower)</a></span><br/>
<span style="margin-left: 20px; ">3.3. <A href="#sect_3_3">Timetag coarse time register, system clock ticks (125MHz)</a></span><br/>
<span style="margin-left: 20px; ">3.4. <A href="#sect_3_4">Trigger time-tag seconds register (upper)</a></span><br/>
<span style="margin-left: 20px; ">3.5. <A href="#sect_3_5">Trigger time-tag seconds register (lower)</a></span><br/>
<span style="margin-left: 20px; ">3.6. <A href="#sect_3_6">Trigger time-tag coarse time (system clock ticks 125MHz) register</a></span><br/>
<span style="margin-left: 20px; ">3.7. <A href="#sect_3_7">Acquisition start time-tag seconds register (upper)</a></span><br/>
<span style="margin-left: 20px; ">3.8. <A href="#sect_3_8">Acquisition start time-tag seconds register (lower)</a></span><br/>
<span style="margin-left: 20px; ">3.9. <A href="#sect_3_9">Acquisition start time-tag coarse time (system clock ticks 125MHz) register</a></span><br/>
<span style="margin-left: 20px; ">3.10. <A href="#sect_3_10">Acquisition stop time-tag seconds register (upper)</a></span><br/>
<span style="margin-left: 20px; ">3.11. <A href="#sect_3_11">Acquisition stop time-tag seconds register (lower)</a></span><br/>
<span style="margin-left: 20px; ">3.12. <A href="#sect_3_12">Acquisition stop time-tag coarse time (system clock ticks 125MHz) register</a></span><br/>
<span style="margin-left: 20px; ">3.13. <A href="#sect_3_13">Acquisition end time-tag seconds register (upper)</a></span><br/>
<span style="margin-left: 20px; ">3.14. <A href="#sect_3_14">Acquisition end time-tag seconds register (lower)</a></span><br/>
<span style="margin-left: 20px; ">3.15. <A href="#sect_3_15">Acquisition end time-tag coarse time (system clock ticks 125MHz) register</a></span><br/>
<span style="margin-left: 20px; ">3.4. <A href="#sect_3_4">Time trigger seconds register (upper)</a></span><br/>
<span style="margin-left: 20px; ">3.5. <A href="#sect_3_5">Timetag seconds register (lower)</a></span><br/>
<span style="margin-left: 20px; ">3.6. <A href="#sect_3_6">Timetag coarse time register, system clock ticks (125MHz)</a></span><br/>
<span style="margin-left: 20px; ">3.7. <A href="#sect_3_7">Trigger time-tag seconds register (upper)</a></span><br/>
<span style="margin-left: 20px; ">3.8. <A href="#sect_3_8">Trigger time-tag seconds register (lower)</a></span><br/>
<span style="margin-left: 20px; ">3.9. <A href="#sect_3_9">Trigger time-tag coarse time (system clock ticks 125MHz) register</a></span><br/>
<span style="margin-left: 20px; ">3.10. <A href="#sect_3_10">Acquisition start time-tag seconds register (upper)</a></span><br/>
<span style="margin-left: 20px; ">3.11. <A href="#sect_3_11">Acquisition start time-tag seconds register (lower)</a></span><br/>
<span style="margin-left: 20px; ">3.12. <A href="#sect_3_12">Acquisition start time-tag coarse time (system clock ticks 125MHz) register</a></span><br/>
<span style="margin-left: 20px; ">3.13. <A href="#sect_3_13">Acquisition stop time-tag seconds register (upper)</a></span><br/>
<span style="margin-left: 20px; ">3.14. <A href="#sect_3_14">Acquisition stop time-tag seconds register (lower)</a></span><br/>
<span style="margin-left: 20px; ">3.15. <A href="#sect_3_15">Acquisition stop time-tag coarse time (system clock ticks 125MHz) register</a></span><br/>
<span style="margin-left: 20px; ">3.16. <A href="#sect_3_16">Acquisition end time-tag seconds register (upper)</a></span><br/>
<span style="margin-left: 20px; ">3.17. <A href="#sect_3_17">Acquisition end time-tag seconds register (lower)</a></span><br/>
<span style="margin-left: 20px; ">3.18. <A href="#sect_3_18">Acquisition end time-tag coarse time (system clock ticks 125MHz) register</a></span><br/>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -127,6 +130,57 @@ COARSE
REG
</td>
<td >
<A href="#TIME_TRIG_SECONDS_UPPER">Time trigger seconds register (upper)</a>
</td>
<td class="td_code">
timetag_core_time_trig_seconds_upper
</td>
<td class="td_code">
TIME_TRIG_SECONDS_UPPER
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x4
</td>
<td >
REG
</td>
<td >
<A href="#TIME_TRIG_SECONDS_LOWER">Timetag seconds register (lower)</a>
</td>
<td class="td_code">
timetag_core_time_trig_seconds_lower
</td>
<td class="td_code">
TIME_TRIG_SECONDS_LOWER
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x5
</td>
<td >
REG
</td>
<td >
<A href="#TIME_TRIG_COARSE">Timetag coarse time register, system clock ticks (125MHz)</a>
</td>
<td class="td_code">
timetag_core_time_trig_coarse
</td>
<td class="td_code">
TIME_TRIG_COARSE
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x6
</td>
<td >
REG
</td>
<td >
<A href="#TRIG_TAG_SECONDS_UPPER">Trigger time-tag seconds register (upper)</a>
</td>
<td class="td_code">
......@@ -136,9 +190,9 @@ timetag_core_trig_tag_seconds_upper
TRIG_TAG_SECONDS_UPPER
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x4
0x7
</td>
<td >
REG
......@@ -153,9 +207,9 @@ timetag_core_trig_tag_seconds_lower
TRIG_TAG_SECONDS_LOWER
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x5
0x8
</td>
<td >
REG
......@@ -170,9 +224,9 @@ timetag_core_trig_tag_coarse
TRIG_TAG_COARSE
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x6
0x9
</td>
<td >
REG
......@@ -187,9 +241,9 @@ timetag_core_acq_start_tag_seconds_upper
ACQ_START_TAG_SECONDS_UPPER
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x7
0xa
</td>
<td >
REG
......@@ -204,9 +258,9 @@ timetag_core_acq_start_tag_seconds_lower
ACQ_START_TAG_SECONDS_LOWER
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x8
0xb
</td>
<td >
REG
......@@ -221,9 +275,9 @@ timetag_core_acq_start_tag_coarse
ACQ_START_TAG_COARSE
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x9
0xc
</td>
<td >
REG
......@@ -238,9 +292,9 @@ timetag_core_acq_stop_tag_seconds_upper
ACQ_STOP_TAG_SECONDS_UPPER
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0xa
0xd
</td>
<td >
REG
......@@ -255,9 +309,9 @@ timetag_core_acq_stop_tag_seconds_lower
ACQ_STOP_TAG_SECONDS_LOWER
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0xb
0xe
</td>
<td >
REG
......@@ -272,9 +326,9 @@ timetag_core_acq_stop_tag_coarse
ACQ_STOP_TAG_COARSE
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0xc
0xf
</td>
<td >
REG
......@@ -289,9 +343,9 @@ timetag_core_acq_end_tag_seconds_upper
ACQ_END_TAG_SECONDS_UPPER
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0xd
0x10
</td>
<td >
REG
......@@ -306,9 +360,9 @@ timetag_core_acq_end_tag_seconds_lower
ACQ_END_TAG_SECONDS_LOWER
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0xe
0x11
</td>
<td >
REG
......@@ -366,7 +420,7 @@ timetag_core_seconds_upper_o[7:0]
&rArr;
</td>
<td class="td_pblock_left">
wb_adr_i[3:0]
wb_adr_i[4:0]
</td>
<td class="td_sym_center">
......@@ -591,6 +645,159 @@ timetag_core_coarse_load_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Time trigger seconds register (upper):</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
timetag_core_time_trig_seconds_upper_o[7:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Timetag seconds register (lower):</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
timetag_core_time_trig_seconds_lower_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Timetag coarse time register, system clock ticks (125MHz):</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
timetag_core_time_trig_coarse_o[27:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Trigger time-tag seconds register (upper):</b>
......@@ -1014,181 +1221,961 @@ timetag_core_acq_stop_tag_seconds_lower_i[31:0]
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
timetag_core_acq_stop_tag_coarse_i[27:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Acquisition end time-tag seconds register (upper):</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
timetag_core_acq_end_tag_seconds_upper_i[7:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Acquisition end time-tag seconds register (lower):</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
timetag_core_acq_end_tag_seconds_lower_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Acquisition end time-tag coarse time (system clock ticks 125MHz) register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
timetag_core_acq_end_tag_coarse_i[27:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
</table>
<h3><a name="sect_3_0">3. Register description</a></h3>
<a name="SECONDS_UPPER"></a>
<h3><a name="sect_3_1">3.1. Timetag seconds register (upper)</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
timetag_core_seconds_upper
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x0
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
SECONDS_UPPER
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x0
</td>
</tr>
</table>
<p>
8 upper bits of seconds counter. Incremented everytime the coarse counter overflows.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SECONDS_UPPER[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
SECONDS_UPPER
</b>[<i>read/write</i>]: Timetag seconds
</ul>
<a name="SECONDS_LOWER"></a>
<h3><a name="sect_3_2">3.2. Timetag seconds register (lower)</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
timetag_core_seconds_lower
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x1
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
SECONDS_LOWER
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x4
</td>
</tr>
</table>
<p>
32 lower bits of seconds counter. Incremented everytime the coarse counter overflows.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SECONDS_LOWER[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SECONDS_LOWER[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SECONDS_LOWER[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SECONDS_LOWER[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
SECONDS_LOWER
</b>[<i>read/write</i>]: Timetag seconds
</ul>
<a name="COARSE"></a>
<h3><a name="sect_3_3">3.3. Timetag coarse time register, system clock ticks (125MHz)</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
timetag_core_coarse
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x2
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
COARSE
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x8
</td>
</tr>
</table>
<p>
Coarse time counter clocked by 125MHz system clock.<br>Counts from 0 to 125000000.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=4 class="td_field">
COARSE[27:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_pblock_right">
timetag_core_acq_stop_tag_coarse_i[27:0]
<td class="td_bit">
17
</td>
<td class="td_arrow_right">
&lArr;
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_arrow_left">
<td style="border: solid 1px black;" colspan=8 class="td_field">
COARSE[23:16]
</td>
<td class="td_pblock_left">
<td >
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
<td >
</td>
<td class="td_arrow_right">
<td >
</td>
</tr>
<tr>
<td class="td_arrow_left">
<td >
</td>
<td class="td_pblock_left">
<td >
</td>
<td class="td_sym_center">
<td >
</td>
<td class="td_pblock_right">
<b>Acquisition end time-tag seconds register (upper):</b>
</td>
<td class="td_arrow_right">
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_arrow_left">
<td class="td_bit">
15
</td>
<td class="td_pblock_left">
<td class="td_bit">
14
</td>
<td class="td_sym_center">
<td class="td_bit">
13
</td>
<td class="td_pblock_right">
timetag_core_acq_end_tag_seconds_upper_i[7:0]
<td class="td_bit">
12
</td>
<td class="td_arrow_right">
&lArr;
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_arrow_left">
<td style="border: solid 1px black;" colspan=8 class="td_field">
COARSE[15:8]
</td>
<td class="td_pblock_left">
<td >
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
<td >
</td>
<td class="td_arrow_right">
<td >
</td>
</tr>
<tr>
<td class="td_arrow_left">
<td >
</td>
<td class="td_pblock_left">
<td >
</td>
<td class="td_sym_center">
<td >
</td>
<td class="td_pblock_right">
<b>Acquisition end time-tag seconds register (lower):</b>
</td>
<td class="td_arrow_right">
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
<td class="td_bit">
7
</td>
<td class="td_pblock_right">
timetag_core_acq_end_tag_seconds_lower_i[31:0]
<td class="td_bit">
6
</td>
<td class="td_arrow_right">
&lArr;
<td class="td_bit">
5
</td>
</tr>
<tr>
<td class="td_arrow_left">
<td class="td_bit">
4
</td>
<td class="td_pblock_left">
<td class="td_bit">
3
</td>
<td class="td_sym_center">
&nbsp;
<td class="td_bit">
2
</td>
<td class="td_pblock_right">
<td class="td_bit">
1
</td>
<td class="td_arrow_right">
<td class="td_bit">
0
</td>
</tr>
<tr>
<td class="td_arrow_left">
<td style="border: solid 1px black;" colspan=8 class="td_field">
COARSE[7:0]
</td>
<td class="td_pblock_left">
<td >
</td>
<td class="td_sym_center">
<td >
</td>
<td class="td_pblock_right">
<b>Acquisition end time-tag coarse time (system clock ticks 125MHz) register:</b>
</td>
<td class="td_arrow_right">
<td >
</td>
</tr>
<tr>
<td class="td_arrow_left">
<td >
</td>
<td class="td_pblock_left">
<td >
</td>
<td class="td_sym_center">
<td >
</td>
<td class="td_pblock_right">
timetag_core_acq_end_tag_coarse_i[27:0]
</td>
<td class="td_arrow_right">
&lArr;
<td >
</td>
</tr>
</table>
<h3><a name="sect_3_0">3. Register description</a></h3>
<a name="SECONDS_UPPER"></a>
<h3><a name="sect_3_1">3.1. Timetag seconds register (upper)</a></h3>
<ul>
<li><b>
COARSE
</b>[<i>read/write</i>]: Timetag coarse time
</ul>
<a name="TIME_TRIG_SECONDS_UPPER"></a>
<h3><a name="sect_3_4">3.4. Time trigger seconds register (upper)</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
timetag_core_seconds_upper
timetag_core_time_trig_seconds_upper
</td>
</tr>
<tr>
......@@ -1196,7 +2183,7 @@ timetag_core_seconds_upper
<b>HW address: </b>
</td>
<td class="td_code">
0x0
0x3
</td>
</tr>
<tr>
......@@ -1204,7 +2191,7 @@ timetag_core_seconds_upper
<b>C prefix: </b>
</td>
<td class="td_code">
SECONDS_UPPER
TIME_TRIG_SECONDS_UPPER
</td>
</tr>
<tr>
......@@ -1212,12 +2199,12 @@ SECONDS_UPPER
<b>C offset: </b>
</td>
<td class="td_code">
0x0
0xc
</td>
</tr>
</table>
<p>
8 upper bits of seconds counter. Incremented everytime the coarse counter overflows.
8 upper bits of seconds used for timer trigger.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -1410,7 +2397,7 @@ SECONDS_UPPER
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SECONDS_UPPER[7:0]
TIME_TRIG_SECONDS_UPPER[7:0]
</td>
<td >
......@@ -1437,18 +2424,18 @@ SECONDS_UPPER[7:0]
</table>
<ul>
<li><b>
SECONDS_UPPER
</b>[<i>read/write</i>]: Timetag seconds
TIME_TRIG_SECONDS_UPPER
</b>[<i>read/write</i>]: Time trigger seconds
</ul>
<a name="SECONDS_LOWER"></a>
<h3><a name="sect_3_2">3.2. Timetag seconds register (lower)</a></h3>
<a name="TIME_TRIG_SECONDS_LOWER"></a>
<h3><a name="sect_3_5">3.5. Timetag seconds register (lower)</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
timetag_core_seconds_lower
timetag_core_time_trig_seconds_lower
</td>
</tr>
<tr>
......@@ -1456,7 +2443,7 @@ timetag_core_seconds_lower
<b>HW address: </b>
</td>
<td class="td_code">
0x1
0x4
</td>
</tr>
<tr>
......@@ -1464,7 +2451,7 @@ timetag_core_seconds_lower
<b>C prefix: </b>
</td>
<td class="td_code">
SECONDS_LOWER
TIME_TRIG_SECONDS_LOWER
</td>
</tr>
<tr>
......@@ -1472,12 +2459,12 @@ SECONDS_LOWER
<b>C offset: </b>
</td>
<td class="td_code">
0x4
0x10
</td>
</tr>
</table>
<p>
32 lower bits of seconds counter. Incremented everytime the coarse counter overflows.
32 lower bits of seconds used for time trigger.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -1508,7 +2495,7 @@ SECONDS_LOWER
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SECONDS_LOWER[31:24]
TIME_TRIG_SECONDS_LOWER[31:24]
</td>
<td >
......@@ -1562,7 +2549,7 @@ SECONDS_LOWER[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SECONDS_LOWER[23:16]
TIME_TRIG_SECONDS_LOWER[23:16]
</td>
<td >
......@@ -1616,7 +2603,7 @@ SECONDS_LOWER[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SECONDS_LOWER[15:8]
TIME_TRIG_SECONDS_LOWER[15:8]
</td>
<td >
......@@ -1670,7 +2657,7 @@ SECONDS_LOWER[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SECONDS_LOWER[7:0]
TIME_TRIG_SECONDS_LOWER[7:0]
</td>
<td >
......@@ -1697,18 +2684,18 @@ SECONDS_LOWER[7:0]
</table>
<ul>
<li><b>
SECONDS_LOWER
</b>[<i>read/write</i>]: Timetag seconds
TIME_TRIG_SECONDS_LOWER
</b>[<i>read/write</i>]: Time trigger seconds
</ul>
<a name="COARSE"></a>
<h3><a name="sect_3_3">3.3. Timetag coarse time register, system clock ticks (125MHz)</a></h3>
<a name="TIME_TRIG_COARSE"></a>
<h3><a name="sect_3_6">3.6. Timetag coarse time register, system clock ticks (125MHz)</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
timetag_core_coarse
timetag_core_time_trig_coarse
</td>
</tr>
<tr>
......@@ -1716,7 +2703,7 @@ timetag_core_coarse
<b>HW address: </b>
</td>
<td class="td_code">
0x2
0x5
</td>
</tr>
<tr>
......@@ -1724,7 +2711,7 @@ timetag_core_coarse
<b>C prefix: </b>
</td>
<td class="td_code">
COARSE
TIME_TRIG_COARSE
</td>
</tr>
<tr>
......@@ -1732,7 +2719,7 @@ COARSE
<b>C offset: </b>
</td>
<td class="td_code">
0x8
0x14
</td>
</tr>
</table>
......@@ -1780,7 +2767,7 @@ Coarse time counter clocked by 125MHz system clock.<br>Counts from 0 to 12500000
-
</td>
<td style="border: solid 1px black;" colspan=4 class="td_field">
COARSE[27:24]
TIME_TRIG_COARSE[27:24]
</td>
<td >
......@@ -1822,7 +2809,7 @@ COARSE[27:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
COARSE[23:16]
TIME_TRIG_COARSE[23:16]
</td>
<td >
......@@ -1876,7 +2863,7 @@ COARSE[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
COARSE[15:8]
TIME_TRIG_COARSE[15:8]
</td>
<td >
......@@ -1930,7 +2917,7 @@ COARSE[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
COARSE[7:0]
TIME_TRIG_COARSE[7:0]
</td>
<td >
......@@ -1957,11 +2944,11 @@ COARSE[7:0]
</table>
<ul>
<li><b>
COARSE
</b>[<i>read/write</i>]: Timetag coarse time
TIME_TRIG_COARSE
</b>[<i>read/write</i>]: Time trigger coarse value
</ul>
<a name="TRIG_TAG_SECONDS_UPPER"></a>
<h3><a name="sect_3_4">3.4. Trigger time-tag seconds register (upper)</a></h3>
<h3><a name="sect_3_7">3.7. Trigger time-tag seconds register (upper)</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -1976,7 +2963,7 @@ timetag_core_trig_tag_seconds_upper
<b>HW address: </b>
</td>
<td class="td_code">
0x3
0x6
</td>
</tr>
<tr>
......@@ -1992,7 +2979,7 @@ TRIG_TAG_SECONDS_UPPER
<b>C offset: </b>
</td>
<td class="td_code">
0xc
0x18
</td>
</tr>
</table>
......@@ -2219,7 +3206,7 @@ TRIG_TAG_SECONDS_UPPER
<br>Holds time-tag seconds of the last trigger event
</ul>
<a name="TRIG_TAG_SECONDS_LOWER"></a>
<h3><a name="sect_3_5">3.5. Trigger time-tag seconds register (lower)</a></h3>
<h3><a name="sect_3_8">3.8. Trigger time-tag seconds register (lower)</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -2234,7 +3221,7 @@ timetag_core_trig_tag_seconds_lower
<b>HW address: </b>
</td>
<td class="td_code">
0x4
0x7
</td>
</tr>
<tr>
......@@ -2250,7 +3237,7 @@ TRIG_TAG_SECONDS_LOWER
<b>C offset: </b>
</td>
<td class="td_code">
0x10
0x1c
</td>
</tr>
</table>
......@@ -2477,7 +3464,7 @@ TRIG_TAG_SECONDS_LOWER
<br>Holds time-tag seconds of the last trigger event
</ul>
<a name="TRIG_TAG_COARSE"></a>
<h3><a name="sect_3_6">3.6. Trigger time-tag coarse time (system clock ticks 125MHz) register</a></h3>
<h3><a name="sect_3_9">3.9. Trigger time-tag coarse time (system clock ticks 125MHz) register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -2492,7 +3479,7 @@ timetag_core_trig_tag_coarse
<b>HW address: </b>
</td>
<td class="td_code">
0x5
0x8
</td>
</tr>
<tr>
......@@ -2508,7 +3495,7 @@ TRIG_TAG_COARSE
<b>C offset: </b>
</td>
<td class="td_code">
0x14
0x20
</td>
</tr>
</table>
......@@ -2735,7 +3722,7 @@ TRIG_TAG_COARSE
<br>Holds time-tag coarse time of the last trigger event
</ul>
<a name="ACQ_START_TAG_SECONDS_UPPER"></a>
<h3><a name="sect_3_7">3.7. Acquisition start time-tag seconds register (upper)</a></h3>
<h3><a name="sect_3_10">3.10. Acquisition start time-tag seconds register (upper)</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -2750,7 +3737,7 @@ timetag_core_acq_start_tag_seconds_upper
<b>HW address: </b>
</td>
<td class="td_code">
0x6
0x9
</td>
</tr>
<tr>
......@@ -2766,7 +3753,7 @@ ACQ_START_TAG_SECONDS_UPPER
<b>C offset: </b>
</td>
<td class="td_code">
0x18
0x24
</td>
</tr>
</table>
......@@ -2993,7 +3980,7 @@ ACQ_START_TAG_SECONDS_UPPER
<br>Holds time-tag seconds of the last acquisition start event
</ul>
<a name="ACQ_START_TAG_SECONDS_LOWER"></a>
<h3><a name="sect_3_8">3.8. Acquisition start time-tag seconds register (lower)</a></h3>
<h3><a name="sect_3_11">3.11. Acquisition start time-tag seconds register (lower)</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -3008,7 +3995,7 @@ timetag_core_acq_start_tag_seconds_lower
<b>HW address: </b>
</td>
<td class="td_code">
0x7
0xa
</td>
</tr>
<tr>
......@@ -3024,7 +4011,7 @@ ACQ_START_TAG_SECONDS_LOWER
<b>C offset: </b>
</td>
<td class="td_code">
0x1c
0x28
</td>
</tr>
</table>
......@@ -3251,7 +4238,7 @@ ACQ_START_TAG_SECONDS_LOWER
<br>Holds time-tag seconds of the last acquisition start event
</ul>
<a name="ACQ_START_TAG_COARSE"></a>
<h3><a name="sect_3_9">3.9. Acquisition start time-tag coarse time (system clock ticks 125MHz) register</a></h3>
<h3><a name="sect_3_12">3.12. Acquisition start time-tag coarse time (system clock ticks 125MHz) register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -3266,7 +4253,7 @@ timetag_core_acq_start_tag_coarse
<b>HW address: </b>
</td>
<td class="td_code">
0x8
0xb
</td>
</tr>
<tr>
......@@ -3282,7 +4269,7 @@ ACQ_START_TAG_COARSE
<b>C offset: </b>
</td>
<td class="td_code">
0x20
0x2c
</td>
</tr>
</table>
......@@ -3509,7 +4496,7 @@ ACQ_START_TAG_COARSE
<br>Holds time-tag coarse time of the last acquisition start event
</ul>
<a name="ACQ_STOP_TAG_SECONDS_UPPER"></a>
<h3><a name="sect_3_10">3.10. Acquisition stop time-tag seconds register (upper)</a></h3>
<h3><a name="sect_3_13">3.13. Acquisition stop time-tag seconds register (upper)</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -3524,7 +4511,7 @@ timetag_core_acq_stop_tag_seconds_upper
<b>HW address: </b>
</td>
<td class="td_code">
0x9
0xc
</td>
</tr>
<tr>
......@@ -3540,7 +4527,7 @@ ACQ_STOP_TAG_SECONDS_UPPER
<b>C offset: </b>
</td>
<td class="td_code">
0x24
0x30
</td>
</tr>
</table>
......@@ -3767,7 +4754,7 @@ ACQ_STOP_TAG_SECONDS_UPPER
<br>Holds time-tag seconds of the last acquisition stop event
</ul>
<a name="ACQ_STOP_TAG_SECONDS_LOWER"></a>
<h3><a name="sect_3_11">3.11. Acquisition stop time-tag seconds register (lower)</a></h3>
<h3><a name="sect_3_14">3.14. Acquisition stop time-tag seconds register (lower)</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -3782,7 +4769,7 @@ timetag_core_acq_stop_tag_seconds_lower
<b>HW address: </b>
</td>
<td class="td_code">
0xa
0xd
</td>
</tr>
<tr>
......@@ -3798,7 +4785,7 @@ ACQ_STOP_TAG_SECONDS_LOWER
<b>C offset: </b>
</td>
<td class="td_code">
0x28
0x34
</td>
</tr>
</table>
......@@ -4025,7 +5012,7 @@ ACQ_STOP_TAG_SECONDS_LOWER
<br>Holds time-tag seconds of the last acquisition stop event
</ul>
<a name="ACQ_STOP_TAG_COARSE"></a>
<h3><a name="sect_3_12">3.12. Acquisition stop time-tag coarse time (system clock ticks 125MHz) register</a></h3>
<h3><a name="sect_3_15">3.15. Acquisition stop time-tag coarse time (system clock ticks 125MHz) register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -4040,7 +5027,7 @@ timetag_core_acq_stop_tag_coarse
<b>HW address: </b>
</td>
<td class="td_code">
0xb
0xe
</td>
</tr>
<tr>
......@@ -4056,7 +5043,7 @@ ACQ_STOP_TAG_COARSE
<b>C offset: </b>
</td>
<td class="td_code">
0x2c
0x38
</td>
</tr>
</table>
......@@ -4283,7 +5270,7 @@ ACQ_STOP_TAG_COARSE
<br>Holds time-tag coarse time of the last acquisition stop event
</ul>
<a name="ACQ_END_TAG_SECONDS_UPPER"></a>
<h3><a name="sect_3_13">3.13. Acquisition end time-tag seconds register (upper)</a></h3>
<h3><a name="sect_3_16">3.16. Acquisition end time-tag seconds register (upper)</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -4298,7 +5285,7 @@ timetag_core_acq_end_tag_seconds_upper
<b>HW address: </b>
</td>
<td class="td_code">
0xc
0xf
</td>
</tr>
<tr>
......@@ -4314,7 +5301,7 @@ ACQ_END_TAG_SECONDS_UPPER
<b>C offset: </b>
</td>
<td class="td_code">
0x30
0x3c
</td>
</tr>
</table>
......@@ -4541,7 +5528,7 @@ ACQ_END_TAG_SECONDS_UPPER
<br>Holds time-tag seconds of the last acquisition end event
</ul>
<a name="ACQ_END_TAG_SECONDS_LOWER"></a>
<h3><a name="sect_3_14">3.14. Acquisition end time-tag seconds register (lower)</a></h3>
<h3><a name="sect_3_17">3.17. Acquisition end time-tag seconds register (lower)</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -4556,7 +5543,7 @@ timetag_core_acq_end_tag_seconds_lower
<b>HW address: </b>
</td>
<td class="td_code">
0xd
0x10
</td>
</tr>
<tr>
......@@ -4572,7 +5559,7 @@ ACQ_END_TAG_SECONDS_LOWER
<b>C offset: </b>
</td>
<td class="td_code">
0x34
0x40
</td>
</tr>
</table>
......@@ -4799,7 +5786,7 @@ ACQ_END_TAG_SECONDS_LOWER
<br>Holds time-tag seconds of the last acquisition end event
</ul>
<a name="ACQ_END_TAG_COARSE"></a>
<h3><a name="sect_3_15">3.15. Acquisition end time-tag coarse time (system clock ticks 125MHz) register</a></h3>
<h3><a name="sect_3_18">3.18. Acquisition end time-tag coarse time (system clock ticks 125MHz) register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -4814,7 +5801,7 @@ timetag_core_acq_end_tag_coarse
<b>HW address: </b>
</td>
<td class="td_code">
0xe
0x11
</td>
</tr>
<tr>
......@@ -4830,7 +5817,7 @@ ACQ_END_TAG_COARSE
<b>C offset: </b>
</td>
<td class="td_code">
0x38
0x44
</td>
</tr>
</table>
......
hdl/ip_cores/timetag_core/wb_gen/timetag_core_regs.wb
View file @ 6dee5c3b
peripheral {
name = "Time-tagging core registers";
description = "Wishbone slave for registers related to time-tagging core";
hdl_entity = "timetag_core_regs";
prefix = "timetag_core";
reg {
name = "Timetag seconds register (upper)";
description = "8 upper bits of seconds counter. Incremented everytime the coarse counter overflows.";
prefix = "seconds_upper";
field {
name = "Timetag seconds";
type = SLV;
load = LOAD_EXT;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
};
reg {
name = "Timetag seconds register (lower)";
description = "32 lower bits of seconds counter. Incremented everytime the coarse counter overflows.";
prefix = "seconds_lower";
field {
name = "Timetag seconds";
type = SLV;
load = LOAD_EXT;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
};
reg {
name = "Timetag coarse time register, system clock ticks (125MHz)";
description = "Coarse time counter clocked by 125MHz system clock.\nCounts from 0 to 125000000.";
prefix = "coarse";
field {
name = "Timetag coarse time";
type = SLV;
load = LOAD_EXT;
size = 28;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
};
reg {
name = "Trigger time-tag seconds register (upper)";
prefix = "trig_tag_seconds_upper";
field {
name = "Trigger time-tag seconds";
description = "Holds time-tag seconds of the last trigger event";
type = SLV;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Trigger time-tag seconds register (lower)";
prefix = "trig_tag_seconds_lower";
field {
name = "Trigger time-tag seconds";
description = "Holds time-tag seconds of the last trigger event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Trigger time-tag coarse time (system clock ticks 125MHz) register";
prefix = "trig_tag_coarse";
field {
name = "Trigger time-tag coarse time";
description = "Holds time-tag coarse time of the last trigger event";
type = SLV;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition start time-tag seconds register (upper)";
prefix = "acq_start_tag_seconds_upper";
field {
name = "Acquisition start time-tag seconds";
description = "Holds time-tag seconds of the last acquisition start event";
type = SLV;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition start time-tag seconds register (lower)";
prefix = "acq_start_tag_seconds_lower";
field {
name = "Acquisition start time-tag seconds";
description = "Holds time-tag seconds of the last acquisition start event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition start time-tag coarse time (system clock ticks 125MHz) register";
prefix = "acq_start_tag_coarse";
field {
name = "Acquisition start time-tag coarse time";
description = "Holds time-tag coarse time of the last acquisition start event";
type = SLV;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition stop time-tag seconds register (upper)";
prefix = "acq_stop_tag_seconds_upper";
field {
name = "Acquisition stop time-tag seconds";
description = "Holds time-tag seconds of the last acquisition stop event";
type = SLV;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition stop time-tag seconds register (lower)";
prefix = "acq_stop_tag_seconds_lower";
field {
name = "Acquisition stop time-tag seconds";
description = "Holds time-tag seconds of the last acquisition stop event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition stop time-tag coarse time (system clock ticks 125MHz) register";
prefix = "acq_stop_tag_coarse";
field {
name = "Acquisition stop time-tag coarse time";
description = "Holds time-tag coarse time of the last acquisition stop event";
type = SLV;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition end time-tag seconds register (upper)";
prefix = "acq_end_tag_seconds_upper";
field {
name = "Acquisition end time-tag seconds";
description = "Holds time-tag seconds of the last acquisition end event";
type = SLV;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition end time-tag seconds register (lower)";
prefix = "acq_end_tag_seconds_lower";
field {
name = "Acquisition end time-tag seconds";
description = "Holds time-tag seconds of the last acquisition end event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition end time-tag coarse time (system clock ticks 125MHz) register";
prefix = "acq_end_tag_coarse";
field {
name = "Acquisition end time-tag coarse time";
description = "Holds time-tag coarse time of the last acquisition end event";
type = SLV;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
name = "Time-tagging core registers";
description = "Wishbone slave for registers related to time-tagging core";
hdl_entity = "timetag_core_regs";
prefix = "timetag_core";
reg {
name = "Timetag seconds register (upper)";
description = "8 upper bits of seconds counter. Incremented everytime the coarse counter overflows.";
prefix = "seconds_upper";
field {
name = "Timetag seconds";
type = SLV;
load = LOAD_EXT;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
};
reg {
name = "Timetag seconds register (lower)";
description = "32 lower bits of seconds counter. Incremented everytime the coarse counter overflows.";
prefix = "seconds_lower";
field {
name = "Timetag seconds";
type = SLV;
load = LOAD_EXT;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
};
reg {
name = "Timetag coarse time register, system clock ticks (125MHz)";
description = "Coarse time counter clocked by 125MHz system clock.\nCounts from 0 to 125000000.";
prefix = "coarse";
field {
name = "Timetag coarse time";
type = SLV;
load = LOAD_EXT;
size = 28;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
};
reg {
name = "Time trigger seconds register (upper)";
description = "8 upper bits of seconds used for timer trigger.";
prefix = "time_trig_seconds_upper";
field {
name = "Time trigger seconds";
type = SLV;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Timetag seconds register (lower)";
description = "32 lower bits of seconds used for time trigger.";
prefix = "time_trig_seconds_lower";
field {
name = "Time trigger seconds";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Timetag coarse time register, system clock ticks (125MHz)";
description = "Coarse time counter clocked by 125MHz system clock.\nCounts from 0 to 125000000.";
prefix = "time_trig_coarse";
field {
name = "Time trigger coarse value";
type = SLV;
size = 28;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Trigger time-tag seconds register (upper)";
prefix = "trig_tag_seconds_upper";
field {
name = "Trigger time-tag seconds";
description = "Holds time-tag seconds of the last trigger event";
type = SLV;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Trigger time-tag seconds register (lower)";
prefix = "trig_tag_seconds_lower";
field {
name = "Trigger time-tag seconds";
description = "Holds time-tag seconds of the last trigger event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Trigger time-tag coarse time (system clock ticks 125MHz) register";
prefix = "trig_tag_coarse";
field {
name = "Trigger time-tag coarse time";
description = "Holds time-tag coarse time of the last trigger event";
type = SLV;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition start time-tag seconds register (upper)";
prefix = "acq_start_tag_seconds_upper";
field {
name = "Acquisition start time-tag seconds";
description = "Holds time-tag seconds of the last acquisition start event";
type = SLV;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition start time-tag seconds register (lower)";
prefix = "acq_start_tag_seconds_lower";
field {
name = "Acquisition start time-tag seconds";
description = "Holds time-tag seconds of the last acquisition start event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition start time-tag coarse time (system clock ticks 125MHz) register";
prefix = "acq_start_tag_coarse";
field {
name = "Acquisition start time-tag coarse time";
description = "Holds time-tag coarse time of the last acquisition start event";
type = SLV;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition stop time-tag seconds register (upper)";
prefix = "acq_stop_tag_seconds_upper";
field {
name = "Acquisition stop time-tag seconds";
description = "Holds time-tag seconds of the last acquisition stop event";
type = SLV;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition stop time-tag seconds register (lower)";
prefix = "acq_stop_tag_seconds_lower";
field {
name = "Acquisition stop time-tag seconds";
description = "Holds time-tag seconds of the last acquisition stop event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition stop time-tag coarse time (system clock ticks 125MHz) register";
prefix = "acq_stop_tag_coarse";
field {
name = "Acquisition stop time-tag coarse time";
description = "Holds time-tag coarse time of the last acquisition stop event";
type = SLV;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition end time-tag seconds register (upper)";
prefix = "acq_end_tag_seconds_upper";
field {
name = "Acquisition end time-tag seconds";
description = "Holds time-tag seconds of the last acquisition end event";
type = SLV;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition end time-tag seconds register (lower)";
prefix = "acq_end_tag_seconds_lower";
field {
name = "Acquisition end time-tag seconds";
description = "Holds time-tag seconds of the last acquisition end event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition end time-tag coarse time (system clock ticks 125MHz) register";
prefix = "acq_end_tag_coarse";
field {
name = "Acquisition end time-tag coarse time";
description = "Holds time-tag coarse time of the last acquisition end event";
type = SLV;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
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