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FMC ADC 100M 14b 4cha - Gateware
Commit 6f31510f authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: complete rework of trigger logic and SPEC testbench update. 

The new trigger logic allows for logical OR'ing of all trigger sources, by means
of the new "trigger enable" register. For each trigger the "mask" of the trigger source(s)
is reflected in the "trigger status" register and it is also stored in the data stream
together with the trigger time tag.

Furthermore, the previously used glitch filter has been removed, in favor of a comparator module
with optional hysteresis. This approach makes the internal trigger logic more responsible,
versatile and intuitive to the user.

The SPEC testbench has been updated to test these new features. It is still far from perfect though,
see also issue #1726.
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doc/manual/fmc_adc_100Ms_csr.tex
View file @ 6f31510f
......@@ -11,148 +11,156 @@ REG @tab
Status register
@item @code{0x8} @tab
REG @tab
@code{trig_cfg} @tab
Trigger configuration
@code{trig_stat} @tab
Trigger status
@item @code{0xc} @tab
REG @tab
@code{trig_en} @tab
Trigger enable
@item @code{0x10} @tab
REG @tab
@code{trig_pol} @tab
Trigger polarity
@item @code{0x14} @tab
REG @tab
@code{trig_dly} @tab
Trigger delay
@item @code{0x10} @tab
@item @code{0x18} @tab
REG @tab
@code{sw_trig} @tab
Software trigger
@item @code{0x14} @tab
@item @code{0x1c} @tab
REG @tab
@code{shots} @tab
Number of shots
@item @code{0x18} @tab
@item @code{0x20} @tab
REG @tab
@code{multi_depth} @tab
Multi-shot sample depth register
@item @code{0x24} @tab
REG @tab
@code{shots_cnt} @tab
Remaining shots counter
@item @code{0x1c} @tab
@item @code{0x28} @tab
REG @tab
@code{trig_pos} @tab
Trigger address register
@item @code{0x20} @tab
@item @code{0x2c} @tab
REG @tab
@code{fs_freq} @tab
Sampling clock frequency
@item @code{0x24} @tab
@item @code{0x30} @tab
REG @tab
@code{sr} @tab
Sample rate
@item @code{0x28} @tab
@item @code{0x34} @tab
REG @tab
@code{pre_samples} @tab
Pre-trigger samples
@item @code{0x2c} @tab
@item @code{0x38} @tab
REG @tab
@code{post_samples} @tab
Post-trigger samples
@item @code{0x30} @tab
@item @code{0x3c} @tab
REG @tab
@code{samples_cnt} @tab
Samples counter
@item @code{0x34} @tab
@item @code{0x80} @tab
REG @tab
@code{ch1_ctl} @tab
Channel 1 control register
@item @code{0x38} @tab
@item @code{0x84} @tab
REG @tab
@code{ch1_sta} @tab
Channel 1 status register
@item @code{0x3c} @tab
@item @code{0x88} @tab
REG @tab
@code{ch1_gain} @tab
Channel 1 gain calibration register
@item @code{0x40} @tab
@item @code{0x8c} @tab
REG @tab
@code{ch1_offset} @tab
Channel 1 offset calibration register
@item @code{0x44} @tab
@item @code{0x90} @tab
REG @tab
@code{ch1_sat} @tab
Channel 1 saturation register
@item @code{0x48} @tab
@item @code{0x94} @tab
REG @tab
@code{ch1_trig} @tab
Channel 1 trigger configuration register
@item @code{0x4c} @tab
@code{ch1_trig_thres} @tab
Channel 1 trigger threshold configuration register
@item @code{0x100} @tab
REG @tab
@code{ch2_ctl} @tab
Channel 2 control register
@item @code{0x50} @tab
@item @code{0x104} @tab
REG @tab
@code{ch2_sta} @tab
Channel 2 status register
@item @code{0x54} @tab
@item @code{0x108} @tab
REG @tab
@code{ch2_gain} @tab
Channel 2 gain calibration register
@item @code{0x58} @tab
@item @code{0x10c} @tab
REG @tab
@code{ch2_offset} @tab
Channel 2 offset calibration register
@item @code{0x5c} @tab
@item @code{0x110} @tab
REG @tab
@code{ch2_sat} @tab
Channel 2 saturation register
@item @code{0x60} @tab
@item @code{0x114} @tab
REG @tab
@code{ch2_trig} @tab
Channel 2 trigger configuration register
@item @code{0x64} @tab
@code{ch2_trig_thres} @tab
Channel 2 trigger threshold configuration register
@item @code{0x180} @tab
REG @tab
@code{ch3_ctl} @tab
Channel 3 control register
@item @code{0x68} @tab
@item @code{0x184} @tab
REG @tab
@code{ch3_sta} @tab
Channel 3 status register
@item @code{0x6c} @tab
@item @code{0x188} @tab
REG @tab
@code{ch3_gain} @tab
Channel 3 gain calibration register
@item @code{0x70} @tab
@item @code{0x18c} @tab
REG @tab
@code{ch3_offset} @tab
Channel 3 offset calibration register
@item @code{0x74} @tab
@item @code{0x190} @tab
REG @tab
@code{ch3_sat} @tab
Channel 3 saturation register
@item @code{0x78} @tab
@item @code{0x194} @tab
REG @tab
@code{ch3_trig} @tab
Channel 3 trigger configuration register
@item @code{0x7c} @tab
@code{ch3_trig_thres} @tab
Channel 3 trigger threshold configuration register
@item @code{0x200} @tab
REG @tab
@code{ch4_ctl} @tab
Channel 4 control register
@item @code{0x80} @tab
@item @code{0x204} @tab
REG @tab
@code{ch4_sta} @tab
Channel 4 status register
@item @code{0x84} @tab
@item @code{0x208} @tab
REG @tab
@code{ch4_gain} @tab
Channel 4 gain calibration register
@item @code{0x88} @tab
@item @code{0x20c} @tab
REG @tab
@code{ch4_offset} @tab
Channel 4 offset calibration register
@item @code{0x8c} @tab
@item @code{0x210} @tab
REG @tab
@code{ch4_sat} @tab
Channel 4 saturation register
@item @code{0x90} @tab
REG @tab
@code{ch4_trig} @tab
Channel 4 trigger configuration register
@item @code{0x94} @tab
@item @code{0x214} @tab
REG @tab
@code{multi_depth} @tab
Multi-shot sample depth register
@code{ch4_trig_thres} @tab
Channel 4 trigger threshold configuration register
@end multitable
@regsection @code{ctl} - Control register
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -231,42 +239,141 @@ Acquisition configuration status
@item @code{serdes_synced} @tab 0: bitslip in progress@*1: serdes synchronized
@item @code{acq_cfg} @tab 0: Unauthorised acquisition configuration (will prevent acquisition to start)@*1: Valid acquisition configuration@*@bullet{} Shot number > 0@*@bullet{} Post-trigger sample > 0
@end multitable
@regsection @code{trig_cfg} - Trigger configuration
@regsection @code{trig_stat} - Trigger status
Shows the source(s) of the last received trigger.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{1...0}
@item @code{0}
@tab R/O @tab
@code{EXT}
@tab @code{X} @tab
External trigger input
@item @code{1}
@tab R/O @tab
@code{SW}
@tab @code{X} @tab
Software trigger
@item @code{4}
@tab R/O @tab
@code{TIME}
@tab @code{X} @tab
Timetag trigger
@item @code{8}
@tab R/O @tab
@code{CH1}
@tab @code{X} @tab
Channel 1 internal threshold trigger
@item @code{9}
@tab R/O @tab
@code{CH2}
@tab @code{X} @tab
Channel 2 internal threshold trigger
@item @code{10}
@tab R/O @tab
@code{CH3}
@tab @code{X} @tab
Channel 3 internal threshold trigger
@item @code{11}
@tab R/O @tab
@code{CH4}
@tab @code{X} @tab
Channel 4 internal threshold trigger
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{ext} @tab 0: not triggered@*1: triggered
@item @code{sw} @tab 0: not triggered@*1: triggered
@item @code{time} @tab 0: not triggered@*1: triggered
@item @code{ch1} @tab 0: not triggered@*1: triggered
@item @code{ch2} @tab 0: not triggered@*1: triggered
@item @code{ch3} @tab 0: not triggered@*1: triggered
@item @code{ch4} @tab 0: not triggered@*1: triggered
@end multitable
@regsection @code{trig_en} - Trigger enable
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{HW_TRIG_SEL}
@code{EXT}
@tab @code{0} @tab
Hardware trigger selection
@item @code{2}
External trigger input
@item @code{1}
@tab R/W @tab
@code{EX_HW_TRIG_POL}
@code{SW}
@tab @code{0} @tab
External Hardware trigger polarity
@item @code{3}
Software trigger
@item @code{4}
@tab R/W @tab
@code{HW_TRIG_EN}
@code{TIME}
@tab @code{0} @tab
Hardware trigger enable
@item @code{4}
Timetag trigger
@item @code{8}
@tab R/W @tab
@code{SW_TRIG_EN}
@code{CH1}
@tab @code{0} @tab
Software trigger enable
@item @code{5}
Channel 1 internal threshold trigger
@item @code{9}
@tab R/W @tab
@code{CH2}
@tab @code{0} @tab
Channel 2 internal threshold trigger
@item @code{10}
@tab R/W @tab
@code{CH3}
@tab @code{0} @tab
Channel 3 internal threshold trigger
@item @code{11}
@tab R/W @tab
@code{CH4}
@tab @code{0} @tab
Channel 4 internal threshold trigger
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{ext} @tab 0: disable@*1: enable
@item @code{sw} @tab 0: disable@*1: enable
@item @code{time} @tab 0: disable@*1: enable
@item @code{ch1} @tab 0: disable@*1: enable
@item @code{ch2} @tab 0: disable@*1: enable
@item @code{ch3} @tab 0: disable@*1: enable
@item @code{ch4} @tab 0: disable@*1: enable
@end multitable
@regsection @code{trig_pol} - Trigger polarity
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{EXT}
@tab @code{0} @tab
External trigger input
@item @code{8}
@tab R/W @tab
@code{CH1}
@tab @code{0} @tab
Channel 1 internal threshold trigger
@item @code{9}
@tab R/W @tab
@code{INT_TRIG_TEST_EN}
@code{CH2}
@tab @code{0} @tab
Enable internal trigger test mode
Channel 2 internal threshold trigger
@item @code{10}
@tab R/W @tab
@code{CH3}
@tab @code{0} @tab
Channel 3 internal threshold trigger
@item @code{11}
@tab R/W @tab
@code{CH4}
@tab @code{0} @tab
Channel 4 internal threshold trigger
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{hw_trig_sel} @tab 00: internal (data threshold)@*01: external (front panel trigger input)@*10: trigger from timetag core@*11: reserved (for WR message-based trigger)
@item @code{ex_hw_trig_pol} @tab 0: positive edge/slope@*1: negative edge/slope
@item @code{hw_trig_en} @tab 0: disable@*1: enable
@item @code{sw_trig_en} @tab 0: disable@*1: enable
@item @code{int_trig_test_en} @tab Test mode:@* ch1 = Channel 1 input(analogue)@* ch2 = Channel input over threshold (digital)@* ch3 = Channel input over threshold filtered (digital)@* ch4 = Trigger (digital)
@item @code{ext} @tab 0: positive edge/slope@*1: negative edge/slope
@item @code{ch1} @tab 0: positive edge/slope@*1: negative edge/slope
@item @code{ch2} @tab 0: positive edge/slope@*1: negative edge/slope
@item @code{ch3} @tab 0: positive edge/slope@*1: negative edge/slope
@item @code{ch4} @tab 0: positive edge/slope@*1: negative edge/slope
@end multitable
@regsection @code{trig_dly} - Trigger delay
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -304,6 +411,19 @@ Number of shots
@headitem Field @tab Description
@item @code{nb} @tab Number of shots required in multi-shot mode, set to one for single-shot mode.
@end multitable
@regsection @code{multi_depth} - Multi-shot sample depth register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/O @tab
@code{MULTI_DEPTH}
@tab @code{X} @tab
Multi-shot sample depth
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{multi_depth} @tab Maximum sample depth allowed in multi-shot acquisition mode, excluding two samples already reserved for time tag
@end multitable
@regsection @code{shots_cnt} - Remaining shots counter
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
......@@ -460,41 +580,24 @@ Saturation value for channel 1
@headitem Field @tab Description
@item @code{val} @tab Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
@end multitable
@regsection @code{ch1_trig} - Channel 1 trigger configuration register
@regsection @code{ch1_trig_thres} - Channel 1 trigger threshold configuration register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{TRIG_EN}
@tab @code{0} @tab
Trigger enable for channel 1
@item @code{1}
@tab R/W @tab
@code{TRIG_POL}
@tab @code{0} @tab
Trigger polarity
@item @code{7...2}
@tab R/W @tab
@code{RESERVED}
@tab @code{0} @tab
Reserved
@item @code{15...8}
@item @code{15...0}
@tab R/W @tab
@code{INT_TRIG_THRES_FILT}
@code{VAL}
@tab @code{0} @tab
Internal trigger threshold glitch filter for Channel 1
Threshold for internal trigger
@item @code{31...16}
@tab R/W @tab
@code{INT_TRIG_THRES}
@code{HYST}
@tab @code{0} @tab
Threshold for Channel 1 internal trigger
Internal trigger threshold hysteresis
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{trig_pol} @tab 0: positive edge/slope@*1: negative edge/slope
@item @code{reserved} @tab Ignore on read, write with 0's
@item @code{int_trig_thres_filt} @tab Configures the internal trigger threshold glitch filter length.
@item @code{int_trig_thres} @tab Treated as binary two's complement and compared to raw ADC data.
@item @code{val} @tab Treated as binary two's complement and compared to raw ADC data.
@item @code{hyst} @tab Configures the internal trigger threshold hysteresis (two's complement).
@end multitable
@regsection @code{ch2_ctl} - Channel 2 control register
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -561,41 +664,24 @@ Saturation value for channel 2
@headitem Field @tab Description
@item @code{val} @tab Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
@end multitable
@regsection @code{ch2_trig} - Channel 2 trigger configuration register
@regsection @code{ch2_trig_thres} - Channel 2 trigger threshold configuration register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{TRIG_EN}
@tab @code{0} @tab
Trigger enable for channel 2
@item @code{1}
@tab R/W @tab
@code{TRIG_POL}
@tab @code{0} @tab
Trigger polarity
@item @code{7...2}
@tab R/W @tab
@code{RESERVED}
@tab @code{0} @tab
Reserved
@item @code{15...8}
@item @code{15...0}
@tab R/W @tab
@code{INT_TRIG_THRES_FILT}
@code{VAL}
@tab @code{0} @tab
Internal trigger threshold glitch filter for Channel 2
Threshold for internal trigger
@item @code{31...16}
@tab R/W @tab
@code{INT_TRIG_THRES}
@code{HYST}
@tab @code{0} @tab
Threshold for Channel 2 internal trigger
Internal trigger threshold hysteresis
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{trig_pol} @tab 0: positive edge/slope@*1: negative edge/slope
@item @code{reserved} @tab Ignore on read, write with 0's
@item @code{int_trig_thres_filt} @tab Configures the internal trigger threshold glitch filter length.
@item @code{int_trig_thres} @tab Treated as binary two's complement and compared to raw ADC data.
@item @code{val} @tab Treated as binary two's complement and compared to raw ADC data.
@item @code{hyst} @tab Configures the internal trigger threshold hysteresis (two's complement).
@end multitable
@regsection @code{ch3_ctl} - Channel 3 control register
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -662,41 +748,24 @@ Saturation value for channel 3
@headitem Field @tab Description
@item @code{val} @tab Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
@end multitable
@regsection @code{ch3_trig} - Channel 3 trigger configuration register
@regsection @code{ch3_trig_thres} - Channel 3 trigger threshold configuration register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{TRIG_EN}
@tab @code{0} @tab
Trigger enable for channel 3
@item @code{1}
@tab R/W @tab
@code{TRIG_POL}
@tab @code{0} @tab
Trigger polarity
@item @code{7...2}
@tab R/W @tab
@code{RESERVED}
@tab @code{0} @tab
Reserved
@item @code{15...8}
@item @code{15...0}
@tab R/W @tab
@code{INT_TRIG_THRES_FILT}
@code{VAL}
@tab @code{0} @tab
Internal trigger threshold glitch filter for Channel 3
Threshold for internal trigger
@item @code{31...16}
@tab R/W @tab
@code{INT_TRIG_THRES}
@code{HYST}
@tab @code{0} @tab
Threshold for Channel 3 internal trigger
Internal trigger threshold hysteresis
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{trig_pol} @tab 0: positive edge/slope@*1: negative edge/slope
@item @code{reserved} @tab Ignore on read, write with 0's
@item @code{int_trig_thres_filt} @tab Configures the internal trigger threshold glitch filter length.
@item @code{int_trig_thres} @tab Treated as binary two's complement and compared to raw ADC data.
@item @code{val} @tab Treated as binary two's complement and compared to raw ADC data.
@item @code{hyst} @tab Configures the internal trigger threshold hysteresis (two's complement).
@end multitable
@regsection @code{ch4_ctl} - Channel 4 control register
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -763,52 +832,22 @@ Saturation value for channel 4
@headitem Field @tab Description
@item @code{val} @tab Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
@end multitable
@regsection @code{ch4_trig} - Channel 4 trigger configuration register
@regsection @code{ch4_trig_thres} - Channel 4 trigger threshold configuration register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{TRIG_EN}
@tab @code{0} @tab
Trigger enable for channel 4
@item @code{1}
@tab R/W @tab
@code{TRIG_POL}
@tab @code{0} @tab
trigger polarity
@item @code{7...2}
@tab R/W @tab
@code{RESERVED}
@tab @code{0} @tab
Reserved
@item @code{15...8}
@item @code{15...0}
@tab R/W @tab
@code{INT_TRIG_THRES_FILT}
@code{VAL}
@tab @code{0} @tab
Internal trigger threshold glitch filter for Channel 4
Threshold for internal trigger
@item @code{31...16}
@tab R/W @tab
@code{INT_TRIG_THRES}
@code{HYST}
@tab @code{0} @tab
Threshold for Channel 4 internal trigger
Internal trigger threshold hysteresis
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{trig_pol} @tab 0: positive edge/slope@*1: negative edge/slope
@item @code{reserved} @tab Ignore on read, write with 0's
@item @code{int_trig_thres_filt} @tab Configures the internal trigger threshold glitch filter length.
@item @code{int_trig_thres} @tab Treated as binary two's complement and compared to raw ADC data.
@end multitable
@regsection @code{multi_depth} - Multi-shot sample depth register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/O @tab
@code{MULTI_DEPTH}
@tab @code{X} @tab
Multi-shot sample depth
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{multi_depth} @tab Maximum sample depth allowed in multi-shot acquisition mode, excluding two samples already reserved for time tag
@item @code{val} @tab Treated as binary two's complement and compared to raw ADC data.
@item @code{hyst} @tab Configures the internal trigger threshold hysteresis (two's complement).
@end multitable
hdl/adc/rtl/fmc_adc_100Ms_core.vhd
View file @ 6f31510f
......@@ -9,7 +9,7 @@
-- Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-02-24
-- Last update: 2018-01-23
-- Last update: 2018-01-25
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: FMC ADC 100Ms/s core.
......@@ -62,7 +62,7 @@ entity fmc_adc_100Ms_core is
sys_rst_n_i : in std_logic;
-- CSR wishbone interface
wb_csr_adr_i : in std_logic_vector(5 downto 0);
wb_csr_adr_i : in std_logic_vector(7 downto 0);
wb_csr_dat_i : in std_logic_vector(31 downto 0);
wb_csr_dat_o : out std_logic_vector(31 downto 0);
wb_csr_cyc_i : in std_logic;
......@@ -153,7 +153,7 @@ architecture rtl of fmc_adc_100Ms_core is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(5 downto 0);
wb_adr_i : in std_logic_vector(7 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......@@ -194,8 +194,6 @@ architecture rtl of fmc_adc_100Ms_core is
-- Types declaration
------------------------------------------------------------------------------
type t_acq_fsm_state is (IDLE, PRE_TRIG, WAIT_TRIG, POST_TRIG, TRIG_TAG, DECR_SHOT);
type t_data_pipe is array (natural range<>) of std_logic_vector(63 downto 0);
type t_fmc_adc_vec8_array is array (positive range<>) of std_logic_vector(7 downto 0);
type t_fmc_adc_vec16_array is array (positive range<>) of std_logic_vector(15 downto 0);
------------------------------------------------------------------------------
......@@ -236,36 +234,33 @@ architecture rtl of fmc_adc_100Ms_core is
-- Trigger
signal ext_trig_a, ext_trig : std_logic;
signal ext_trig_p, ext_trig_n : std_logic;
signal ext_trig_d : std_logic;
signal time_trig : std_logic;
signal int_trig : std_logic;
signal time_trig_d : std_logic;
signal int_ch_trig : std_logic_vector(1 to 4);
signal int_trig_over_thres : std_logic_vector(1 to 4);
signal int_trig_over_thres_filt : std_logic_vector(1 to 4);
signal int_trig_over_thres_filt_d : std_logic_vector(1 to 4);
signal int_trig_data : t_fmc_adc_vec16_array(1 to 4);
signal int_trig_thres : t_fmc_adc_vec16_array(1 to 4);
signal int_trig_test_en : std_logic;
signal int_trig_thres_filt : t_fmc_adc_vec8_array(1 to 4);
signal hw_trig_pol : std_logic;
signal int_trig_thres_hyst : t_fmc_adc_vec16_array(1 to 4);
signal ext_trig_pol : std_logic;
signal int_trig_pol : std_logic_vector(1 to 4);
signal hw_trig : std_logic;
signal hw_trig_t : std_logic;
signal hw_trig_sel : std_logic_vector(1 downto 0);
signal hw_trig_en : std_logic;
signal ext_trig_en : std_logic;
signal int_trig_en : std_logic_vector(1 to 4);
signal time_trig_en : std_logic;
signal sw_trig : std_logic;
signal sw_trig_t : std_logic;
signal sw_trig_d : std_logic;
signal sw_trig_en : std_logic;
signal trig : std_logic;
signal trig_delay : std_logic_vector(31 downto 0);
signal trig_delay_cnt : unsigned(31 downto 0);
signal trig_d : std_logic;
signal trig_align : std_logic;
-- Internal trigger test mode
signal int_trig_over_thres_tst : std_logic_vector(15 downto 0);
signal int_trig_over_thres_filt_tst : std_logic_vector(15 downto 0);
signal trig_tst : std_logic_vector(15 downto 0);
signal trig_storage : std_logic_vector(31 downto 0);
signal trig_fifo_wr : std_logic;
signal trig_fifo_rd : std_logic;
signal trig_fifo_empty : std_logic;
signal trig_fifo_full : std_logic;
signal trig_fifo_din : std_logic_vector(32 downto 0);
signal trig_fifo_dout : std_logic_vector(32 downto 0);
-- Under-sampling
signal undersample_factor : std_logic_vector(31 downto 0);
......@@ -286,8 +281,9 @@ architecture rtl of fmc_adc_100Ms_core is
signal offset_calibr : std_logic_vector(63 downto 0);
signal data_calibr_in : std_logic_vector(63 downto 0);
signal data_calibr_out : std_logic_vector(63 downto 0);
signal data_calibr_out_t : std_logic_vector(63 downto 0);
signal data_calibr_out_d : t_data_pipe(3 downto 0);
signal data_calibr_out_d1 : std_logic_vector(63 downto 0);
signal data_calibr_out_d2 : std_logic_vector(63 downto 0);
signal data_calibr_out_d3 : std_logic_vector(63 downto 0);
signal sat_val : std_logic_vector(59 downto 0);
-- Acquisition FSM
......@@ -658,6 +654,13 @@ begin
csr_regin.sta_serdes_pll_i <= locked_out;
csr_regin.sta_serdes_synced_i <= serdes_synced;
csr_regin.sta_acq_cfg_i <= acq_config_ok;
csr_regin.trig_stat_ext_i <= trig_storage(0);
csr_regin.trig_stat_sw_i <= trig_storage(1);
csr_regin.trig_stat_time_i <= trig_storage(4);
csr_regin.trig_stat_ch1_i <= trig_storage(8);
csr_regin.trig_stat_ch2_i <= trig_storage(9);
csr_regin.trig_stat_ch3_i <= trig_storage(10);
csr_regin.trig_stat_ch4_i <= trig_storage(11);
csr_regin.shots_cnt_val_i <= remaining_shots;
csr_regin.trig_pos_i <= trig_addr;
csr_regin.fs_freq_i <= fs_freq;
......@@ -676,29 +679,28 @@ begin
test_data_en <= csr_regout.ctl_test_data_en_o;
trig_led_man <= csr_regout.ctl_trig_led_o;
acq_led_man <= csr_regout.ctl_acq_led_o;
hw_trig_sel <= csr_regout.trig_cfg_hw_trig_sel_o;
hw_trig_pol <= csr_regout.trig_cfg_ex_hw_trig_pol_o;
int_trig_pol(1) <= csr_regout.ch1_trig_trig_pol_o;
int_trig_pol(2) <= csr_regout.ch2_trig_trig_pol_o;
int_trig_pol(3) <= csr_regout.ch3_trig_trig_pol_o;
int_trig_pol(4) <= csr_regout.ch4_trig_trig_pol_o;
hw_trig_en <= csr_regout.trig_cfg_hw_trig_en_o;
sw_trig_en <= csr_regout.trig_cfg_sw_trig_en_o;
int_trig_en(1) <= csr_regout.ch1_trig_trig_en_o;
int_trig_en(2) <= csr_regout.ch2_trig_trig_en_o;
int_trig_en(3) <= csr_regout.ch3_trig_trig_en_o;
int_trig_en(4) <= csr_regout.ch4_trig_trig_en_o;
int_trig_test_en <= csr_regout.trig_cfg_int_trig_test_en_o;
int_trig_thres_filt(1) <= csr_regout.ch1_trig_int_trig_thres_filt_o;
int_trig_thres_filt(2) <= csr_regout.ch2_trig_int_trig_thres_filt_o;
int_trig_thres_filt(3) <= csr_regout.ch3_trig_int_trig_thres_filt_o;
int_trig_thres_filt(4) <= csr_regout.ch4_trig_int_trig_thres_filt_o;
int_trig_thres(1) <= csr_regout.ch1_trig_int_trig_thres_o;
int_trig_thres(2) <= csr_regout.ch2_trig_int_trig_thres_o;
int_trig_thres(3) <= csr_regout.ch3_trig_int_trig_thres_o;
int_trig_thres(4) <= csr_regout.ch4_trig_int_trig_thres_o;
ext_trig_en <= csr_regout.trig_en_ext_o;
sw_trig_en <= csr_regout.trig_en_sw_o;
time_trig_en <= csr_regout.trig_en_time_o;
int_trig_en(1) <= csr_regout.trig_en_ch1_o;
int_trig_en(2) <= csr_regout.trig_en_ch2_o;
int_trig_en(3) <= csr_regout.trig_en_ch3_o;
int_trig_en(4) <= csr_regout.trig_en_ch4_o;
ext_trig_pol <= csr_regout.trig_pol_ext_o;
int_trig_pol(1) <= csr_regout.trig_pol_ch1_o;
int_trig_pol(2) <= csr_regout.trig_pol_ch2_o;
int_trig_pol(3) <= csr_regout.trig_pol_ch3_o;
int_trig_pol(4) <= csr_regout.trig_pol_ch4_o;
int_trig_thres_hyst(1) <= csr_regout.ch1_trig_thres_hyst_o;
int_trig_thres_hyst(2) <= csr_regout.ch2_trig_thres_hyst_o;
int_trig_thres_hyst(3) <= csr_regout.ch3_trig_thres_hyst_o;
int_trig_thres_hyst(4) <= csr_regout.ch4_trig_thres_hyst_o;
int_trig_thres(1) <= csr_regout.ch1_trig_thres_val_o;
int_trig_thres(2) <= csr_regout.ch2_trig_thres_val_o;
int_trig_thres(3) <= csr_regout.ch3_trig_thres_val_o;
int_trig_thres(4) <= csr_regout.ch4_trig_thres_val_o;
trig_delay <= csr_regout.trig_dly_o;
sw_trig_t <= csr_regout.sw_trig_wr_o;
sw_trig <= csr_regout.sw_trig_wr_o;
shots_value <= csr_regout.shots_nb_o;
undersample_factor <= csr_regout.sr_undersample_o;
pre_trig_value <= csr_regout.pre_samples_o;
......@@ -758,7 +760,7 @@ begin
ppulse_o => ext_trig_p);
-- select external trigger pulse polarity
with hw_trig_pol select
with ext_trig_pol select
ext_trig <=
ext_trig_p when '0',
ext_trig_n when '1',
......@@ -778,69 +780,45 @@ begin
g_int_trig : for I in 1 to 4 generate
int_trig_data(I) <= data_calibr_out(16*I-1 downto 16*I-16);
-- Detects input data going over the internal trigger threshold
p_int_trig : process (fs_clk, fs_rst_n)
begin
if (fs_rst_n = '0' or int_trig_en(I) = '0') then
int_trig_over_thres(I) <= '0';
elsif rising_edge(fs_clk) then
if signed(int_trig_data(I)) > signed(int_trig_thres(I)) then
int_trig_over_thres(I) <= '1';
else
int_trig_over_thres(I) <= '0';
end if;
end if;
end process p_int_trig;
-- Filters out glitches from over threshold signal (rejects noise around the threshold -> hysteresis)
cmp_dyn_glitch_filt : gc_dyn_glitch_filt
generic map(
g_len_width => 8
)
port map(
cmp_gc_comparator: entity work.gc_comparator
generic map (
g_IN_WIDTH => 16)
port map (
clk_i => fs_clk,
rst_n_i => fs_rst_n,
len_i => int_trig_thres_filt(I),
dat_i => int_trig_over_thres(I),
dat_o => int_trig_over_thres_filt(I)
);
pol_inv_i => int_trig_pol(I),
enable_i => int_trig_en(I),
inp_i => int_trig_data(I),
inn_i => int_trig_thres(I),
hys_i => int_trig_thres_hyst(I),
out_o => open,
out_p_o => int_ch_trig(I));
-- Detects whether it's a positive or negative slope
p_int_trig_slope : process (fs_clk, fs_rst_n)
end generate g_int_trig;
-- Internal triggers take one more cycle to propagate, so delay all other sources
-- to properly align everything with the acquired data.
p_trig_shift : process(fs_clk, fs_rst_n)
begin
if fs_rst_n = '0' then
int_trig_over_thres_filt_d(I) <= '0';
sw_trig_d <= '0';
ext_trig_d <= '0';
time_trig_d <= '0';
elsif rising_edge(fs_clk) then
int_trig_over_thres_filt_d(I) <= int_trig_over_thres_filt(I);
sw_trig_d <= sw_trig;
ext_trig_d <= ext_trig;
time_trig_d <= time_trig;
end if;
end process;
int_ch_trig(I) <= int_trig_over_thres_filt(I) and not(int_trig_over_thres_filt_d(I)) when int_trig_pol(I) = '0' else -- positive slope
not(int_trig_over_thres_filt(I)) and int_trig_over_thres_filt_d(I); -- negative slope
end generate g_int_trig;
int_trig <= int_ch_trig(1) or int_ch_trig(2) or int_ch_trig(3) or int_ch_trig(4);
-- Hardware trigger selection
-- 00: internal = adc data threshold
-- 01: external = pulse from front panel
-- 10: time = time trigger
-- 11: reserved = (for WR message-based interrupts)
with hw_trig_sel select
hw_trig_t <=
int_trig when "00",
ext_trig when "01",
time_trig when "10",
'0' when others;
-- Hardware trigger enable
hw_trig <= hw_trig_t and hw_trig_en;
-- Software trigger enable
sw_trig <= sw_trig_t and sw_trig_en;
end process p_trig_shift;
-- Trigger sources ORing
trig <= sw_trig or hw_trig;
trig <= (sw_trig_d and sw_trig_en) or
(ext_trig_d and ext_trig_en) or
(int_ch_trig(1) and int_trig_en(1)) or
(int_ch_trig(2) and int_trig_en(2)) or
(int_ch_trig(3) and int_trig_en(3)) or
(int_ch_trig(4) and int_trig_en(4)) or
(time_trig_d and time_trig_en);
-- Trigger delay
p_trig_delay_cnt : process(fs_clk, fs_rst_n)
......@@ -877,6 +855,69 @@ begin
end if;
end process p_trig_delay;
------------------------------------------------------------------------------
-- Trigger storage and synchronisation to system clock domain
------------------------------------------------------------------------------
trig_fifo_din <= trig & X"00000" &
int_ch_trig(4) & int_ch_trig(3) &
int_ch_trig(2) & int_ch_trig(1) &
"000" & time_trig_d &
"00" & sw_trig_d & ext_trig_d;
trig_fifo_wr <= not trig_fifo_full;
cmp_trig_sync_fifo : generic_async_fifo
generic map (
g_data_width => 33,
g_size => 16,
g_show_ahead => FALSE,
g_with_rd_empty => TRUE,
g_with_rd_full => FALSE,
g_with_rd_almost_empty => FALSE,
g_with_rd_almost_full => FALSE,
g_with_rd_count => FALSE,
g_with_wr_empty => FALSE,
g_with_wr_full => TRUE,
g_with_wr_almost_empty => FALSE,
g_with_wr_almost_full => FALSE,
g_with_wr_count => FALSE,
g_almost_empty_threshold => 0,
g_almost_full_threshold => 0
)
port map(
rst_n_i => fs_rst_n,
clk_wr_i => fs_clk,
d_i => trig_fifo_din,
we_i => trig_fifo_wr,
wr_empty_o => open,
wr_full_o => trig_fifo_full,
wr_almost_empty_o => open,
wr_almost_full_o => open,
wr_count_o => open,
clk_rd_i => sys_clk_i,
q_o => trig_fifo_dout,
rd_i => trig_fifo_rd,
rd_empty_o => trig_fifo_empty,
rd_full_o => open,
rd_almost_empty_o => open,
rd_almost_full_o => open,
rd_count_o => open
);
trig_fifo_rd <= not trig_fifo_empty;
p_trig_storage_sys: process (sys_clk_i, sys_rst_n_i) is
begin
if sys_rst_n_i = '0' then
trig_storage <= (others => '0');
elsif rising_edge(sys_clk_i) then
if trig_fifo_dout(32) = '1' and trig_fifo_empty = '0' then
trig_storage <= trig_fifo_dout(31 downto 0);
end if;
end if;
end process p_trig_storage_sys;
------------------------------------------------------------------------------
-- Under-sampling and trigger alignment
-- When under-sampling is enabled, if the trigger occurs between two
......@@ -967,35 +1008,22 @@ begin
end if;
end process;
-- Internal trigger test mode
int_trig_over_thres_tst <= X"1000" when int_trig_over_thres(1) = '1' else X"0000";
int_trig_over_thres_filt_tst <= X"1000" when int_trig_over_thres_filt(1) = '1' else X"0000";
trig_tst <= X"1000" when trig_align = '1' else X"0000";
-- Delay data to compoensate for internal trigger detection
p_data_delay : process (fs_clk, fs_rst_n)
-- Delay data to compensate for trigger processing
p_data_delay : process (fs_clk)
begin
if fs_rst_n = '0' then
data_calibr_out_d <= (others => (others => '0'));
elsif rising_edge(fs_clk) then
data_calibr_out_d <= data_calibr_out_d(data_calibr_out_d'LEFT-1 downto 0) & data_calibr_out;
if rising_edge(fs_clk) then
data_calibr_out_d1 <= data_calibr_out;
data_calibr_out_d2 <= data_calibr_out_d1;
data_calibr_out_d3 <= data_calibr_out_d2;
end if;
end process p_data_delay;
-- An additional 1 fs_clk period delay is added when internal hw trigger is selected
sync_fifo_din <= (trig_align &
trig_tst & int_trig_over_thres_filt_tst &
int_trig_over_thres_tst &
data_calibr_out_d(3)(15 downto 0)) when int_trig_test_en = '1' else
(trig_align & data_calibr_out_d(3)) when hw_trig_sel = "00" else
(trig_align & data_calibr_out);
-- FOR DEBUG: FR instead of CH1 and SerDes Synced instead of CH2
--sync_fifo_din <= trig_align & serdes_out_data(63 downto 32) &
-- "000000000000000" & serdes_synced &
-- "00000000" & serdes_out_fr;
-- Data to FIFO
sync_fifo_din(64) <= trig_align;
sync_fifo_din(63 downto 0) <= data_calibr_out_d3;
sync_fifo_wr <= undersample_en and serdes_synced and not(sync_fifo_full);
sync_fifo_rd <= not(sync_fifo_empty); -- read sync fifo as soon as data are available
......@@ -1284,7 +1312,7 @@ begin
end process p_acq_fsm_outputs;
------------------------------------------------------------------------------
-- Inserting trigger time-tag after post_trigger samples
-- Inserting trigger information after post_trigger samples
------------------------------------------------------------------------------
p_trig_tag_done : process (sys_clk_i, sys_rst_n_i)
begin
......@@ -1297,8 +1325,7 @@ begin
trig_tag_done <= acq_in_trig_tag and acq_in_trig_tag_d;
-- keep compatibility with trig_tag_data order prior to 5.0 release
trig_tag_data <= X"000000000" & trigger_tag_i.coarse when trig_tag_done = '1' else
trig_tag_data <= X"0" & trig_storage & trigger_tag_i.coarse when trig_tag_done = '1' else
trigger_tag_i.seconds(31 downto 0) & X"000000" & trigger_tag_i.seconds(39 downto 32);
------------------------------------------------------------------------------
......
hdl/adc/rtl/fmc_adc_100Ms_core_pkg.vhd
View file @ 6f31510f
......@@ -9,7 +9,7 @@
-- Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2012-11-16
-- Last update: 2016-06-15
-- Last update: 2018-01-24
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Package for FMC ADC 100Ms/s core.
......@@ -60,7 +60,7 @@ package fmc_adc_100Ms_core_pkg is
sys_rst_n_i : in std_logic;
-- CSR wishbone interface
wb_csr_adr_i : in std_logic_vector(5 downto 0);
wb_csr_adr_i : in std_logic_vector(7 downto 0);
wb_csr_dat_i : in std_logic_vector(31 downto 0);
wb_csr_dat_o : out std_logic_vector(31 downto 0);
wb_csr_cyc_i : in std_logic;
......
hdl/adc/rtl/fmc_adc_100Ms_csr.vhd
View file @ 6f31510f
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/fmc_adc_100Ms_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Created : Mon Jan 22 15:24:47 2018
-- Created : Thu Jan 25 09:51:59 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -21,7 +21,7 @@ entity fmc_adc_100ms_csr is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(5 downto 0);
wb_adr_i : in std_logic_vector(7 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......@@ -48,24 +48,42 @@ signal fmc_adc_100ms_csr_ctl_man_bitslip_sync2 : std_logic ;
signal fmc_adc_100ms_csr_ctl_test_data_en_int : std_logic ;
signal fmc_adc_100ms_csr_ctl_trig_led_int : std_logic ;
signal fmc_adc_100ms_csr_ctl_acq_led_int : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_int : std_logic_vector(1 downto 0);
signal fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_swb : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_swb_delay : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_swb_s0 : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_swb_s1 : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_swb_s2 : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_ex_hw_trig_pol_int : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_ex_hw_trig_pol_sync0 : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_ex_hw_trig_pol_sync1 : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_hw_trig_en_int : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_hw_trig_en_sync0 : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_hw_trig_en_sync1 : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_sw_trig_en_int : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_sw_trig_en_sync0 : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_sw_trig_en_sync1 : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_int_trig_test_en_int : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_int_trig_test_en_sync0 : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_int_trig_test_en_sync1 : std_logic ;
signal fmc_adc_100ms_csr_trig_en_ext_int : std_logic ;
signal fmc_adc_100ms_csr_trig_en_ext_sync0 : std_logic ;
signal fmc_adc_100ms_csr_trig_en_ext_sync1 : std_logic ;
signal fmc_adc_100ms_csr_trig_en_sw_int : std_logic ;
signal fmc_adc_100ms_csr_trig_en_sw_sync0 : std_logic ;
signal fmc_adc_100ms_csr_trig_en_sw_sync1 : std_logic ;
signal fmc_adc_100ms_csr_trig_en_time_int : std_logic ;
signal fmc_adc_100ms_csr_trig_en_time_sync0 : std_logic ;
signal fmc_adc_100ms_csr_trig_en_time_sync1 : std_logic ;
signal fmc_adc_100ms_csr_trig_en_ch1_int : std_logic ;
signal fmc_adc_100ms_csr_trig_en_ch1_sync0 : std_logic ;
signal fmc_adc_100ms_csr_trig_en_ch1_sync1 : std_logic ;
signal fmc_adc_100ms_csr_trig_en_ch2_int : std_logic ;
signal fmc_adc_100ms_csr_trig_en_ch2_sync0 : std_logic ;
signal fmc_adc_100ms_csr_trig_en_ch2_sync1 : std_logic ;
signal fmc_adc_100ms_csr_trig_en_ch3_int : std_logic ;
signal fmc_adc_100ms_csr_trig_en_ch3_sync0 : std_logic ;
signal fmc_adc_100ms_csr_trig_en_ch3_sync1 : std_logic ;
signal fmc_adc_100ms_csr_trig_en_ch4_int : std_logic ;
signal fmc_adc_100ms_csr_trig_en_ch4_sync0 : std_logic ;
signal fmc_adc_100ms_csr_trig_en_ch4_sync1 : std_logic ;
signal fmc_adc_100ms_csr_trig_pol_ext_int : std_logic ;
signal fmc_adc_100ms_csr_trig_pol_ext_sync0 : std_logic ;
signal fmc_adc_100ms_csr_trig_pol_ext_sync1 : std_logic ;
signal fmc_adc_100ms_csr_trig_pol_ch1_int : std_logic ;
signal fmc_adc_100ms_csr_trig_pol_ch1_sync0 : std_logic ;
signal fmc_adc_100ms_csr_trig_pol_ch1_sync1 : std_logic ;
signal fmc_adc_100ms_csr_trig_pol_ch2_int : std_logic ;
signal fmc_adc_100ms_csr_trig_pol_ch2_sync0 : std_logic ;
signal fmc_adc_100ms_csr_trig_pol_ch2_sync1 : std_logic ;
signal fmc_adc_100ms_csr_trig_pol_ch3_int : std_logic ;
signal fmc_adc_100ms_csr_trig_pol_ch3_sync0 : std_logic ;
signal fmc_adc_100ms_csr_trig_pol_ch3_sync1 : std_logic ;
signal fmc_adc_100ms_csr_trig_pol_ch4_int : std_logic ;
signal fmc_adc_100ms_csr_trig_pol_ch4_sync0 : std_logic ;
signal fmc_adc_100ms_csr_trig_pol_ch4_sync1 : std_logic ;
signal fmc_adc_100ms_csr_trig_dly_int : std_logic_vector(31 downto 0);
signal fmc_adc_100ms_csr_sw_trig_wr_int : std_logic ;
signal fmc_adc_100ms_csr_sw_trig_wr_int_delay : std_logic ;
......@@ -99,25 +117,18 @@ signal fmc_adc_100ms_csr_ch1_sta_val_lwb_s2 : std_logic ;
signal fmc_adc_100ms_csr_ch1_gain_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch1_offset_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch1_sat_val_int : std_logic_vector(14 downto 0);
signal fmc_adc_100ms_csr_ch1_trig_trig_en_int : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_trig_en_sync0 : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_trig_en_sync1 : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_trig_pol_int : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_trig_pol_sync0 : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_trig_pol_sync1 : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_reserved_int : std_logic_vector(5 downto 0);
signal fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_int : std_logic_vector(7 downto 0);
signal fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb_delay : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb_s0 : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb_s1 : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb_s2 : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_int_trig_thres_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb_delay : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb_s0 : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb_s1 : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb_s2 : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_thres_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch1_trig_thres_val_swb : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_thres_val_swb_delay : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_thres_val_swb_s0 : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_thres_val_swb_s1 : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_thres_val_swb_s2 : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_thres_hyst_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_delay : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_s0 : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_s1 : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_s2 : std_logic ;
signal fmc_adc_100ms_csr_ch2_ctl_ssr_int : std_logic_vector(6 downto 0);
signal fmc_adc_100ms_csr_ch2_sta_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch2_sta_val_lwb : std_logic ;
......@@ -129,25 +140,18 @@ signal fmc_adc_100ms_csr_ch2_sta_val_lwb_s2 : std_logic ;
signal fmc_adc_100ms_csr_ch2_gain_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch2_offset_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch2_sat_val_int : std_logic_vector(14 downto 0);
signal fmc_adc_100ms_csr_ch2_trig_trig_en_int : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_trig_en_sync0 : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_trig_en_sync1 : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_trig_pol_int : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_trig_pol_sync0 : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_trig_pol_sync1 : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_reserved_int : std_logic_vector(5 downto 0);
signal fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_int : std_logic_vector(7 downto 0);
signal fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb_delay : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb_s0 : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb_s1 : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb_s2 : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_int_trig_thres_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb_delay : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb_s0 : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb_s1 : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb_s2 : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_thres_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch2_trig_thres_val_swb : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_thres_val_swb_delay : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_thres_val_swb_s0 : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_thres_val_swb_s1 : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_thres_val_swb_s2 : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_thres_hyst_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_delay : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_s0 : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_s1 : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_s2 : std_logic ;
signal fmc_adc_100ms_csr_ch3_ctl_ssr_int : std_logic_vector(6 downto 0);
signal fmc_adc_100ms_csr_ch3_sta_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch3_sta_val_lwb : std_logic ;
......@@ -159,25 +163,18 @@ signal fmc_adc_100ms_csr_ch3_sta_val_lwb_s2 : std_logic ;
signal fmc_adc_100ms_csr_ch3_gain_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch3_offset_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch3_sat_val_int : std_logic_vector(14 downto 0);
signal fmc_adc_100ms_csr_ch3_trig_trig_en_int : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_trig_en_sync0 : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_trig_en_sync1 : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_trig_pol_int : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_trig_pol_sync0 : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_trig_pol_sync1 : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_reserved_int : std_logic_vector(5 downto 0);
signal fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_int : std_logic_vector(7 downto 0);
signal fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb_delay : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb_s0 : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb_s1 : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb_s2 : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_int_trig_thres_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb_delay : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb_s0 : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb_s1 : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb_s2 : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_thres_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch3_trig_thres_val_swb : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_thres_val_swb_delay : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_thres_val_swb_s0 : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_thres_val_swb_s1 : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_thres_val_swb_s2 : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_thres_hyst_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_delay : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_s0 : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_s1 : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_s2 : std_logic ;
signal fmc_adc_100ms_csr_ch4_ctl_ssr_int : std_logic_vector(6 downto 0);
signal fmc_adc_100ms_csr_ch4_sta_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch4_sta_val_lwb : std_logic ;
......@@ -189,29 +186,22 @@ signal fmc_adc_100ms_csr_ch4_sta_val_lwb_s2 : std_logic ;
signal fmc_adc_100ms_csr_ch4_gain_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch4_offset_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch4_sat_val_int : std_logic_vector(14 downto 0);
signal fmc_adc_100ms_csr_ch4_trig_trig_en_int : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_trig_en_sync0 : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_trig_en_sync1 : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_trig_pol_int : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_trig_pol_sync0 : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_trig_pol_sync1 : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_reserved_int : std_logic_vector(5 downto 0);
signal fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_int : std_logic_vector(7 downto 0);
signal fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb_delay : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb_s0 : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb_s1 : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb_s2 : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_int_trig_thres_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb_delay : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb_s0 : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb_s1 : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb_s2 : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_thres_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch4_trig_thres_val_swb : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_thres_val_swb_delay : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_thres_val_swb_s0 : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_thres_val_swb_s1 : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_thres_val_swb_s2 : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_thres_hyst_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_delay : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_s0 : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_s1 : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_s2 : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal rwaddr_reg : std_logic_vector(5 downto 0);
signal rwaddr_reg : std_logic_vector(7 downto 0);
signal ack_in_progress : std_logic ;
begin
......@@ -233,13 +223,18 @@ begin
fmc_adc_100ms_csr_ctl_test_data_en_int <= '0';
fmc_adc_100ms_csr_ctl_trig_led_int <= '0';
fmc_adc_100ms_csr_ctl_acq_led_int <= '0';
fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_int <= "00";
fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_swb <= '0';
fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_swb_delay <= '0';
fmc_adc_100ms_csr_trig_cfg_ex_hw_trig_pol_int <= '0';
fmc_adc_100ms_csr_trig_cfg_hw_trig_en_int <= '0';
fmc_adc_100ms_csr_trig_cfg_sw_trig_en_int <= '0';
fmc_adc_100ms_csr_trig_cfg_int_trig_test_en_int <= '0';
fmc_adc_100ms_csr_trig_en_ext_int <= '0';
fmc_adc_100ms_csr_trig_en_sw_int <= '0';
fmc_adc_100ms_csr_trig_en_time_int <= '0';
fmc_adc_100ms_csr_trig_en_ch1_int <= '0';
fmc_adc_100ms_csr_trig_en_ch2_int <= '0';
fmc_adc_100ms_csr_trig_en_ch3_int <= '0';
fmc_adc_100ms_csr_trig_en_ch4_int <= '0';
fmc_adc_100ms_csr_trig_pol_ext_int <= '0';
fmc_adc_100ms_csr_trig_pol_ch1_int <= '0';
fmc_adc_100ms_csr_trig_pol_ch2_int <= '0';
fmc_adc_100ms_csr_trig_pol_ch3_int <= '0';
fmc_adc_100ms_csr_trig_pol_ch4_int <= '0';
fmc_adc_100ms_csr_trig_dly_int <= "00000000000000000000000000000000";
fmc_adc_100ms_csr_sw_trig_wr_int <= '0';
fmc_adc_100ms_csr_sw_trig_wr_int_delay <= '0';
......@@ -259,15 +254,12 @@ begin
fmc_adc_100ms_csr_ch1_gain_val_int <= "0000000000000000";
fmc_adc_100ms_csr_ch1_offset_val_int <= "0000000000000000";
fmc_adc_100ms_csr_ch1_sat_val_int <= "000000000000000";
fmc_adc_100ms_csr_ch1_trig_trig_en_int <= '0';
fmc_adc_100ms_csr_ch1_trig_trig_pol_int <= '0';
fmc_adc_100ms_csr_ch1_trig_reserved_int <= "000000";
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_int <= "00000000";
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb <= '0';
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb_delay <= '0';
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_int <= "0000000000000000";
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb <= '0';
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb_delay <= '0';
fmc_adc_100ms_csr_ch1_trig_thres_val_int <= "0000000000000000";
fmc_adc_100ms_csr_ch1_trig_thres_val_swb <= '0';
fmc_adc_100ms_csr_ch1_trig_thres_val_swb_delay <= '0';
fmc_adc_100ms_csr_ch1_trig_thres_hyst_int <= "0000000000000000";
fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb <= '0';
fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_delay <= '0';
fmc_adc_100ms_csr_ch2_ctl_ssr_int <= "0000000";
fmc_adc_100ms_csr_ch2_sta_val_lwb <= '0';
fmc_adc_100ms_csr_ch2_sta_val_lwb_delay <= '0';
......@@ -275,15 +267,12 @@ begin
fmc_adc_100ms_csr_ch2_gain_val_int <= "0000000000000000";
fmc_adc_100ms_csr_ch2_offset_val_int <= "0000000000000000";
fmc_adc_100ms_csr_ch2_sat_val_int <= "000000000000000";
fmc_adc_100ms_csr_ch2_trig_trig_en_int <= '0';
fmc_adc_100ms_csr_ch2_trig_trig_pol_int <= '0';
fmc_adc_100ms_csr_ch2_trig_reserved_int <= "000000";
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_int <= "00000000";
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb <= '0';
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb_delay <= '0';
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_int <= "0000000000000000";
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb <= '0';
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb_delay <= '0';
fmc_adc_100ms_csr_ch2_trig_thres_val_int <= "0000000000000000";
fmc_adc_100ms_csr_ch2_trig_thres_val_swb <= '0';
fmc_adc_100ms_csr_ch2_trig_thres_val_swb_delay <= '0';
fmc_adc_100ms_csr_ch2_trig_thres_hyst_int <= "0000000000000000";
fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb <= '0';
fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_delay <= '0';
fmc_adc_100ms_csr_ch3_ctl_ssr_int <= "0000000";
fmc_adc_100ms_csr_ch3_sta_val_lwb <= '0';
fmc_adc_100ms_csr_ch3_sta_val_lwb_delay <= '0';
......@@ -291,15 +280,12 @@ begin
fmc_adc_100ms_csr_ch3_gain_val_int <= "0000000000000000";
fmc_adc_100ms_csr_ch3_offset_val_int <= "0000000000000000";
fmc_adc_100ms_csr_ch3_sat_val_int <= "000000000000000";
fmc_adc_100ms_csr_ch3_trig_trig_en_int <= '0';
fmc_adc_100ms_csr_ch3_trig_trig_pol_int <= '0';
fmc_adc_100ms_csr_ch3_trig_reserved_int <= "000000";
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_int <= "00000000";
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb <= '0';
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb_delay <= '0';
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_int <= "0000000000000000";
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb <= '0';
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb_delay <= '0';
fmc_adc_100ms_csr_ch3_trig_thres_val_int <= "0000000000000000";
fmc_adc_100ms_csr_ch3_trig_thres_val_swb <= '0';
fmc_adc_100ms_csr_ch3_trig_thres_val_swb_delay <= '0';
fmc_adc_100ms_csr_ch3_trig_thres_hyst_int <= "0000000000000000";
fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb <= '0';
fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_delay <= '0';
fmc_adc_100ms_csr_ch4_ctl_ssr_int <= "0000000";
fmc_adc_100ms_csr_ch4_sta_val_lwb <= '0';
fmc_adc_100ms_csr_ch4_sta_val_lwb_delay <= '0';
......@@ -307,15 +293,12 @@ begin
fmc_adc_100ms_csr_ch4_gain_val_int <= "0000000000000000";
fmc_adc_100ms_csr_ch4_offset_val_int <= "0000000000000000";
fmc_adc_100ms_csr_ch4_sat_val_int <= "000000000000000";
fmc_adc_100ms_csr_ch4_trig_trig_en_int <= '0';
fmc_adc_100ms_csr_ch4_trig_trig_pol_int <= '0';
fmc_adc_100ms_csr_ch4_trig_reserved_int <= "000000";
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_int <= "00000000";
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb <= '0';
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb_delay <= '0';
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_int <= "0000000000000000";
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb <= '0';
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb_delay <= '0';
fmc_adc_100ms_csr_ch4_trig_thres_val_int <= "0000000000000000";
fmc_adc_100ms_csr_ch4_trig_thres_val_swb <= '0';
fmc_adc_100ms_csr_ch4_trig_thres_val_swb_delay <= '0';
fmc_adc_100ms_csr_ch4_trig_thres_hyst_int <= "0000000000000000";
fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb <= '0';
fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_delay <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
......@@ -328,8 +311,6 @@ begin
regs_o.ctl_fsm_cmd_wr_o <= '0';
fmc_adc_100ms_csr_ctl_man_bitslip_int <= fmc_adc_100ms_csr_ctl_man_bitslip_int_delay;
fmc_adc_100ms_csr_ctl_man_bitslip_int_delay <= '0';
fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_swb <= fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_swb_delay;
fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_swb_delay <= '0';
fmc_adc_100ms_csr_sw_trig_wr_int <= fmc_adc_100ms_csr_sw_trig_wr_int_delay;
fmc_adc_100ms_csr_sw_trig_wr_int_delay <= '0';
fmc_adc_100ms_csr_fs_freq_lwb <= fmc_adc_100ms_csr_fs_freq_lwb_delay;
......@@ -346,45 +327,45 @@ begin
rddata_reg(15 downto 0) <= fmc_adc_100ms_csr_ch1_sta_val_int;
fmc_adc_100ms_csr_ch1_sta_val_lwb_in_progress <= '0';
end if;
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb <= fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb_delay;
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb_delay <= '0';
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb <= fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb_delay;
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb_delay <= '0';
fmc_adc_100ms_csr_ch1_trig_thres_val_swb <= fmc_adc_100ms_csr_ch1_trig_thres_val_swb_delay;
fmc_adc_100ms_csr_ch1_trig_thres_val_swb_delay <= '0';
fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb <= fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_delay;
fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_delay <= '0';
fmc_adc_100ms_csr_ch2_sta_val_lwb <= fmc_adc_100ms_csr_ch2_sta_val_lwb_delay;
fmc_adc_100ms_csr_ch2_sta_val_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (fmc_adc_100ms_csr_ch2_sta_val_lwb_in_progress = '1')) then
rddata_reg(15 downto 0) <= fmc_adc_100ms_csr_ch2_sta_val_int;
fmc_adc_100ms_csr_ch2_sta_val_lwb_in_progress <= '0';
end if;
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb <= fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb_delay;
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb_delay <= '0';
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb <= fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb_delay;
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb_delay <= '0';
fmc_adc_100ms_csr_ch2_trig_thres_val_swb <= fmc_adc_100ms_csr_ch2_trig_thres_val_swb_delay;
fmc_adc_100ms_csr_ch2_trig_thres_val_swb_delay <= '0';
fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb <= fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_delay;
fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_delay <= '0';
fmc_adc_100ms_csr_ch3_sta_val_lwb <= fmc_adc_100ms_csr_ch3_sta_val_lwb_delay;
fmc_adc_100ms_csr_ch3_sta_val_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (fmc_adc_100ms_csr_ch3_sta_val_lwb_in_progress = '1')) then
rddata_reg(15 downto 0) <= fmc_adc_100ms_csr_ch3_sta_val_int;
fmc_adc_100ms_csr_ch3_sta_val_lwb_in_progress <= '0';
end if;
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb <= fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb_delay;
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb_delay <= '0';
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb <= fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb_delay;
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb_delay <= '0';
fmc_adc_100ms_csr_ch3_trig_thres_val_swb <= fmc_adc_100ms_csr_ch3_trig_thres_val_swb_delay;
fmc_adc_100ms_csr_ch3_trig_thres_val_swb_delay <= '0';
fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb <= fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_delay;
fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_delay <= '0';
fmc_adc_100ms_csr_ch4_sta_val_lwb <= fmc_adc_100ms_csr_ch4_sta_val_lwb_delay;
fmc_adc_100ms_csr_ch4_sta_val_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (fmc_adc_100ms_csr_ch4_sta_val_lwb_in_progress = '1')) then
rddata_reg(15 downto 0) <= fmc_adc_100ms_csr_ch4_sta_val_int;
fmc_adc_100ms_csr_ch4_sta_val_lwb_in_progress <= '0';
end if;
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb <= fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb_delay;
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb_delay <= '0';
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb <= fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb_delay;
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb_delay <= '0';
fmc_adc_100ms_csr_ch4_trig_thres_val_swb <= fmc_adc_100ms_csr_ch4_trig_thres_val_swb_delay;
fmc_adc_100ms_csr_ch4_trig_thres_val_swb_delay <= '0';
fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb <= fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_delay;
fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_delay <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(5 downto 0) is
when "000000" =>
case rwaddr_reg(7 downto 0) is
when "00000000" =>
if (wb_we_i = '1') then
regs_o.ctl_fsm_cmd_wr_o <= '1';
fmc_adc_100ms_csr_ctl_fmc_clk_oe_int <= wrdata_reg(2);
......@@ -429,7 +410,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(4) <= '1';
ack_in_progress <= '1';
when "000001" =>
when "00000001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(2 downto 0) <= regs_i.sta_fsm_i;
......@@ -464,27 +445,65 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000010" =>
when "00000010" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_int <= wrdata_reg(1 downto 0);
fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_swb <= '1';
fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_swb_delay <= '1';
fmc_adc_100ms_csr_trig_cfg_ex_hw_trig_pol_int <= wrdata_reg(2);
fmc_adc_100ms_csr_trig_cfg_hw_trig_en_int <= wrdata_reg(3);
fmc_adc_100ms_csr_trig_cfg_sw_trig_en_int <= wrdata_reg(4);
fmc_adc_100ms_csr_trig_cfg_int_trig_test_en_int <= wrdata_reg(5);
end if;
rddata_reg(1 downto 0) <= fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_int;
rddata_reg(2) <= fmc_adc_100ms_csr_trig_cfg_ex_hw_trig_pol_int;
rddata_reg(3) <= fmc_adc_100ms_csr_trig_cfg_hw_trig_en_int;
rddata_reg(4) <= fmc_adc_100ms_csr_trig_cfg_sw_trig_en_int;
rddata_reg(5) <= fmc_adc_100ms_csr_trig_cfg_int_trig_test_en_int;
end if;
rddata_reg(0) <= regs_i.trig_stat_ext_i;
rddata_reg(1) <= regs_i.trig_stat_sw_i;
rddata_reg(4) <= regs_i.trig_stat_time_i;
rddata_reg(8) <= regs_i.trig_stat_ch1_i;
rddata_reg(9) <= regs_i.trig_stat_ch2_i;
rddata_reg(10) <= regs_i.trig_stat_ch3_i;
rddata_reg(11) <= regs_i.trig_stat_ch4_i;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00000011" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_trig_en_ext_int <= wrdata_reg(0);
fmc_adc_100ms_csr_trig_en_sw_int <= wrdata_reg(1);
fmc_adc_100ms_csr_trig_en_time_int <= wrdata_reg(4);
fmc_adc_100ms_csr_trig_en_ch1_int <= wrdata_reg(8);
fmc_adc_100ms_csr_trig_en_ch2_int <= wrdata_reg(9);
fmc_adc_100ms_csr_trig_en_ch3_int <= wrdata_reg(10);
fmc_adc_100ms_csr_trig_en_ch4_int <= wrdata_reg(11);
end if;
rddata_reg(0) <= fmc_adc_100ms_csr_trig_en_ext_int;
rddata_reg(1) <= fmc_adc_100ms_csr_trig_en_sw_int;
rddata_reg(4) <= fmc_adc_100ms_csr_trig_en_time_int;
rddata_reg(8) <= fmc_adc_100ms_csr_trig_en_ch1_int;
rddata_reg(9) <= fmc_adc_100ms_csr_trig_en_ch2_int;
rddata_reg(10) <= fmc_adc_100ms_csr_trig_en_ch3_int;
rddata_reg(11) <= fmc_adc_100ms_csr_trig_en_ch4_int;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
......@@ -507,14 +526,56 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "000011" =>
when "00000100" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_trig_pol_ext_int <= wrdata_reg(0);
fmc_adc_100ms_csr_trig_pol_ch1_int <= wrdata_reg(8);
fmc_adc_100ms_csr_trig_pol_ch2_int <= wrdata_reg(9);
fmc_adc_100ms_csr_trig_pol_ch3_int <= wrdata_reg(10);
fmc_adc_100ms_csr_trig_pol_ch4_int <= wrdata_reg(11);
end if;
rddata_reg(0) <= fmc_adc_100ms_csr_trig_pol_ext_int;
rddata_reg(8) <= fmc_adc_100ms_csr_trig_pol_ch1_int;
rddata_reg(9) <= fmc_adc_100ms_csr_trig_pol_ch2_int;
rddata_reg(10) <= fmc_adc_100ms_csr_trig_pol_ch3_int;
rddata_reg(11) <= fmc_adc_100ms_csr_trig_pol_ch4_int;
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "00000101" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_trig_dly_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= fmc_adc_100ms_csr_trig_dly_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000100" =>
when "00000110" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_sw_trig_wr_int <= '1';
fmc_adc_100ms_csr_sw_trig_wr_int_delay <= '1';
......@@ -553,7 +614,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "000101" =>
when "00000111" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_shots_nb_int <= wrdata_reg(15 downto 0);
end if;
......@@ -576,7 +637,13 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000110" =>
when "00001000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.multi_depth_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(15 downto 0) <= regs_i.shots_cnt_val_i;
......@@ -598,13 +665,13 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000111" =>
when "00001010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.trig_pos_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001000" =>
when "00001011" =>
if (wb_we_i = '1') then
end if;
if (wb_we_i = '0') then
......@@ -614,7 +681,7 @@ begin
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "001001" =>
when "00001100" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_sr_undersample_int <= wrdata_reg(31 downto 0);
fmc_adc_100ms_csr_sr_undersample_swb <= '1';
......@@ -623,27 +690,27 @@ begin
rddata_reg(31 downto 0) <= fmc_adc_100ms_csr_sr_undersample_int;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "001010" =>
when "00001101" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_pre_samples_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= fmc_adc_100ms_csr_pre_samples_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001011" =>
when "00001110" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_post_samples_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= fmc_adc_100ms_csr_post_samples_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001100" =>
when "00001111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.samples_cnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001101" =>
when "00100000" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch1_ctl_ssr_int <= wrdata_reg(6 downto 0);
end if;
......@@ -675,7 +742,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001110" =>
when "00100001" =>
if (wb_we_i = '1') then
end if;
if (wb_we_i = '0') then
......@@ -701,7 +768,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "001111" =>
when "00100010" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch1_gain_val_int <= wrdata_reg(15 downto 0);
end if;
......@@ -724,7 +791,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010000" =>
when "00100011" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch1_offset_val_int <= wrdata_reg(15 downto 0);
end if;
......@@ -747,7 +814,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010001" =>
when "00100100" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch1_sat_val_int <= wrdata_reg(14 downto 0);
end if;
......@@ -771,26 +838,20 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010010" =>
when "00100101" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch1_trig_trig_en_int <= wrdata_reg(0);
fmc_adc_100ms_csr_ch1_trig_trig_pol_int <= wrdata_reg(1);
fmc_adc_100ms_csr_ch1_trig_reserved_int <= wrdata_reg(7 downto 2);
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_int <= wrdata_reg(15 downto 8);
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb <= '1';
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb_delay <= '1';
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_int <= wrdata_reg(31 downto 16);
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb <= '1';
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb_delay <= '1';
end if;
rddata_reg(0) <= fmc_adc_100ms_csr_ch1_trig_trig_en_int;
rddata_reg(1) <= fmc_adc_100ms_csr_ch1_trig_trig_pol_int;
rddata_reg(7 downto 2) <= fmc_adc_100ms_csr_ch1_trig_reserved_int;
rddata_reg(15 downto 8) <= fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_int;
rddata_reg(31 downto 16) <= fmc_adc_100ms_csr_ch1_trig_int_trig_thres_int;
fmc_adc_100ms_csr_ch1_trig_thres_val_int <= wrdata_reg(15 downto 0);
fmc_adc_100ms_csr_ch1_trig_thres_val_swb <= '1';
fmc_adc_100ms_csr_ch1_trig_thres_val_swb_delay <= '1';
fmc_adc_100ms_csr_ch1_trig_thres_hyst_int <= wrdata_reg(31 downto 16);
fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb <= '1';
fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_delay <= '1';
end if;
rddata_reg(15 downto 0) <= fmc_adc_100ms_csr_ch1_trig_thres_val_int;
rddata_reg(31 downto 16) <= fmc_adc_100ms_csr_ch1_trig_thres_hyst_int;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "010011" =>
when "01000000" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch2_ctl_ssr_int <= wrdata_reg(6 downto 0);
end if;
......@@ -822,7 +883,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010100" =>
when "01000001" =>
if (wb_we_i = '1') then
end if;
if (wb_we_i = '0') then
......@@ -848,7 +909,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "010101" =>
when "01000010" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch2_gain_val_int <= wrdata_reg(15 downto 0);
end if;
......@@ -871,7 +932,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010110" =>
when "01000011" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch2_offset_val_int <= wrdata_reg(15 downto 0);
end if;
......@@ -894,7 +955,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010111" =>
when "01000100" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch2_sat_val_int <= wrdata_reg(14 downto 0);
end if;
......@@ -918,26 +979,20 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011000" =>
when "01000101" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch2_trig_trig_en_int <= wrdata_reg(0);
fmc_adc_100ms_csr_ch2_trig_trig_pol_int <= wrdata_reg(1);
fmc_adc_100ms_csr_ch2_trig_reserved_int <= wrdata_reg(7 downto 2);
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_int <= wrdata_reg(15 downto 8);
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb <= '1';
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb_delay <= '1';
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_int <= wrdata_reg(31 downto 16);
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb <= '1';
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb_delay <= '1';
end if;
rddata_reg(0) <= fmc_adc_100ms_csr_ch2_trig_trig_en_int;
rddata_reg(1) <= fmc_adc_100ms_csr_ch2_trig_trig_pol_int;
rddata_reg(7 downto 2) <= fmc_adc_100ms_csr_ch2_trig_reserved_int;
rddata_reg(15 downto 8) <= fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_int;
rddata_reg(31 downto 16) <= fmc_adc_100ms_csr_ch2_trig_int_trig_thres_int;
fmc_adc_100ms_csr_ch2_trig_thres_val_int <= wrdata_reg(15 downto 0);
fmc_adc_100ms_csr_ch2_trig_thres_val_swb <= '1';
fmc_adc_100ms_csr_ch2_trig_thres_val_swb_delay <= '1';
fmc_adc_100ms_csr_ch2_trig_thres_hyst_int <= wrdata_reg(31 downto 16);
fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb <= '1';
fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_delay <= '1';
end if;
rddata_reg(15 downto 0) <= fmc_adc_100ms_csr_ch2_trig_thres_val_int;
rddata_reg(31 downto 16) <= fmc_adc_100ms_csr_ch2_trig_thres_hyst_int;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "011001" =>
when "01100000" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch3_ctl_ssr_int <= wrdata_reg(6 downto 0);
end if;
......@@ -969,7 +1024,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011010" =>
when "01100001" =>
if (wb_we_i = '1') then
end if;
if (wb_we_i = '0') then
......@@ -995,7 +1050,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "011011" =>
when "01100010" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch3_gain_val_int <= wrdata_reg(15 downto 0);
end if;
......@@ -1018,7 +1073,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011100" =>
when "01100011" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch3_offset_val_int <= wrdata_reg(15 downto 0);
end if;
......@@ -1041,7 +1096,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011101" =>
when "01100100" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch3_sat_val_int <= wrdata_reg(14 downto 0);
end if;
......@@ -1065,26 +1120,20 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011110" =>
when "01100101" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch3_trig_trig_en_int <= wrdata_reg(0);
fmc_adc_100ms_csr_ch3_trig_trig_pol_int <= wrdata_reg(1);
fmc_adc_100ms_csr_ch3_trig_reserved_int <= wrdata_reg(7 downto 2);
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_int <= wrdata_reg(15 downto 8);
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb <= '1';
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb_delay <= '1';
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_int <= wrdata_reg(31 downto 16);
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb <= '1';
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb_delay <= '1';
end if;
rddata_reg(0) <= fmc_adc_100ms_csr_ch3_trig_trig_en_int;
rddata_reg(1) <= fmc_adc_100ms_csr_ch3_trig_trig_pol_int;
rddata_reg(7 downto 2) <= fmc_adc_100ms_csr_ch3_trig_reserved_int;
rddata_reg(15 downto 8) <= fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_int;
rddata_reg(31 downto 16) <= fmc_adc_100ms_csr_ch3_trig_int_trig_thres_int;
fmc_adc_100ms_csr_ch3_trig_thres_val_int <= wrdata_reg(15 downto 0);
fmc_adc_100ms_csr_ch3_trig_thres_val_swb <= '1';
fmc_adc_100ms_csr_ch3_trig_thres_val_swb_delay <= '1';
fmc_adc_100ms_csr_ch3_trig_thres_hyst_int <= wrdata_reg(31 downto 16);
fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb <= '1';
fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_delay <= '1';
end if;
rddata_reg(15 downto 0) <= fmc_adc_100ms_csr_ch3_trig_thres_val_int;
rddata_reg(31 downto 16) <= fmc_adc_100ms_csr_ch3_trig_thres_hyst_int;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "011111" =>
when "10000000" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch4_ctl_ssr_int <= wrdata_reg(6 downto 0);
end if;
......@@ -1116,7 +1165,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100000" =>
when "10000001" =>
if (wb_we_i = '1') then
end if;
if (wb_we_i = '0') then
......@@ -1142,7 +1191,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "100001" =>
when "10000010" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch4_gain_val_int <= wrdata_reg(15 downto 0);
end if;
......@@ -1165,7 +1214,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100010" =>
when "10000011" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch4_offset_val_int <= wrdata_reg(15 downto 0);
end if;
......@@ -1188,7 +1237,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100011" =>
when "10000100" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch4_sat_val_int <= wrdata_reg(14 downto 0);
end if;
......@@ -1212,31 +1261,19 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100100" =>
when "10000101" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch4_trig_trig_en_int <= wrdata_reg(0);
fmc_adc_100ms_csr_ch4_trig_trig_pol_int <= wrdata_reg(1);
fmc_adc_100ms_csr_ch4_trig_reserved_int <= wrdata_reg(7 downto 2);
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_int <= wrdata_reg(15 downto 8);
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb <= '1';
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb_delay <= '1';
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_int <= wrdata_reg(31 downto 16);
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb <= '1';
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb_delay <= '1';
end if;
rddata_reg(0) <= fmc_adc_100ms_csr_ch4_trig_trig_en_int;
rddata_reg(1) <= fmc_adc_100ms_csr_ch4_trig_trig_pol_int;
rddata_reg(7 downto 2) <= fmc_adc_100ms_csr_ch4_trig_reserved_int;
rddata_reg(15 downto 8) <= fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_int;
rddata_reg(31 downto 16) <= fmc_adc_100ms_csr_ch4_trig_int_trig_thres_int;
fmc_adc_100ms_csr_ch4_trig_thres_val_int <= wrdata_reg(15 downto 0);
fmc_adc_100ms_csr_ch4_trig_thres_val_swb <= '1';
fmc_adc_100ms_csr_ch4_trig_thres_val_swb_delay <= '1';
fmc_adc_100ms_csr_ch4_trig_thres_hyst_int <= wrdata_reg(31 downto 16);
fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb <= '1';
fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_delay <= '1';
end if;
rddata_reg(15 downto 0) <= fmc_adc_100ms_csr_ch4_trig_thres_val_int;
rddata_reg(31 downto 16) <= fmc_adc_100ms_csr_ch4_trig_thres_hyst_int;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "100101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.multi_depth_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
......@@ -1284,86 +1321,201 @@ begin
-- SerDes PLL status
-- SerDes synchronization status
-- Acquisition configuration status
-- Hardware trigger selection
-- asynchronous std_logic_vector register : Hardware trigger selection (type RW/RO, fs_clk_i <-> clk_sys_i)
-- External trigger input
-- Software trigger
-- Timetag trigger
-- Channel 1 internal threshold trigger
-- Channel 2 internal threshold trigger
-- Channel 3 internal threshold trigger
-- Channel 4 internal threshold trigger
-- External trigger input
-- synchronizer chain for field : External trigger input (type RW/RO, clk_sys_i <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.trig_en_ext_o <= '0';
fmc_adc_100ms_csr_trig_en_ext_sync0 <= '0';
fmc_adc_100ms_csr_trig_en_ext_sync1 <= '0';
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_trig_en_ext_sync0 <= fmc_adc_100ms_csr_trig_en_ext_int;
fmc_adc_100ms_csr_trig_en_ext_sync1 <= fmc_adc_100ms_csr_trig_en_ext_sync0;
regs_o.trig_en_ext_o <= fmc_adc_100ms_csr_trig_en_ext_sync1;
end if;
end process;
-- Software trigger
-- synchronizer chain for field : Software trigger (type RW/RO, clk_sys_i <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.trig_en_sw_o <= '0';
fmc_adc_100ms_csr_trig_en_sw_sync0 <= '0';
fmc_adc_100ms_csr_trig_en_sw_sync1 <= '0';
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_trig_en_sw_sync0 <= fmc_adc_100ms_csr_trig_en_sw_int;
fmc_adc_100ms_csr_trig_en_sw_sync1 <= fmc_adc_100ms_csr_trig_en_sw_sync0;
regs_o.trig_en_sw_o <= fmc_adc_100ms_csr_trig_en_sw_sync1;
end if;
end process;
-- Timetag trigger
-- synchronizer chain for field : Timetag trigger (type RW/RO, clk_sys_i <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_swb_s0 <= '0';
fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_swb_s1 <= '0';
fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_swb_s2 <= '0';
regs_o.trig_cfg_hw_trig_sel_o <= "00";
regs_o.trig_en_time_o <= '0';
fmc_adc_100ms_csr_trig_en_time_sync0 <= '0';
fmc_adc_100ms_csr_trig_en_time_sync1 <= '0';
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_swb_s0 <= fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_swb;
fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_swb_s1 <= fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_swb_s0;
fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_swb_s2 <= fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_swb_s1;
if ((fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_swb_s2 = '0') and (fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_swb_s1 = '1')) then
regs_o.trig_cfg_hw_trig_sel_o <= fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_int;
fmc_adc_100ms_csr_trig_en_time_sync0 <= fmc_adc_100ms_csr_trig_en_time_int;
fmc_adc_100ms_csr_trig_en_time_sync1 <= fmc_adc_100ms_csr_trig_en_time_sync0;
regs_o.trig_en_time_o <= fmc_adc_100ms_csr_trig_en_time_sync1;
end if;
end process;
-- Channel 1 internal threshold trigger
-- synchronizer chain for field : Channel 1 internal threshold trigger (type RW/RO, clk_sys_i <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.trig_en_ch1_o <= '0';
fmc_adc_100ms_csr_trig_en_ch1_sync0 <= '0';
fmc_adc_100ms_csr_trig_en_ch1_sync1 <= '0';
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_trig_en_ch1_sync0 <= fmc_adc_100ms_csr_trig_en_ch1_int;
fmc_adc_100ms_csr_trig_en_ch1_sync1 <= fmc_adc_100ms_csr_trig_en_ch1_sync0;
regs_o.trig_en_ch1_o <= fmc_adc_100ms_csr_trig_en_ch1_sync1;
end if;
end process;
-- External Hardware trigger polarity
-- synchronizer chain for field : External Hardware trigger polarity (type RW/RO, clk_sys_i <-> fs_clk_i)
-- Channel 2 internal threshold trigger
-- synchronizer chain for field : Channel 2 internal threshold trigger (type RW/RO, clk_sys_i <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.trig_cfg_ex_hw_trig_pol_o <= '0';
fmc_adc_100ms_csr_trig_cfg_ex_hw_trig_pol_sync0 <= '0';
fmc_adc_100ms_csr_trig_cfg_ex_hw_trig_pol_sync1 <= '0';
regs_o.trig_en_ch2_o <= '0';
fmc_adc_100ms_csr_trig_en_ch2_sync0 <= '0';
fmc_adc_100ms_csr_trig_en_ch2_sync1 <= '0';
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_trig_cfg_ex_hw_trig_pol_sync0 <= fmc_adc_100ms_csr_trig_cfg_ex_hw_trig_pol_int;
fmc_adc_100ms_csr_trig_cfg_ex_hw_trig_pol_sync1 <= fmc_adc_100ms_csr_trig_cfg_ex_hw_trig_pol_sync0;
regs_o.trig_cfg_ex_hw_trig_pol_o <= fmc_adc_100ms_csr_trig_cfg_ex_hw_trig_pol_sync1;
fmc_adc_100ms_csr_trig_en_ch2_sync0 <= fmc_adc_100ms_csr_trig_en_ch2_int;
fmc_adc_100ms_csr_trig_en_ch2_sync1 <= fmc_adc_100ms_csr_trig_en_ch2_sync0;
regs_o.trig_en_ch2_o <= fmc_adc_100ms_csr_trig_en_ch2_sync1;
end if;
end process;
-- Hardware trigger enable
-- synchronizer chain for field : Hardware trigger enable (type RW/RO, clk_sys_i <-> fs_clk_i)
-- Channel 3 internal threshold trigger
-- synchronizer chain for field : Channel 3 internal threshold trigger (type RW/RO, clk_sys_i <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.trig_cfg_hw_trig_en_o <= '0';
fmc_adc_100ms_csr_trig_cfg_hw_trig_en_sync0 <= '0';
fmc_adc_100ms_csr_trig_cfg_hw_trig_en_sync1 <= '0';
regs_o.trig_en_ch3_o <= '0';
fmc_adc_100ms_csr_trig_en_ch3_sync0 <= '0';
fmc_adc_100ms_csr_trig_en_ch3_sync1 <= '0';
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_trig_cfg_hw_trig_en_sync0 <= fmc_adc_100ms_csr_trig_cfg_hw_trig_en_int;
fmc_adc_100ms_csr_trig_cfg_hw_trig_en_sync1 <= fmc_adc_100ms_csr_trig_cfg_hw_trig_en_sync0;
regs_o.trig_cfg_hw_trig_en_o <= fmc_adc_100ms_csr_trig_cfg_hw_trig_en_sync1;
fmc_adc_100ms_csr_trig_en_ch3_sync0 <= fmc_adc_100ms_csr_trig_en_ch3_int;
fmc_adc_100ms_csr_trig_en_ch3_sync1 <= fmc_adc_100ms_csr_trig_en_ch3_sync0;
regs_o.trig_en_ch3_o <= fmc_adc_100ms_csr_trig_en_ch3_sync1;
end if;
end process;
-- Software trigger enable
-- synchronizer chain for field : Software trigger enable (type RW/RO, clk_sys_i <-> fs_clk_i)
-- Channel 4 internal threshold trigger
-- synchronizer chain for field : Channel 4 internal threshold trigger (type RW/RO, clk_sys_i <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.trig_cfg_sw_trig_en_o <= '0';
fmc_adc_100ms_csr_trig_cfg_sw_trig_en_sync0 <= '0';
fmc_adc_100ms_csr_trig_cfg_sw_trig_en_sync1 <= '0';
regs_o.trig_en_ch4_o <= '0';
fmc_adc_100ms_csr_trig_en_ch4_sync0 <= '0';
fmc_adc_100ms_csr_trig_en_ch4_sync1 <= '0';
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_trig_cfg_sw_trig_en_sync0 <= fmc_adc_100ms_csr_trig_cfg_sw_trig_en_int;
fmc_adc_100ms_csr_trig_cfg_sw_trig_en_sync1 <= fmc_adc_100ms_csr_trig_cfg_sw_trig_en_sync0;
regs_o.trig_cfg_sw_trig_en_o <= fmc_adc_100ms_csr_trig_cfg_sw_trig_en_sync1;
fmc_adc_100ms_csr_trig_en_ch4_sync0 <= fmc_adc_100ms_csr_trig_en_ch4_int;
fmc_adc_100ms_csr_trig_en_ch4_sync1 <= fmc_adc_100ms_csr_trig_en_ch4_sync0;
regs_o.trig_en_ch4_o <= fmc_adc_100ms_csr_trig_en_ch4_sync1;
end if;
end process;
-- Enable internal trigger test mode
-- synchronizer chain for field : Enable internal trigger test mode (type RW/RO, clk_sys_i <-> fs_clk_i)
-- External trigger input
-- synchronizer chain for field : External trigger input (type RW/RO, clk_sys_i <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.trig_cfg_int_trig_test_en_o <= '0';
fmc_adc_100ms_csr_trig_cfg_int_trig_test_en_sync0 <= '0';
fmc_adc_100ms_csr_trig_cfg_int_trig_test_en_sync1 <= '0';
regs_o.trig_pol_ext_o <= '0';
fmc_adc_100ms_csr_trig_pol_ext_sync0 <= '0';
fmc_adc_100ms_csr_trig_pol_ext_sync1 <= '0';
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_trig_cfg_int_trig_test_en_sync0 <= fmc_adc_100ms_csr_trig_cfg_int_trig_test_en_int;
fmc_adc_100ms_csr_trig_cfg_int_trig_test_en_sync1 <= fmc_adc_100ms_csr_trig_cfg_int_trig_test_en_sync0;
regs_o.trig_cfg_int_trig_test_en_o <= fmc_adc_100ms_csr_trig_cfg_int_trig_test_en_sync1;
fmc_adc_100ms_csr_trig_pol_ext_sync0 <= fmc_adc_100ms_csr_trig_pol_ext_int;
fmc_adc_100ms_csr_trig_pol_ext_sync1 <= fmc_adc_100ms_csr_trig_pol_ext_sync0;
regs_o.trig_pol_ext_o <= fmc_adc_100ms_csr_trig_pol_ext_sync1;
end if;
end process;
-- Channel 1 internal threshold trigger
-- synchronizer chain for field : Channel 1 internal threshold trigger (type RW/RO, clk_sys_i <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.trig_pol_ch1_o <= '0';
fmc_adc_100ms_csr_trig_pol_ch1_sync0 <= '0';
fmc_adc_100ms_csr_trig_pol_ch1_sync1 <= '0';
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_trig_pol_ch1_sync0 <= fmc_adc_100ms_csr_trig_pol_ch1_int;
fmc_adc_100ms_csr_trig_pol_ch1_sync1 <= fmc_adc_100ms_csr_trig_pol_ch1_sync0;
regs_o.trig_pol_ch1_o <= fmc_adc_100ms_csr_trig_pol_ch1_sync1;
end if;
end process;
-- Channel 2 internal threshold trigger
-- synchronizer chain for field : Channel 2 internal threshold trigger (type RW/RO, clk_sys_i <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.trig_pol_ch2_o <= '0';
fmc_adc_100ms_csr_trig_pol_ch2_sync0 <= '0';
fmc_adc_100ms_csr_trig_pol_ch2_sync1 <= '0';
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_trig_pol_ch2_sync0 <= fmc_adc_100ms_csr_trig_pol_ch2_int;
fmc_adc_100ms_csr_trig_pol_ch2_sync1 <= fmc_adc_100ms_csr_trig_pol_ch2_sync0;
regs_o.trig_pol_ch2_o <= fmc_adc_100ms_csr_trig_pol_ch2_sync1;
end if;
end process;
-- Channel 3 internal threshold trigger
-- synchronizer chain for field : Channel 3 internal threshold trigger (type RW/RO, clk_sys_i <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.trig_pol_ch3_o <= '0';
fmc_adc_100ms_csr_trig_pol_ch3_sync0 <= '0';
fmc_adc_100ms_csr_trig_pol_ch3_sync1 <= '0';
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_trig_pol_ch3_sync0 <= fmc_adc_100ms_csr_trig_pol_ch3_int;
fmc_adc_100ms_csr_trig_pol_ch3_sync1 <= fmc_adc_100ms_csr_trig_pol_ch3_sync0;
regs_o.trig_pol_ch3_o <= fmc_adc_100ms_csr_trig_pol_ch3_sync1;
end if;
end process;
-- Channel 4 internal threshold trigger
-- synchronizer chain for field : Channel 4 internal threshold trigger (type RW/RO, clk_sys_i <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.trig_pol_ch4_o <= '0';
fmc_adc_100ms_csr_trig_pol_ch4_sync0 <= '0';
fmc_adc_100ms_csr_trig_pol_ch4_sync1 <= '0';
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_trig_pol_ch4_sync0 <= fmc_adc_100ms_csr_trig_pol_ch4_int;
fmc_adc_100ms_csr_trig_pol_ch4_sync1 <= fmc_adc_100ms_csr_trig_pol_ch4_sync0;
regs_o.trig_pol_ch4_o <= fmc_adc_100ms_csr_trig_pol_ch4_sync1;
end if;
end process;
......@@ -1390,6 +1542,7 @@ begin
-- Number of shots
regs_o.shots_nb_o <= fmc_adc_100ms_csr_shots_nb_int;
-- Multi-shot sample depth
-- Remaining shots counter
-- Trigger address
-- Sampling clock frequency
......@@ -1465,75 +1618,41 @@ begin
regs_o.ch1_offset_val_o <= fmc_adc_100ms_csr_ch1_offset_val_int;
-- Saturation value for channel 1
regs_o.ch1_sat_val_o <= fmc_adc_100ms_csr_ch1_sat_val_int;
-- Trigger enable for channel 1
-- synchronizer chain for field : Trigger enable for channel 1 (type RW/RO, clk_sys_i <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.ch1_trig_trig_en_o <= '0';
fmc_adc_100ms_csr_ch1_trig_trig_en_sync0 <= '0';
fmc_adc_100ms_csr_ch1_trig_trig_en_sync1 <= '0';
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_ch1_trig_trig_en_sync0 <= fmc_adc_100ms_csr_ch1_trig_trig_en_int;
fmc_adc_100ms_csr_ch1_trig_trig_en_sync1 <= fmc_adc_100ms_csr_ch1_trig_trig_en_sync0;
regs_o.ch1_trig_trig_en_o <= fmc_adc_100ms_csr_ch1_trig_trig_en_sync1;
end if;
end process;
-- Trigger polarity
-- synchronizer chain for field : Trigger polarity (type RW/RO, clk_sys_i <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.ch1_trig_trig_pol_o <= '0';
fmc_adc_100ms_csr_ch1_trig_trig_pol_sync0 <= '0';
fmc_adc_100ms_csr_ch1_trig_trig_pol_sync1 <= '0';
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_ch1_trig_trig_pol_sync0 <= fmc_adc_100ms_csr_ch1_trig_trig_pol_int;
fmc_adc_100ms_csr_ch1_trig_trig_pol_sync1 <= fmc_adc_100ms_csr_ch1_trig_trig_pol_sync0;
regs_o.ch1_trig_trig_pol_o <= fmc_adc_100ms_csr_ch1_trig_trig_pol_sync1;
end if;
end process;
-- Reserved
regs_o.ch1_trig_reserved_o <= fmc_adc_100ms_csr_ch1_trig_reserved_int;
-- Internal trigger threshold glitch filter for Channel 1
-- asynchronous std_logic_vector register : Internal trigger threshold glitch filter for Channel 1 (type RW/RO, fs_clk_i <-> clk_sys_i)
-- Threshold for internal trigger
-- asynchronous std_logic_vector register : Threshold for internal trigger (type RW/RO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb_s0 <= '0';
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb_s1 <= '0';
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb_s2 <= '0';
regs_o.ch1_trig_int_trig_thres_filt_o <= "00000000";
fmc_adc_100ms_csr_ch1_trig_thres_val_swb_s0 <= '0';
fmc_adc_100ms_csr_ch1_trig_thres_val_swb_s1 <= '0';
fmc_adc_100ms_csr_ch1_trig_thres_val_swb_s2 <= '0';
regs_o.ch1_trig_thres_val_o <= "0000000000000000";
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb_s0 <= fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb;
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb_s1 <= fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb_s0;
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb_s2 <= fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb_s1;
if ((fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb_s2 = '0') and (fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb_s1 = '1')) then
regs_o.ch1_trig_int_trig_thres_filt_o <= fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_int;
fmc_adc_100ms_csr_ch1_trig_thres_val_swb_s0 <= fmc_adc_100ms_csr_ch1_trig_thres_val_swb;
fmc_adc_100ms_csr_ch1_trig_thres_val_swb_s1 <= fmc_adc_100ms_csr_ch1_trig_thres_val_swb_s0;
fmc_adc_100ms_csr_ch1_trig_thres_val_swb_s2 <= fmc_adc_100ms_csr_ch1_trig_thres_val_swb_s1;
if ((fmc_adc_100ms_csr_ch1_trig_thres_val_swb_s2 = '0') and (fmc_adc_100ms_csr_ch1_trig_thres_val_swb_s1 = '1')) then
regs_o.ch1_trig_thres_val_o <= fmc_adc_100ms_csr_ch1_trig_thres_val_int;
end if;
end if;
end process;
-- Threshold for Channel 1 internal trigger
-- asynchronous std_logic_vector register : Threshold for Channel 1 internal trigger (type RW/RO, fs_clk_i <-> clk_sys_i)
-- Internal trigger threshold hysteresis
-- asynchronous std_logic_vector register : Internal trigger threshold hysteresis (type RW/RO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb_s0 <= '0';
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb_s1 <= '0';
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb_s2 <= '0';
regs_o.ch1_trig_int_trig_thres_o <= "0000000000000000";
fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_s0 <= '0';
fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_s1 <= '0';
fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_s2 <= '0';
regs_o.ch1_trig_thres_hyst_o <= "0000000000000000";
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb_s0 <= fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb;
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb_s1 <= fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb_s0;
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb_s2 <= fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb_s1;
if ((fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb_s2 = '0') and (fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb_s1 = '1')) then
regs_o.ch1_trig_int_trig_thres_o <= fmc_adc_100ms_csr_ch1_trig_int_trig_thres_int;
fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_s0 <= fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb;
fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_s1 <= fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_s0;
fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_s2 <= fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_s1;
if ((fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_s2 = '0') and (fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_s1 = '1')) then
regs_o.ch1_trig_thres_hyst_o <= fmc_adc_100ms_csr_ch1_trig_thres_hyst_int;
end if;
end if;
end process;
......@@ -1567,75 +1686,41 @@ begin
regs_o.ch2_offset_val_o <= fmc_adc_100ms_csr_ch2_offset_val_int;
-- Saturation value for channel 2
regs_o.ch2_sat_val_o <= fmc_adc_100ms_csr_ch2_sat_val_int;
-- Trigger enable for channel 2
-- synchronizer chain for field : Trigger enable for channel 2 (type RW/RO, clk_sys_i <-> fs_clk_i)
-- Threshold for internal trigger
-- asynchronous std_logic_vector register : Threshold for internal trigger (type RW/RO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.ch2_trig_trig_en_o <= '0';
fmc_adc_100ms_csr_ch2_trig_trig_en_sync0 <= '0';
fmc_adc_100ms_csr_ch2_trig_trig_en_sync1 <= '0';
fmc_adc_100ms_csr_ch2_trig_thres_val_swb_s0 <= '0';
fmc_adc_100ms_csr_ch2_trig_thres_val_swb_s1 <= '0';
fmc_adc_100ms_csr_ch2_trig_thres_val_swb_s2 <= '0';
regs_o.ch2_trig_thres_val_o <= "0000000000000000";
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_ch2_trig_trig_en_sync0 <= fmc_adc_100ms_csr_ch2_trig_trig_en_int;
fmc_adc_100ms_csr_ch2_trig_trig_en_sync1 <= fmc_adc_100ms_csr_ch2_trig_trig_en_sync0;
regs_o.ch2_trig_trig_en_o <= fmc_adc_100ms_csr_ch2_trig_trig_en_sync1;
fmc_adc_100ms_csr_ch2_trig_thres_val_swb_s0 <= fmc_adc_100ms_csr_ch2_trig_thres_val_swb;
fmc_adc_100ms_csr_ch2_trig_thres_val_swb_s1 <= fmc_adc_100ms_csr_ch2_trig_thres_val_swb_s0;
fmc_adc_100ms_csr_ch2_trig_thres_val_swb_s2 <= fmc_adc_100ms_csr_ch2_trig_thres_val_swb_s1;
if ((fmc_adc_100ms_csr_ch2_trig_thres_val_swb_s2 = '0') and (fmc_adc_100ms_csr_ch2_trig_thres_val_swb_s1 = '1')) then
regs_o.ch2_trig_thres_val_o <= fmc_adc_100ms_csr_ch2_trig_thres_val_int;
end if;
end process;
-- Trigger polarity
-- synchronizer chain for field : Trigger polarity (type RW/RO, clk_sys_i <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.ch2_trig_trig_pol_o <= '0';
fmc_adc_100ms_csr_ch2_trig_trig_pol_sync0 <= '0';
fmc_adc_100ms_csr_ch2_trig_trig_pol_sync1 <= '0';
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_ch2_trig_trig_pol_sync0 <= fmc_adc_100ms_csr_ch2_trig_trig_pol_int;
fmc_adc_100ms_csr_ch2_trig_trig_pol_sync1 <= fmc_adc_100ms_csr_ch2_trig_trig_pol_sync0;
regs_o.ch2_trig_trig_pol_o <= fmc_adc_100ms_csr_ch2_trig_trig_pol_sync1;
end if;
end process;
-- Reserved
regs_o.ch2_trig_reserved_o <= fmc_adc_100ms_csr_ch2_trig_reserved_int;
-- Internal trigger threshold glitch filter for Channel 2
-- asynchronous std_logic_vector register : Internal trigger threshold glitch filter for Channel 2 (type RW/RO, fs_clk_i <-> clk_sys_i)
-- Internal trigger threshold hysteresis
-- asynchronous std_logic_vector register : Internal trigger threshold hysteresis (type RW/RO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb_s0 <= '0';
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb_s1 <= '0';
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb_s2 <= '0';
regs_o.ch2_trig_int_trig_thres_filt_o <= "00000000";
fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_s0 <= '0';
fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_s1 <= '0';
fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_s2 <= '0';
regs_o.ch2_trig_thres_hyst_o <= "0000000000000000";
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb_s0 <= fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb;
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb_s1 <= fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb_s0;
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb_s2 <= fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb_s1;
if ((fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb_s2 = '0') and (fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb_s1 = '1')) then
regs_o.ch2_trig_int_trig_thres_filt_o <= fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_int;
end if;
end if;
end process;
-- Threshold for Channel 2 internal trigger
-- asynchronous std_logic_vector register : Threshold for Channel 2 internal trigger (type RW/RO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb_s0 <= '0';
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb_s1 <= '0';
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb_s2 <= '0';
regs_o.ch2_trig_int_trig_thres_o <= "0000000000000000";
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb_s0 <= fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb;
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb_s1 <= fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb_s0;
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb_s2 <= fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb_s1;
if ((fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb_s2 = '0') and (fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb_s1 = '1')) then
regs_o.ch2_trig_int_trig_thres_o <= fmc_adc_100ms_csr_ch2_trig_int_trig_thres_int;
fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_s0 <= fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb;
fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_s1 <= fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_s0;
fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_s2 <= fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_s1;
if ((fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_s2 = '0') and (fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_s1 = '1')) then
regs_o.ch2_trig_thres_hyst_o <= fmc_adc_100ms_csr_ch2_trig_thres_hyst_int;
end if;
end if;
end process;
......@@ -1669,75 +1754,41 @@ begin
regs_o.ch3_offset_val_o <= fmc_adc_100ms_csr_ch3_offset_val_int;
-- Saturation value for channel 3
regs_o.ch3_sat_val_o <= fmc_adc_100ms_csr_ch3_sat_val_int;
-- Trigger enable for channel 3
-- synchronizer chain for field : Trigger enable for channel 3 (type RW/RO, clk_sys_i <-> fs_clk_i)
-- Threshold for internal trigger
-- asynchronous std_logic_vector register : Threshold for internal trigger (type RW/RO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.ch3_trig_trig_en_o <= '0';
fmc_adc_100ms_csr_ch3_trig_trig_en_sync0 <= '0';
fmc_adc_100ms_csr_ch3_trig_trig_en_sync1 <= '0';
fmc_adc_100ms_csr_ch3_trig_thres_val_swb_s0 <= '0';
fmc_adc_100ms_csr_ch3_trig_thres_val_swb_s1 <= '0';
fmc_adc_100ms_csr_ch3_trig_thres_val_swb_s2 <= '0';
regs_o.ch3_trig_thres_val_o <= "0000000000000000";
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_ch3_trig_trig_en_sync0 <= fmc_adc_100ms_csr_ch3_trig_trig_en_int;
fmc_adc_100ms_csr_ch3_trig_trig_en_sync1 <= fmc_adc_100ms_csr_ch3_trig_trig_en_sync0;
regs_o.ch3_trig_trig_en_o <= fmc_adc_100ms_csr_ch3_trig_trig_en_sync1;
fmc_adc_100ms_csr_ch3_trig_thres_val_swb_s0 <= fmc_adc_100ms_csr_ch3_trig_thres_val_swb;
fmc_adc_100ms_csr_ch3_trig_thres_val_swb_s1 <= fmc_adc_100ms_csr_ch3_trig_thres_val_swb_s0;
fmc_adc_100ms_csr_ch3_trig_thres_val_swb_s2 <= fmc_adc_100ms_csr_ch3_trig_thres_val_swb_s1;
if ((fmc_adc_100ms_csr_ch3_trig_thres_val_swb_s2 = '0') and (fmc_adc_100ms_csr_ch3_trig_thres_val_swb_s1 = '1')) then
regs_o.ch3_trig_thres_val_o <= fmc_adc_100ms_csr_ch3_trig_thres_val_int;
end if;
end process;
-- Trigger polarity
-- synchronizer chain for field : Trigger polarity (type RW/RO, clk_sys_i <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.ch3_trig_trig_pol_o <= '0';
fmc_adc_100ms_csr_ch3_trig_trig_pol_sync0 <= '0';
fmc_adc_100ms_csr_ch3_trig_trig_pol_sync1 <= '0';
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_ch3_trig_trig_pol_sync0 <= fmc_adc_100ms_csr_ch3_trig_trig_pol_int;
fmc_adc_100ms_csr_ch3_trig_trig_pol_sync1 <= fmc_adc_100ms_csr_ch3_trig_trig_pol_sync0;
regs_o.ch3_trig_trig_pol_o <= fmc_adc_100ms_csr_ch3_trig_trig_pol_sync1;
end if;
end process;
-- Reserved
regs_o.ch3_trig_reserved_o <= fmc_adc_100ms_csr_ch3_trig_reserved_int;
-- Internal trigger threshold glitch filter for Channel 3
-- asynchronous std_logic_vector register : Internal trigger threshold glitch filter for Channel 3 (type RW/RO, fs_clk_i <-> clk_sys_i)
-- Internal trigger threshold hysteresis
-- asynchronous std_logic_vector register : Internal trigger threshold hysteresis (type RW/RO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb_s0 <= '0';
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb_s1 <= '0';
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb_s2 <= '0';
regs_o.ch3_trig_int_trig_thres_filt_o <= "00000000";
fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_s0 <= '0';
fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_s1 <= '0';
fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_s2 <= '0';
regs_o.ch3_trig_thres_hyst_o <= "0000000000000000";
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb_s0 <= fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb;
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb_s1 <= fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb_s0;
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb_s2 <= fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb_s1;
if ((fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb_s2 = '0') and (fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb_s1 = '1')) then
regs_o.ch3_trig_int_trig_thres_filt_o <= fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_int;
end if;
end if;
end process;
-- Threshold for Channel 3 internal trigger
-- asynchronous std_logic_vector register : Threshold for Channel 3 internal trigger (type RW/RO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb_s0 <= '0';
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb_s1 <= '0';
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb_s2 <= '0';
regs_o.ch3_trig_int_trig_thres_o <= "0000000000000000";
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb_s0 <= fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb;
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb_s1 <= fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb_s0;
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb_s2 <= fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb_s1;
if ((fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb_s2 = '0') and (fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb_s1 = '1')) then
regs_o.ch3_trig_int_trig_thres_o <= fmc_adc_100ms_csr_ch3_trig_int_trig_thres_int;
fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_s0 <= fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb;
fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_s1 <= fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_s0;
fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_s2 <= fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_s1;
if ((fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_s2 = '0') and (fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_s1 = '1')) then
regs_o.ch3_trig_thres_hyst_o <= fmc_adc_100ms_csr_ch3_trig_thres_hyst_int;
end if;
end if;
end process;
......@@ -1771,81 +1822,46 @@ begin
regs_o.ch4_offset_val_o <= fmc_adc_100ms_csr_ch4_offset_val_int;
-- Saturation value for channel 4
regs_o.ch4_sat_val_o <= fmc_adc_100ms_csr_ch4_sat_val_int;
-- Trigger enable for channel 4
-- synchronizer chain for field : Trigger enable for channel 4 (type RW/RO, clk_sys_i <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.ch4_trig_trig_en_o <= '0';
fmc_adc_100ms_csr_ch4_trig_trig_en_sync0 <= '0';
fmc_adc_100ms_csr_ch4_trig_trig_en_sync1 <= '0';
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_ch4_trig_trig_en_sync0 <= fmc_adc_100ms_csr_ch4_trig_trig_en_int;
fmc_adc_100ms_csr_ch4_trig_trig_en_sync1 <= fmc_adc_100ms_csr_ch4_trig_trig_en_sync0;
regs_o.ch4_trig_trig_en_o <= fmc_adc_100ms_csr_ch4_trig_trig_en_sync1;
end if;
end process;
-- trigger polarity
-- synchronizer chain for field : trigger polarity (type RW/RO, clk_sys_i <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.ch4_trig_trig_pol_o <= '0';
fmc_adc_100ms_csr_ch4_trig_trig_pol_sync0 <= '0';
fmc_adc_100ms_csr_ch4_trig_trig_pol_sync1 <= '0';
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_ch4_trig_trig_pol_sync0 <= fmc_adc_100ms_csr_ch4_trig_trig_pol_int;
fmc_adc_100ms_csr_ch4_trig_trig_pol_sync1 <= fmc_adc_100ms_csr_ch4_trig_trig_pol_sync0;
regs_o.ch4_trig_trig_pol_o <= fmc_adc_100ms_csr_ch4_trig_trig_pol_sync1;
end if;
end process;
-- Reserved
regs_o.ch4_trig_reserved_o <= fmc_adc_100ms_csr_ch4_trig_reserved_int;
-- Internal trigger threshold glitch filter for Channel 4
-- asynchronous std_logic_vector register : Internal trigger threshold glitch filter for Channel 4 (type RW/RO, fs_clk_i <-> clk_sys_i)
-- Threshold for internal trigger
-- asynchronous std_logic_vector register : Threshold for internal trigger (type RW/RO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb_s0 <= '0';
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb_s1 <= '0';
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb_s2 <= '0';
regs_o.ch4_trig_int_trig_thres_filt_o <= "00000000";
fmc_adc_100ms_csr_ch4_trig_thres_val_swb_s0 <= '0';
fmc_adc_100ms_csr_ch4_trig_thres_val_swb_s1 <= '0';
fmc_adc_100ms_csr_ch4_trig_thres_val_swb_s2 <= '0';
regs_o.ch4_trig_thres_val_o <= "0000000000000000";
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb_s0 <= fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb;
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb_s1 <= fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb_s0;
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb_s2 <= fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb_s1;
if ((fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb_s2 = '0') and (fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb_s1 = '1')) then
regs_o.ch4_trig_int_trig_thres_filt_o <= fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_int;
fmc_adc_100ms_csr_ch4_trig_thres_val_swb_s0 <= fmc_adc_100ms_csr_ch4_trig_thres_val_swb;
fmc_adc_100ms_csr_ch4_trig_thres_val_swb_s1 <= fmc_adc_100ms_csr_ch4_trig_thres_val_swb_s0;
fmc_adc_100ms_csr_ch4_trig_thres_val_swb_s2 <= fmc_adc_100ms_csr_ch4_trig_thres_val_swb_s1;
if ((fmc_adc_100ms_csr_ch4_trig_thres_val_swb_s2 = '0') and (fmc_adc_100ms_csr_ch4_trig_thres_val_swb_s1 = '1')) then
regs_o.ch4_trig_thres_val_o <= fmc_adc_100ms_csr_ch4_trig_thres_val_int;
end if;
end if;
end process;
-- Threshold for Channel 4 internal trigger
-- asynchronous std_logic_vector register : Threshold for Channel 4 internal trigger (type RW/RO, fs_clk_i <-> clk_sys_i)
-- Internal trigger threshold hysteresis
-- asynchronous std_logic_vector register : Internal trigger threshold hysteresis (type RW/RO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb_s0 <= '0';
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb_s1 <= '0';
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb_s2 <= '0';
regs_o.ch4_trig_int_trig_thres_o <= "0000000000000000";
fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_s0 <= '0';
fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_s1 <= '0';
fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_s2 <= '0';
regs_o.ch4_trig_thres_hyst_o <= "0000000000000000";
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb_s0 <= fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb;
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb_s1 <= fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb_s0;
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb_s2 <= fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb_s1;
if ((fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb_s2 = '0') and (fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb_s1 = '1')) then
regs_o.ch4_trig_int_trig_thres_o <= fmc_adc_100ms_csr_ch4_trig_int_trig_thres_int;
fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_s0 <= fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb;
fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_s1 <= fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_s0;
fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_s2 <= fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_s1;
if ((fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_s2 = '0') and (fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_s1 = '1')) then
regs_o.ch4_trig_thres_hyst_o <= fmc_adc_100ms_csr_ch4_trig_thres_hyst_int;
end if;
end if;
end process;
-- Multi-shot sample depth
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
......
hdl/adc/rtl/fmc_adc_100Ms_csr_wbgen2_pkg.vhd
View file @ 6f31510f
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/fmc_adc_100Ms_csr_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Created : Mon Jan 22 15:24:47 2018
-- Created : Thu Jan 25 09:51:59 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -24,6 +24,14 @@ package fmc_adc_100ms_csr_wbgen2_pkg is
sta_serdes_pll_i : std_logic;
sta_serdes_synced_i : std_logic;
sta_acq_cfg_i : std_logic;
trig_stat_ext_i : std_logic;
trig_stat_sw_i : std_logic;
trig_stat_time_i : std_logic;
trig_stat_ch1_i : std_logic;
trig_stat_ch2_i : std_logic;
trig_stat_ch3_i : std_logic;
trig_stat_ch4_i : std_logic;
multi_depth_i : std_logic_vector(31 downto 0);
shots_cnt_val_i : std_logic_vector(15 downto 0);
trig_pos_i : std_logic_vector(31 downto 0);
fs_freq_i : std_logic_vector(31 downto 0);
......@@ -32,7 +40,6 @@ package fmc_adc_100ms_csr_wbgen2_pkg is
ch2_sta_val_i : std_logic_vector(15 downto 0);
ch3_sta_val_i : std_logic_vector(15 downto 0);
ch4_sta_val_i : std_logic_vector(15 downto 0);
multi_depth_i : std_logic_vector(31 downto 0);
end record;
constant c_fmc_adc_100ms_csr_in_registers_init_value: t_fmc_adc_100ms_csr_in_registers := (
......@@ -40,6 +47,14 @@ package fmc_adc_100ms_csr_wbgen2_pkg is
sta_serdes_pll_i => '0',
sta_serdes_synced_i => '0',
sta_acq_cfg_i => '0',
trig_stat_ext_i => '0',
trig_stat_sw_i => '0',
trig_stat_time_i => '0',
trig_stat_ch1_i => '0',
trig_stat_ch2_i => '0',
trig_stat_ch3_i => '0',
trig_stat_ch4_i => '0',
multi_depth_i => (others => '0'),
shots_cnt_val_i => (others => '0'),
trig_pos_i => (others => '0'),
fs_freq_i => (others => '0'),
......@@ -47,8 +62,7 @@ package fmc_adc_100ms_csr_wbgen2_pkg is
ch1_sta_val_i => (others => '0'),
ch2_sta_val_i => (others => '0'),
ch3_sta_val_i => (others => '0'),
ch4_sta_val_i => (others => '0'),
multi_depth_i => (others => '0')
ch4_sta_val_i => (others => '0')
);
-- Output registers (WB slave -> user design)
......@@ -62,11 +76,18 @@ package fmc_adc_100ms_csr_wbgen2_pkg is
ctl_test_data_en_o : std_logic;
ctl_trig_led_o : std_logic;
ctl_acq_led_o : std_logic;
trig_cfg_hw_trig_sel_o : std_logic_vector(1 downto 0);
trig_cfg_ex_hw_trig_pol_o : std_logic;
trig_cfg_hw_trig_en_o : std_logic;
trig_cfg_sw_trig_en_o : std_logic;
trig_cfg_int_trig_test_en_o : std_logic;
trig_en_ext_o : std_logic;
trig_en_sw_o : std_logic;
trig_en_time_o : std_logic;
trig_en_ch1_o : std_logic;
trig_en_ch2_o : std_logic;
trig_en_ch3_o : std_logic;
trig_en_ch4_o : std_logic;
trig_pol_ext_o : std_logic;
trig_pol_ch1_o : std_logic;
trig_pol_ch2_o : std_logic;
trig_pol_ch3_o : std_logic;
trig_pol_ch4_o : std_logic;
trig_dly_o : std_logic_vector(31 downto 0);
sw_trig_o : std_logic_vector(31 downto 0);
sw_trig_wr_o : std_logic;
......@@ -78,38 +99,26 @@ package fmc_adc_100ms_csr_wbgen2_pkg is
ch1_gain_val_o : std_logic_vector(15 downto 0);
ch1_offset_val_o : std_logic_vector(15 downto 0);
ch1_sat_val_o : std_logic_vector(14 downto 0);
ch1_trig_trig_en_o : std_logic;
ch1_trig_trig_pol_o : std_logic;
ch1_trig_reserved_o : std_logic_vector(5 downto 0);
ch1_trig_int_trig_thres_filt_o : std_logic_vector(7 downto 0);
ch1_trig_int_trig_thres_o : std_logic_vector(15 downto 0);
ch1_trig_thres_val_o : std_logic_vector(15 downto 0);
ch1_trig_thres_hyst_o : std_logic_vector(15 downto 0);
ch2_ctl_ssr_o : std_logic_vector(6 downto 0);
ch2_gain_val_o : std_logic_vector(15 downto 0);
ch2_offset_val_o : std_logic_vector(15 downto 0);
ch2_sat_val_o : std_logic_vector(14 downto 0);
ch2_trig_trig_en_o : std_logic;
ch2_trig_trig_pol_o : std_logic;
ch2_trig_reserved_o : std_logic_vector(5 downto 0);
ch2_trig_int_trig_thres_filt_o : std_logic_vector(7 downto 0);
ch2_trig_int_trig_thres_o : std_logic_vector(15 downto 0);
ch2_trig_thres_val_o : std_logic_vector(15 downto 0);
ch2_trig_thres_hyst_o : std_logic_vector(15 downto 0);
ch3_ctl_ssr_o : std_logic_vector(6 downto 0);
ch3_gain_val_o : std_logic_vector(15 downto 0);
ch3_offset_val_o : std_logic_vector(15 downto 0);
ch3_sat_val_o : std_logic_vector(14 downto 0);
ch3_trig_trig_en_o : std_logic;
ch3_trig_trig_pol_o : std_logic;
ch3_trig_reserved_o : std_logic_vector(5 downto 0);
ch3_trig_int_trig_thres_filt_o : std_logic_vector(7 downto 0);
ch3_trig_int_trig_thres_o : std_logic_vector(15 downto 0);
ch3_trig_thres_val_o : std_logic_vector(15 downto 0);
ch3_trig_thres_hyst_o : std_logic_vector(15 downto 0);
ch4_ctl_ssr_o : std_logic_vector(6 downto 0);
ch4_gain_val_o : std_logic_vector(15 downto 0);
ch4_offset_val_o : std_logic_vector(15 downto 0);
ch4_sat_val_o : std_logic_vector(14 downto 0);
ch4_trig_trig_en_o : std_logic;
ch4_trig_trig_pol_o : std_logic;
ch4_trig_reserved_o : std_logic_vector(5 downto 0);
ch4_trig_int_trig_thres_filt_o : std_logic_vector(7 downto 0);
ch4_trig_int_trig_thres_o : std_logic_vector(15 downto 0);
ch4_trig_thres_val_o : std_logic_vector(15 downto 0);
ch4_trig_thres_hyst_o : std_logic_vector(15 downto 0);
end record;
constant c_fmc_adc_100ms_csr_out_registers_init_value: t_fmc_adc_100ms_csr_out_registers := (
......@@ -121,11 +130,18 @@ package fmc_adc_100ms_csr_wbgen2_pkg is
ctl_test_data_en_o => '0',
ctl_trig_led_o => '0',
ctl_acq_led_o => '0',
trig_cfg_hw_trig_sel_o => (others => '0'),
trig_cfg_ex_hw_trig_pol_o => '0',
trig_cfg_hw_trig_en_o => '0',
trig_cfg_sw_trig_en_o => '0',
trig_cfg_int_trig_test_en_o => '0',
trig_en_ext_o => '0',
trig_en_sw_o => '0',
trig_en_time_o => '0',
trig_en_ch1_o => '0',
trig_en_ch2_o => '0',
trig_en_ch3_o => '0',
trig_en_ch4_o => '0',
trig_pol_ext_o => '0',
trig_pol_ch1_o => '0',
trig_pol_ch2_o => '0',
trig_pol_ch3_o => '0',
trig_pol_ch4_o => '0',
trig_dly_o => (others => '0'),
sw_trig_o => (others => '0'),
sw_trig_wr_o => '0',
......@@ -137,38 +153,26 @@ package fmc_adc_100ms_csr_wbgen2_pkg is
ch1_gain_val_o => (others => '0'),
ch1_offset_val_o => (others => '0'),
ch1_sat_val_o => (others => '0'),
ch1_trig_trig_en_o => '0',
ch1_trig_trig_pol_o => '0',
ch1_trig_reserved_o => (others => '0'),
ch1_trig_int_trig_thres_filt_o => (others => '0'),
ch1_trig_int_trig_thres_o => (others => '0'),
ch1_trig_thres_val_o => (others => '0'),
ch1_trig_thres_hyst_o => (others => '0'),
ch2_ctl_ssr_o => (others => '0'),
ch2_gain_val_o => (others => '0'),
ch2_offset_val_o => (others => '0'),
ch2_sat_val_o => (others => '0'),
ch2_trig_trig_en_o => '0',
ch2_trig_trig_pol_o => '0',
ch2_trig_reserved_o => (others => '0'),
ch2_trig_int_trig_thres_filt_o => (others => '0'),
ch2_trig_int_trig_thres_o => (others => '0'),
ch2_trig_thres_val_o => (others => '0'),
ch2_trig_thres_hyst_o => (others => '0'),
ch3_ctl_ssr_o => (others => '0'),
ch3_gain_val_o => (others => '0'),
ch3_offset_val_o => (others => '0'),
ch3_sat_val_o => (others => '0'),
ch3_trig_trig_en_o => '0',
ch3_trig_trig_pol_o => '0',
ch3_trig_reserved_o => (others => '0'),
ch3_trig_int_trig_thres_filt_o => (others => '0'),
ch3_trig_int_trig_thres_o => (others => '0'),
ch3_trig_thres_val_o => (others => '0'),
ch3_trig_thres_hyst_o => (others => '0'),
ch4_ctl_ssr_o => (others => '0'),
ch4_gain_val_o => (others => '0'),
ch4_offset_val_o => (others => '0'),
ch4_sat_val_o => (others => '0'),
ch4_trig_trig_en_o => '0',
ch4_trig_trig_pol_o => '0',
ch4_trig_reserved_o => (others => '0'),
ch4_trig_int_trig_thres_filt_o => (others => '0'),
ch4_trig_int_trig_thres_o => (others => '0')
ch4_trig_thres_val_o => (others => '0'),
ch4_trig_thres_hyst_o => (others => '0')
);
function "or" (left, right: t_fmc_adc_100ms_csr_in_registers) return t_fmc_adc_100ms_csr_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
......@@ -203,6 +207,14 @@ tmp.sta_fsm_i := f_x_to_zero(left.sta_fsm_i) or f_x_to_zero(right.sta_fsm_i);
tmp.sta_serdes_pll_i := f_x_to_zero(left.sta_serdes_pll_i) or f_x_to_zero(right.sta_serdes_pll_i);
tmp.sta_serdes_synced_i := f_x_to_zero(left.sta_serdes_synced_i) or f_x_to_zero(right.sta_serdes_synced_i);
tmp.sta_acq_cfg_i := f_x_to_zero(left.sta_acq_cfg_i) or f_x_to_zero(right.sta_acq_cfg_i);
tmp.trig_stat_ext_i := f_x_to_zero(left.trig_stat_ext_i) or f_x_to_zero(right.trig_stat_ext_i);
tmp.trig_stat_sw_i := f_x_to_zero(left.trig_stat_sw_i) or f_x_to_zero(right.trig_stat_sw_i);
tmp.trig_stat_time_i := f_x_to_zero(left.trig_stat_time_i) or f_x_to_zero(right.trig_stat_time_i);
tmp.trig_stat_ch1_i := f_x_to_zero(left.trig_stat_ch1_i) or f_x_to_zero(right.trig_stat_ch1_i);
tmp.trig_stat_ch2_i := f_x_to_zero(left.trig_stat_ch2_i) or f_x_to_zero(right.trig_stat_ch2_i);
tmp.trig_stat_ch3_i := f_x_to_zero(left.trig_stat_ch3_i) or f_x_to_zero(right.trig_stat_ch3_i);
tmp.trig_stat_ch4_i := f_x_to_zero(left.trig_stat_ch4_i) or f_x_to_zero(right.trig_stat_ch4_i);
tmp.multi_depth_i := f_x_to_zero(left.multi_depth_i) or f_x_to_zero(right.multi_depth_i);
tmp.shots_cnt_val_i := f_x_to_zero(left.shots_cnt_val_i) or f_x_to_zero(right.shots_cnt_val_i);
tmp.trig_pos_i := f_x_to_zero(left.trig_pos_i) or f_x_to_zero(right.trig_pos_i);
tmp.fs_freq_i := f_x_to_zero(left.fs_freq_i) or f_x_to_zero(right.fs_freq_i);
......@@ -211,7 +223,6 @@ tmp.ch1_sta_val_i := f_x_to_zero(left.ch1_sta_val_i) or f_x_to_zero(right.ch1_st
tmp.ch2_sta_val_i := f_x_to_zero(left.ch2_sta_val_i) or f_x_to_zero(right.ch2_sta_val_i);
tmp.ch3_sta_val_i := f_x_to_zero(left.ch3_sta_val_i) or f_x_to_zero(right.ch3_sta_val_i);
tmp.ch4_sta_val_i := f_x_to_zero(left.ch4_sta_val_i) or f_x_to_zero(right.ch4_sta_val_i);
tmp.multi_depth_i := f_x_to_zero(left.multi_depth_i) or f_x_to_zero(right.multi_depth_i);
return tmp;
end function;
end package body;
hdl/adc/rtl/fmc_adc_mezzanine.vhd
View file @ 6f31510f
......@@ -8,7 +8,7 @@
-- Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2013-05-07
-- Last update: 2016-06-15
-- Last update: 2018-01-24
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: The FMC ADC mezzanine is wrapper around the fmc-adc-100ms core
......@@ -166,10 +166,10 @@ architecture rtl of fmc_adc_mezzanine is
constant c_WB_MASTER : integer := 0;
-- Wishbone slave(s)
constant c_WB_SLAVE_FMC_SYS_I2C : integer := 0; -- Mezzanine system I2C interface (EEPROM)
constant c_WB_SLAVE_FMC_SPI : integer := 1; -- Mezzanine SPI interface
constant c_WB_SLAVE_FMC_I2C : integer := 2; -- Mezzanine I2C controller
constant c_WB_SLAVE_FMC_ADC : integer := 3; -- Mezzanine ADC core
constant c_WB_SLAVE_FMC_ADC : integer := 0; -- Mezzanine ADC core
constant c_WB_SLAVE_FMC_SYS_I2C : integer := 1; -- Mezzanine system I2C interface (EEPROM)
constant c_WB_SLAVE_FMC_SPI : integer := 2; -- Mezzanine SPI interface
constant c_WB_SLAVE_FMC_I2C : integer := 3; -- Mezzanine I2C controller
constant c_WB_SLAVE_FMC_ONEWIRE : integer := 4; -- Mezzanine onewire interface
constant c_WB_SLAVE_FMC_EIC : integer := 5; -- Mezzanine interrupt controller
constant c_WB_SLAVE_TIMETAG : integer := 6; -- Mezzanine timetag core
......@@ -183,7 +183,7 @@ architecture rtl of fmc_adc_mezzanine is
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000FF",
addr_last => x"00000000000003FF",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000608",
......@@ -229,13 +229,13 @@ architecture rtl of fmc_adc_mezzanine is
-- Wishbone crossbar layout
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(6 downto 0) :=
(
0 => f_sdb_embed_device(c_xwb_i2c_master_sdb, x"00001000"),
1 => f_sdb_embed_device(c_xwb_spi_sdb, x"00001100"),
2 => f_sdb_embed_device(c_xwb_i2c_master_sdb, x"00001200"),
3 => f_sdb_embed_device(c_wb_adc_csr_sdb, x"00001300"),
4 => f_sdb_embed_device(c_xwb_onewire_master_sdb, x"00001400"),
5 => f_sdb_embed_device(c_wb_fmc_adc_eic_sdb, x"00001500"),
6 => f_sdb_embed_device(c_wb_timetag_sdb, x"00001600")
0 => f_sdb_embed_device(c_wb_adc_csr_sdb, x"00001000"),
1 => f_sdb_embed_device(c_xwb_i2c_master_sdb, x"00001400"),
2 => f_sdb_embed_device(c_xwb_spi_sdb, x"00001500"),
3 => f_sdb_embed_device(c_xwb_i2c_master_sdb, x"00001600"),
4 => f_sdb_embed_device(c_xwb_onewire_master_sdb, x"00001700"),
5 => f_sdb_embed_device(c_wb_fmc_adc_eic_sdb, x"00001800"),
6 => f_sdb_embed_device(c_wb_timetag_sdb, x"00001900")
);
......@@ -354,12 +354,12 @@ begin
slave_o => cnx_master_in(c_WB_SLAVE_FMC_SYS_I2C),
desc_o => open,
scl_pad_i => sys_scl_in,
scl_pad_o => sys_scl_out,
scl_padoen_o => sys_scl_oe_n,
sda_pad_i => sys_sda_in,
sda_pad_o => sys_sda_out,
sda_padoen_o => sys_sda_oe_n
scl_pad_i(0) => sys_scl_in,
scl_pad_o(0) => sys_scl_out,
scl_padoen_o(0) => sys_scl_oe_n,
sda_pad_i(0) => sys_sda_in,
sda_pad_o(0) => sys_sda_out,
sda_padoen_o(0) => sys_sda_oe_n
);
-- Tri-state buffer for SDA and SCL
......@@ -431,12 +431,12 @@ begin
slave_o => cnx_master_in(c_WB_SLAVE_FMC_I2C),
desc_o => open,
scl_pad_i => si570_scl_in,
scl_pad_o => si570_scl_out,
scl_padoen_o => si570_scl_oe_n,
sda_pad_i => si570_sda_in,
sda_pad_o => si570_sda_out,
sda_padoen_o => si570_sda_oe_n
scl_pad_i(0) => si570_scl_in,
scl_pad_o(0) => si570_scl_out,
scl_padoen_o(0) => si570_scl_oe_n,
sda_pad_i(0) => si570_sda_in,
sda_pad_o(0) => si570_sda_out,
sda_padoen_o(0) => si570_sda_oe_n
);
-- Tri-state buffer for SDA and SCL
......@@ -462,7 +462,7 @@ begin
sys_clk_i => sys_clk_i,
sys_rst_n_i => sys_rst_n_i,
wb_csr_adr_i => cnx_master_out(c_WB_SLAVE_FMC_ADC).adr(7 downto 2), -- cnx_master_out.adr is byte address
wb_csr_adr_i => cnx_master_out(c_WB_SLAVE_FMC_ADC).adr(9 downto 2), -- cnx_master_out.adr is byte address
wb_csr_dat_i => cnx_master_out(c_WB_SLAVE_FMC_ADC).dat,
wb_csr_dat_o => cnx_master_in(c_WB_SLAVE_FMC_ADC).dat,
wb_csr_cyc_i => cnx_master_out(c_WB_SLAVE_FMC_ADC).cyc,
......
hdl/adc/wb_gen/Makefile
View file @ 6f31510f
WBGEN2=$(shell which wbgen2)
RTL=../rtl/
SIM=../../spec/testbench/include/
TEX=../../../doc/manual/
all: fmc_adc_100Ms_csr fmc_adc_eic
fmc_adc_100Ms_csr:
$(WBGEN2) -l vhdl -H record -V $(RTL)$@.vhd -p $(RTL)$@_wbgen2_pkg.vhd -f html -D $@.htm -C $@.h $@.wb
$(WBGEN2) -l vhdl -H record -V $(RTL)$@.vhd -p $(RTL)$@_wbgen2_pkg.vhd -f html -D $@.htm -C $@.h -K $(SIM)$@.v $@.wb
$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
fmc_adc_eic:
......
hdl/adc/wb_gen/fmc_adc_100Ms_csr.h
View file @ 6f31510f
......@@ -3,7 +3,7 @@
* File : fmc_adc_100Ms_csr.h
* Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
* Created : Mon Jan 22 15:24:47 2018
* Created : Thu Jan 25 09:52:00 2018
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -78,25 +78,68 @@
/* definitions for field: Acquisition configuration status in reg: Status register */
#define FMC_ADC_100MS_CSR_STA_ACQ_CFG WBGEN2_GEN_MASK(5, 1)
/* definitions for register: Trigger configuration */
/* definitions for register: Trigger status */
/* definitions for field: Hardware trigger selection in reg: Trigger configuration */
#define FMC_ADC_100MS_CSR_TRIG_CFG_HW_TRIG_SEL_MASK WBGEN2_GEN_MASK(0, 2)
#define FMC_ADC_100MS_CSR_TRIG_CFG_HW_TRIG_SEL_SHIFT 0
#define FMC_ADC_100MS_CSR_TRIG_CFG_HW_TRIG_SEL_W(value) WBGEN2_GEN_WRITE(value, 0, 2)
#define FMC_ADC_100MS_CSR_TRIG_CFG_HW_TRIG_SEL_R(reg) WBGEN2_GEN_READ(reg, 0, 2)
/* definitions for field: External trigger input in reg: Trigger status */
#define FMC_ADC_100MS_CSR_TRIG_STAT_EXT WBGEN2_GEN_MASK(0, 1)
/* definitions for field: External Hardware trigger polarity in reg: Trigger configuration */
#define FMC_ADC_100MS_CSR_TRIG_CFG_EX_HW_TRIG_POL WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Software trigger in reg: Trigger status */
#define FMC_ADC_100MS_CSR_TRIG_STAT_SW WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Hardware trigger enable in reg: Trigger configuration */
#define FMC_ADC_100MS_CSR_TRIG_CFG_HW_TRIG_EN WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Timetag trigger in reg: Trigger status */
#define FMC_ADC_100MS_CSR_TRIG_STAT_TIME WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Software trigger enable in reg: Trigger configuration */
#define FMC_ADC_100MS_CSR_TRIG_CFG_SW_TRIG_EN WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Channel 1 internal threshold trigger in reg: Trigger status */
#define FMC_ADC_100MS_CSR_TRIG_STAT_CH1 WBGEN2_GEN_MASK(8, 1)
/* definitions for field: Enable internal trigger test mode in reg: Trigger configuration */
#define FMC_ADC_100MS_CSR_TRIG_CFG_INT_TRIG_TEST_EN WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Channel 2 internal threshold trigger in reg: Trigger status */
#define FMC_ADC_100MS_CSR_TRIG_STAT_CH2 WBGEN2_GEN_MASK(9, 1)
/* definitions for field: Channel 3 internal threshold trigger in reg: Trigger status */
#define FMC_ADC_100MS_CSR_TRIG_STAT_CH3 WBGEN2_GEN_MASK(10, 1)
/* definitions for field: Channel 4 internal threshold trigger in reg: Trigger status */
#define FMC_ADC_100MS_CSR_TRIG_STAT_CH4 WBGEN2_GEN_MASK(11, 1)
/* definitions for register: Trigger enable */
/* definitions for field: External trigger input in reg: Trigger enable */
#define FMC_ADC_100MS_CSR_TRIG_EN_EXT WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Software trigger in reg: Trigger enable */
#define FMC_ADC_100MS_CSR_TRIG_EN_SW WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timetag trigger in reg: Trigger enable */
#define FMC_ADC_100MS_CSR_TRIG_EN_TIME WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Channel 1 internal threshold trigger in reg: Trigger enable */
#define FMC_ADC_100MS_CSR_TRIG_EN_CH1 WBGEN2_GEN_MASK(8, 1)
/* definitions for field: Channel 2 internal threshold trigger in reg: Trigger enable */
#define FMC_ADC_100MS_CSR_TRIG_EN_CH2 WBGEN2_GEN_MASK(9, 1)
/* definitions for field: Channel 3 internal threshold trigger in reg: Trigger enable */
#define FMC_ADC_100MS_CSR_TRIG_EN_CH3 WBGEN2_GEN_MASK(10, 1)
/* definitions for field: Channel 4 internal threshold trigger in reg: Trigger enable */
#define FMC_ADC_100MS_CSR_TRIG_EN_CH4 WBGEN2_GEN_MASK(11, 1)
/* definitions for register: Trigger polarity */
/* definitions for field: External trigger input in reg: Trigger polarity */
#define FMC_ADC_100MS_CSR_TRIG_POL_EXT WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Channel 1 internal threshold trigger in reg: Trigger polarity */
#define FMC_ADC_100MS_CSR_TRIG_POL_CH1 WBGEN2_GEN_MASK(8, 1)
/* definitions for field: Channel 2 internal threshold trigger in reg: Trigger polarity */
#define FMC_ADC_100MS_CSR_TRIG_POL_CH2 WBGEN2_GEN_MASK(9, 1)
/* definitions for field: Channel 3 internal threshold trigger in reg: Trigger polarity */
#define FMC_ADC_100MS_CSR_TRIG_POL_CH3 WBGEN2_GEN_MASK(10, 1)
/* definitions for field: Channel 4 internal threshold trigger in reg: Trigger polarity */
#define FMC_ADC_100MS_CSR_TRIG_POL_CH4 WBGEN2_GEN_MASK(11, 1)
/* definitions for register: Trigger delay */
......@@ -110,6 +153,8 @@
#define FMC_ADC_100MS_CSR_SHOTS_NB_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_100MS_CSR_SHOTS_NB_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: Multi-shot sample depth register */
/* definitions for register: Remaining shots counter */
/* definitions for field: Remaining shots counter in reg: Remaining shots counter */
......@@ -176,31 +221,19 @@
#define FMC_ADC_100MS_CSR_CH1_SAT_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 15)
#define FMC_ADC_100MS_CSR_CH1_SAT_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 15)
/* definitions for register: Channel 1 trigger configuration register */
/* definitions for field: Trigger enable for channel 1 in reg: Channel 1 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH1_TRIG_TRIG_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Trigger polarity in reg: Channel 1 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH1_TRIG_TRIG_POL WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Channel 1 trigger threshold configuration register */
/* definitions for field: Reserved in reg: Channel 1 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH1_TRIG_RESERVED_MASK WBGEN2_GEN_MASK(2, 6)
#define FMC_ADC_100MS_CSR_CH1_TRIG_RESERVED_SHIFT 2
#define FMC_ADC_100MS_CSR_CH1_TRIG_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 2, 6)
#define FMC_ADC_100MS_CSR_CH1_TRIG_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 2, 6)
/* definitions for field: Threshold for internal trigger in reg: Channel 1 trigger threshold configuration register */
#define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_VAL_SHIFT 0
#define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Internal trigger threshold glitch filter for Channel 1 in reg: Channel 1 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH1_TRIG_INT_TRIG_THRES_FILT_MASK WBGEN2_GEN_MASK(8, 8)
#define FMC_ADC_100MS_CSR_CH1_TRIG_INT_TRIG_THRES_FILT_SHIFT 8
#define FMC_ADC_100MS_CSR_CH1_TRIG_INT_TRIG_THRES_FILT_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define FMC_ADC_100MS_CSR_CH1_TRIG_INT_TRIG_THRES_FILT_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
/* definitions for field: Threshold for Channel 1 internal trigger in reg: Channel 1 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH1_TRIG_INT_TRIG_THRES_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_100MS_CSR_CH1_TRIG_INT_TRIG_THRES_SHIFT 16
#define FMC_ADC_100MS_CSR_CH1_TRIG_INT_TRIG_THRES_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_100MS_CSR_CH1_TRIG_INT_TRIG_THRES_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for field: Internal trigger threshold hysteresis in reg: Channel 1 trigger threshold configuration register */
#define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_HYST_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_HYST_SHIFT 16
#define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_HYST_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_HYST_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 2 control register */
......@@ -242,31 +275,19 @@
#define FMC_ADC_100MS_CSR_CH2_SAT_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 15)
#define FMC_ADC_100MS_CSR_CH2_SAT_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 15)
/* definitions for register: Channel 2 trigger configuration register */
/* definitions for field: Trigger enable for channel 2 in reg: Channel 2 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH2_TRIG_TRIG_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for register: Channel 2 trigger threshold configuration register */
/* definitions for field: Trigger polarity in reg: Channel 2 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH2_TRIG_TRIG_POL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Threshold for internal trigger in reg: Channel 2 trigger threshold configuration register */
#define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_VAL_SHIFT 0
#define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Reserved in reg: Channel 2 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH2_TRIG_RESERVED_MASK WBGEN2_GEN_MASK(2, 6)
#define FMC_ADC_100MS_CSR_CH2_TRIG_RESERVED_SHIFT 2
#define FMC_ADC_100MS_CSR_CH2_TRIG_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 2, 6)
#define FMC_ADC_100MS_CSR_CH2_TRIG_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 2, 6)
/* definitions for field: Internal trigger threshold glitch filter for Channel 2 in reg: Channel 2 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH2_TRIG_INT_TRIG_THRES_FILT_MASK WBGEN2_GEN_MASK(8, 8)
#define FMC_ADC_100MS_CSR_CH2_TRIG_INT_TRIG_THRES_FILT_SHIFT 8
#define FMC_ADC_100MS_CSR_CH2_TRIG_INT_TRIG_THRES_FILT_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define FMC_ADC_100MS_CSR_CH2_TRIG_INT_TRIG_THRES_FILT_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
/* definitions for field: Threshold for Channel 2 internal trigger in reg: Channel 2 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH2_TRIG_INT_TRIG_THRES_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_100MS_CSR_CH2_TRIG_INT_TRIG_THRES_SHIFT 16
#define FMC_ADC_100MS_CSR_CH2_TRIG_INT_TRIG_THRES_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_100MS_CSR_CH2_TRIG_INT_TRIG_THRES_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for field: Internal trigger threshold hysteresis in reg: Channel 2 trigger threshold configuration register */
#define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_HYST_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_HYST_SHIFT 16
#define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_HYST_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_HYST_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 3 control register */
......@@ -308,31 +329,19 @@
#define FMC_ADC_100MS_CSR_CH3_SAT_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 15)
#define FMC_ADC_100MS_CSR_CH3_SAT_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 15)
/* definitions for register: Channel 3 trigger configuration register */
/* definitions for field: Trigger enable for channel 3 in reg: Channel 3 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH3_TRIG_TRIG_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Trigger polarity in reg: Channel 3 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH3_TRIG_TRIG_POL WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Channel 3 trigger threshold configuration register */
/* definitions for field: Reserved in reg: Channel 3 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH3_TRIG_RESERVED_MASK WBGEN2_GEN_MASK(2, 6)
#define FMC_ADC_100MS_CSR_CH3_TRIG_RESERVED_SHIFT 2
#define FMC_ADC_100MS_CSR_CH3_TRIG_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 2, 6)
#define FMC_ADC_100MS_CSR_CH3_TRIG_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 2, 6)
/* definitions for field: Threshold for internal trigger in reg: Channel 3 trigger threshold configuration register */
#define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_VAL_SHIFT 0
#define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Internal trigger threshold glitch filter for Channel 3 in reg: Channel 3 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH3_TRIG_INT_TRIG_THRES_FILT_MASK WBGEN2_GEN_MASK(8, 8)
#define FMC_ADC_100MS_CSR_CH3_TRIG_INT_TRIG_THRES_FILT_SHIFT 8
#define FMC_ADC_100MS_CSR_CH3_TRIG_INT_TRIG_THRES_FILT_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define FMC_ADC_100MS_CSR_CH3_TRIG_INT_TRIG_THRES_FILT_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
/* definitions for field: Threshold for Channel 3 internal trigger in reg: Channel 3 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH3_TRIG_INT_TRIG_THRES_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_100MS_CSR_CH3_TRIG_INT_TRIG_THRES_SHIFT 16
#define FMC_ADC_100MS_CSR_CH3_TRIG_INT_TRIG_THRES_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_100MS_CSR_CH3_TRIG_INT_TRIG_THRES_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for field: Internal trigger threshold hysteresis in reg: Channel 3 trigger threshold configuration register */
#define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_HYST_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_HYST_SHIFT 16
#define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_HYST_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_HYST_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 4 control register */
......@@ -374,111 +383,109 @@
#define FMC_ADC_100MS_CSR_CH4_SAT_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 15)
#define FMC_ADC_100MS_CSR_CH4_SAT_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 15)
/* definitions for register: Channel 4 trigger configuration register */
/* definitions for field: Trigger enable for channel 4 in reg: Channel 4 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH4_TRIG_TRIG_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: trigger polarity in reg: Channel 4 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH4_TRIG_TRIG_POL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Reserved in reg: Channel 4 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH4_TRIG_RESERVED_MASK WBGEN2_GEN_MASK(2, 6)
#define FMC_ADC_100MS_CSR_CH4_TRIG_RESERVED_SHIFT 2
#define FMC_ADC_100MS_CSR_CH4_TRIG_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 2, 6)
#define FMC_ADC_100MS_CSR_CH4_TRIG_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 2, 6)
/* definitions for register: Channel 4 trigger threshold configuration register */
/* definitions for field: Internal trigger threshold glitch filter for Channel 4 in reg: Channel 4 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH4_TRIG_INT_TRIG_THRES_FILT_MASK WBGEN2_GEN_MASK(8, 8)
#define FMC_ADC_100MS_CSR_CH4_TRIG_INT_TRIG_THRES_FILT_SHIFT 8
#define FMC_ADC_100MS_CSR_CH4_TRIG_INT_TRIG_THRES_FILT_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define FMC_ADC_100MS_CSR_CH4_TRIG_INT_TRIG_THRES_FILT_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
/* definitions for field: Threshold for internal trigger in reg: Channel 4 trigger threshold configuration register */
#define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_VAL_SHIFT 0
#define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Threshold for Channel 4 internal trigger in reg: Channel 4 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH4_TRIG_INT_TRIG_THRES_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_100MS_CSR_CH4_TRIG_INT_TRIG_THRES_SHIFT 16
#define FMC_ADC_100MS_CSR_CH4_TRIG_INT_TRIG_THRES_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_100MS_CSR_CH4_TRIG_INT_TRIG_THRES_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Multi-shot sample depth register */
/* definitions for field: Internal trigger threshold hysteresis in reg: Channel 4 trigger threshold configuration register */
#define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_HYST_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_HYST_SHIFT 16
#define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_HYST_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_HYST_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
PACKED struct FMC_ADC_100MS_CSR_WB {
/* [0x0]: REG Control register */
uint32_t CTL;
/* [0x4]: REG Status register */
uint32_t STA;
/* [0x8]: REG Trigger configuration */
uint32_t TRIG_CFG;
/* [0xc]: REG Trigger delay */
/* [0x8]: REG Trigger status */
uint32_t TRIG_STAT;
/* [0xc]: REG Trigger enable */
uint32_t TRIG_EN;
/* [0x10]: REG Trigger polarity */
uint32_t TRIG_POL;
/* [0x14]: REG Trigger delay */
uint32_t TRIG_DLY;
/* [0x10]: REG Software trigger */
/* [0x18]: REG Software trigger */
uint32_t SW_TRIG;
/* [0x14]: REG Number of shots */
/* [0x1c]: REG Number of shots */
uint32_t SHOTS;
/* [0x18]: REG Remaining shots counter */
/* [0x20]: REG Multi-shot sample depth register */
uint32_t MULTI_DEPTH;
/* [0x24]: REG Remaining shots counter */
uint32_t SHOTS_CNT;
/* [0x1c]: REG Trigger address register */
/* [0x28]: REG Trigger address register */
uint32_t TRIG_POS;
/* [0x20]: REG Sampling clock frequency */
/* [0x2c]: REG Sampling clock frequency */
uint32_t FS_FREQ;
/* [0x24]: REG Sample rate */
/* [0x30]: REG Sample rate */
uint32_t SR;
/* [0x28]: REG Pre-trigger samples */
/* [0x34]: REG Pre-trigger samples */
uint32_t PRE_SAMPLES;
/* [0x2c]: REG Post-trigger samples */
/* [0x38]: REG Post-trigger samples */
uint32_t POST_SAMPLES;
/* [0x30]: REG Samples counter */
/* [0x3c]: REG Samples counter */
uint32_t SAMPLES_CNT;
/* [0x34]: REG Channel 1 control register */
/* padding to: 32 words */
uint32_t __padding_0[16];
/* [0x80]: REG Channel 1 control register */
uint32_t CH1_CTL;
/* [0x38]: REG Channel 1 status register */
/* [0x84]: REG Channel 1 status register */
uint32_t CH1_STA;
/* [0x3c]: REG Channel 1 gain calibration register */
/* [0x88]: REG Channel 1 gain calibration register */
uint32_t CH1_GAIN;
/* [0x40]: REG Channel 1 offset calibration register */
/* [0x8c]: REG Channel 1 offset calibration register */
uint32_t CH1_OFFSET;
/* [0x44]: REG Channel 1 saturation register */
/* [0x90]: REG Channel 1 saturation register */
uint32_t CH1_SAT;
/* [0x48]: REG Channel 1 trigger configuration register */
uint32_t CH1_TRIG;
/* [0x4c]: REG Channel 2 control register */
/* [0x94]: REG Channel 1 trigger threshold configuration register */
uint32_t CH1_TRIG_THRES;
/* padding to: 64 words */
uint32_t __padding_1[26];
/* [0x100]: REG Channel 2 control register */
uint32_t CH2_CTL;
/* [0x50]: REG Channel 2 status register */
/* [0x104]: REG Channel 2 status register */
uint32_t CH2_STA;
/* [0x54]: REG Channel 2 gain calibration register */
/* [0x108]: REG Channel 2 gain calibration register */
uint32_t CH2_GAIN;
/* [0x58]: REG Channel 2 offset calibration register */
/* [0x10c]: REG Channel 2 offset calibration register */
uint32_t CH2_OFFSET;
/* [0x5c]: REG Channel 2 saturation register */
/* [0x110]: REG Channel 2 saturation register */
uint32_t CH2_SAT;
/* [0x60]: REG Channel 2 trigger configuration register */
uint32_t CH2_TRIG;
/* [0x64]: REG Channel 3 control register */
/* [0x114]: REG Channel 2 trigger threshold configuration register */
uint32_t CH2_TRIG_THRES;
/* padding to: 96 words */
uint32_t __padding_2[26];
/* [0x180]: REG Channel 3 control register */
uint32_t CH3_CTL;
/* [0x68]: REG Channel 3 status register */
/* [0x184]: REG Channel 3 status register */
uint32_t CH3_STA;
/* [0x6c]: REG Channel 3 gain calibration register */
/* [0x188]: REG Channel 3 gain calibration register */
uint32_t CH3_GAIN;
/* [0x70]: REG Channel 3 offset calibration register */
/* [0x18c]: REG Channel 3 offset calibration register */
uint32_t CH3_OFFSET;
/* [0x74]: REG Channel 3 saturation register */
/* [0x190]: REG Channel 3 saturation register */
uint32_t CH3_SAT;
/* [0x78]: REG Channel 3 trigger configuration register */
uint32_t CH3_TRIG;
/* [0x7c]: REG Channel 4 control register */
/* [0x194]: REG Channel 3 trigger threshold configuration register */
uint32_t CH3_TRIG_THRES;
/* padding to: 128 words */
uint32_t __padding_3[26];
/* [0x200]: REG Channel 4 control register */
uint32_t CH4_CTL;
/* [0x80]: REG Channel 4 status register */
/* [0x204]: REG Channel 4 status register */
uint32_t CH4_STA;
/* [0x84]: REG Channel 4 gain calibration register */
/* [0x208]: REG Channel 4 gain calibration register */
uint32_t CH4_GAIN;
/* [0x88]: REG Channel 4 offset calibration register */
/* [0x20c]: REG Channel 4 offset calibration register */
uint32_t CH4_OFFSET;
/* [0x8c]: REG Channel 4 saturation register */
/* [0x210]: REG Channel 4 saturation register */
uint32_t CH4_SAT;
/* [0x90]: REG Channel 4 trigger configuration register */
uint32_t CH4_TRIG;
/* [0x94]: REG Multi-shot sample depth register */
uint32_t MULTI_DEPTH;
/* [0x214]: REG Channel 4 trigger threshold configuration register */
uint32_t CH4_TRIG_THRES;
};
#endif
hdl/adc/wb_gen/fmc_adc_100Ms_csr.htm
View file @ 6f31510f
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hdl/adc/wb_gen/fmc_adc_100Ms_csr.wb
View file @ 6f31510f
......@@ -136,24 +136,96 @@ peripheral {
};
reg {
name = "Trigger configuration";
prefix = "trig_cfg";
name = "Trigger status";
prefix = "trig_stat";
description = "Shows the source(s) of the last received trigger.";
field {
name = "Hardware trigger selection";
description = "00: internal (data threshold)\n01: external (front panel trigger input)\n10: trigger from timetag core\n11: reserved (for WR message-based trigger)";
prefix = "hw_trig_sel";
type = SLV;
size = 2;
name = "External trigger input";
description = "0: not triggered\n1: triggered";
prefix = "ext";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Software trigger";
description = "0: not triggered\n1: triggered";
prefix = "sw";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
align = 4;
name = "Timetag trigger";
description = "0: not triggered\n1: triggered";
prefix = "time";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
align = 8;
name = "Channel 1 internal threshold trigger";
description = "0: not triggered\n1: triggered";
prefix = "ch1";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Channel 2 internal threshold trigger";
description = "0: not triggered\n1: triggered";
prefix = "ch2";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Channel 3 internal threshold trigger";
description = "0: not triggered\n1: triggered";
prefix = "ch3";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Channel 4 internal threshold trigger";
description = "0: not triggered\n1: triggered";
prefix = "ch4";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Trigger enable";
prefix = "trig_en";
field {
name = "External trigger input";
description = "0: disable\n1: enable";
prefix = "ext";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "External Hardware trigger polarity";
description = "0: positive edge/slope\n1: negative edge/slope";
prefix = "ex_hw_trig_pol";
name = "Software trigger";
description = "0: disable\n1: enable";
prefix = "sw";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
......@@ -161,9 +233,10 @@ peripheral {
};
field {
name = "Hardware trigger enable";
align = 4;
name = "Timetag trigger";
description = "0: disable\n1: enable";
prefix = "hw_trig_en";
prefix = "time";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
......@@ -171,9 +244,10 @@ peripheral {
};
field {
name = "Software trigger enable";
align = 8;
name = "Channel 1 internal threshold trigger";
description = "0: disable\n1: enable";
prefix = "sw_trig_en";
prefix = "ch1";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
......@@ -181,27 +255,116 @@ peripheral {
};
field {
name = "Enable internal trigger test mode";
description = "Test mode:\n ch1 = Channel 1 input(analogue)\n ch2 = Channel input over threshold (digital)\n ch3 = Channel input over threshold filtered (digital)\n ch4 = Trigger (digital)";
prefix = "int_trig_test_en";
name = "Channel 2 internal threshold trigger";
description = "0: disable\n1: enable";
prefix = "ch2";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 26;
name = "Channel 3 internal threshold trigger";
description = "0: disable\n1: enable";
prefix = "ch3";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
]]
field {
name = "Channel 4 internal threshold trigger";
description = "0: disable\n1: enable";
prefix = "ch4";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
};
reg {
name = "Trigger polarity";
prefix = "trig_pol";
field {
name = "External trigger input";
description = "0: positive edge/slope\n1: negative edge/slope";
prefix = "ext";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
-- Note: does not make sense to have polarity on soft trigger
-- field {
-- name = "Software trigger";
-- description = "0: positive edge/slope\n1: negative edge/slope";
-- prefix = "sw";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- clock = "fs_clk_i";
-- };
-- Note: does not make sense to have polarity on time trigger
-- field {
-- align = 4;
-- name = "Timetag trigger";
-- description = "0: positive edge/slope\n1: negative edge/slope";
-- prefix = "time";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- clock = "fs_clk_i";
-- };
field {
align = 8;
name = "Channel 1 internal threshold trigger";
description = "0: positive edge/slope\n1: negative edge/slope";
prefix = "ch1";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "Channel 2 internal threshold trigger";
description = "0: positive edge/slope\n1: negative edge/slope";
prefix = "ch2";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "Channel 3 internal threshold trigger";
description = "0: positive edge/slope\n1: negative edge/slope";
prefix = "ch3";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "Channel 4 internal threshold trigger";
description = "0: positive edge/slope\n1: negative edge/slope";
prefix = "ch4";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
};
reg {
......@@ -257,6 +420,20 @@ peripheral {
]]
};
reg {
name = "Multi-shot sample depth register";
prefix = "multi_depth";
field {
name = "Multi-shot sample depth";
description = "Maximum sample depth allowed in multi-shot acquisition mode, excluding two samples already reserved for time tag";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Remaining shots counter";
prefix = "shots_cnt";
......@@ -373,6 +550,7 @@ peripheral {
reg {
name = "Channel 1 control register";
prefix = "ch1_ctl";
align = 0x20;
field {
name = "Solid state relays control for channel 1";
......@@ -502,50 +680,25 @@ peripheral {
};
reg {
name = "Channel 1 trigger configuration register";
prefix = "ch1_trig";
name = "Channel 1 trigger threshold configuration register";
prefix = "ch1_trig_thres";
field {
name = "Trigger enable for channel 1";
discription = "0: disable\n1: enable, Active only if internal trigger in Trigger Configuration is enabled";
prefix = "trig_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "Trigger polarity";
description = "0: positive edge/slope\n1: negative edge/slope";
prefix = "trig_pol";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 6;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Internal trigger threshold glitch filter for Channel 1";
description = "Configures the internal trigger threshold glitch filter length.";
prefix = "int_trig_thres_filt";
name = "Threshold for internal trigger";
description = "Treated as binary two's complement and compared to raw ADC data.";
prefix = "val";
type = SLV;
size = 8;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "Threshold for Channel 1 internal trigger";
description = "Treated as binary two's complement and compared to raw ADC data.";
prefix = "int_trig_thres";
align = 16;
name = "Internal trigger threshold hysteresis";
description = "Configures the internal trigger threshold hysteresis (two's complement).";
prefix = "hyst";
type = SLV;
size = 16;
access_bus = READ_WRITE;
......@@ -557,6 +710,7 @@ peripheral {
reg {
name = "Channel 2 control register";
prefix = "ch2_ctl";
align = 0x20;
field {
name = "Solid state relays control for channel 2";
......@@ -686,50 +840,25 @@ peripheral {
};
reg {
name = "Channel 2 trigger configuration register";
prefix = "ch2_trig";
name = "Channel 2 trigger threshold configuration register";
prefix = "ch2_trig_thres";
field {
name = "Trigger enable for channel 2";
discription = "0: disable\n1: enable, Active only if internal trigger in Trigger Configuration is enabled";
prefix = "trig_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "Trigger polarity";
description = "0: positive edge/slope\n1: negative edge/slope";
prefix = "trig_pol";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 6;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Internal trigger threshold glitch filter for Channel 2";
description = "Configures the internal trigger threshold glitch filter length.";
prefix = "int_trig_thres_filt";
name = "Threshold for internal trigger";
description = "Treated as binary two's complement and compared to raw ADC data.";
prefix = "val";
type = SLV;
size = 8;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "Threshold for Channel 2 internal trigger";
description = "Treated as binary two's complement and compared to raw ADC data.";
prefix = "int_trig_thres";
align = 16;
name = "Internal trigger threshold hysteresis";
description = "Configures the internal trigger threshold hysteresis (two's complement).";
prefix = "hyst";
type = SLV;
size = 16;
access_bus = READ_WRITE;
......@@ -741,6 +870,7 @@ peripheral {
reg {
name = "Channel 3 control register";
prefix = "ch3_ctl";
align = 0x20;
field {
name = "Solid state relays control for channel 3";
......@@ -870,50 +1000,25 @@ peripheral {
};
reg {
name = "Channel 3 trigger configuration register";
prefix = "ch3_trig";
name = "Channel 3 trigger threshold configuration register";
prefix = "ch3_trig_thres";
field {
name = "Trigger enable for channel 3";
discription = "0: disable\n1: enable, Active only if internal trigger in Trigger Configuration is enabled";
prefix = "trig_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "Trigger polarity";
description = "0: positive edge/slope\n1: negative edge/slope";
prefix = "trig_pol";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 6;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Internal trigger threshold glitch filter for Channel 3";
description = "Configures the internal trigger threshold glitch filter length.";
prefix = "int_trig_thres_filt";
name = "Threshold for internal trigger";
description = "Treated as binary two's complement and compared to raw ADC data.";
prefix = "val";
type = SLV;
size = 8;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "Threshold for Channel 3 internal trigger";
description = "Treated as binary two's complement and compared to raw ADC data.";
prefix = "int_trig_thres";
align = 16;
name = "Internal trigger threshold hysteresis";
description = "Configures the internal trigger threshold hysteresis (two's complement).";
prefix = "hyst";
type = SLV;
size = 16;
access_bus = READ_WRITE;
......@@ -925,7 +1030,7 @@ peripheral {
reg {
name = "Channel 4 control register";
prefix = "ch4_ctl";
align = 0x20;
field {
name = "Solid state relays control for channel 4";
description = "Controls input voltage range, termination and DC offset error calibration\n0x23: 100mV range\n0x11: 1V range\n0x45: 10V range\n0x00: Open input\n0x42: 100mV range calibration\n0x40: 1V range calibration\n0x44: 10V range calibration\nBit3 is indepandant of the others and enables the 50ohms termination.";
......@@ -1055,50 +1160,25 @@ peripheral {
reg {
name = "Channel 4 trigger configuration register";
prefix = "ch4_trig";
name = "Channel 4 trigger threshold configuration register";
prefix = "ch4_trig_thres";
field {
name = "Trigger enable for channel 4";
discription = "0: disable\n1: enable, Active only if internal trigger in Trigger Configuration is enabled";
prefix = "trig_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "trigger polarity";
description = "0: positive edge/slope\n1: negative edge/slope";
prefix = "trig_pol";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 6;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Internal trigger threshold glitch filter for Channel 4";
description = "Configures the internal trigger threshold glitch filter length.";
prefix = "int_trig_thres_filt";
name = "Threshold for internal trigger";
description = "Treated as binary two's complement and compared to raw ADC data.";
prefix = "val";
type = SLV;
size = 8;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "Threshold for Channel 4 internal trigger";
description = "Treated as binary two's complement and compared to raw ADC data.";
prefix = "int_trig_thres";
align = 16;
name = "Internal trigger threshold hysteresis";
description = "Configures the internal trigger threshold hysteresis (two's complement).";
prefix = "hyst";
type = SLV;
size = 16;
access_bus = READ_WRITE;
......@@ -1107,18 +1187,4 @@ peripheral {
};
};
reg {
name = "Multi-shot sample depth register";
prefix = "multi_depth";
field {
name = "Multi-shot sample depth";
description = "Maximum sample depth allowed in multi-shot acquisition mode, excluding two samples already reserved for time tag";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
general-cores @ c3cfcfdd
Subproject commit c26ee857158e4a65fd9d2add8b63fcb6fb4691ea
Subproject commit c3cfcfdd48308aeb787fde006cd27f15097f3ed1
hdl/spec/testbench/include/fmc_adc_100Ms_csr.v 0 → 100644
View file @ 6f31510f
`define ADDR_FMC_ADC_100MS_CSR_CTL 10'h0
`define FMC_ADC_100MS_CSR_CTL_FSM_CMD_OFFSET 0
`define FMC_ADC_100MS_CSR_CTL_FSM_CMD 32'h00000003
`define FMC_ADC_100MS_CSR_CTL_FMC_CLK_OE_OFFSET 2
`define FMC_ADC_100MS_CSR_CTL_FMC_CLK_OE 32'h00000004
`define FMC_ADC_100MS_CSR_CTL_OFFSET_DAC_CLR_N_OFFSET 3
`define FMC_ADC_100MS_CSR_CTL_OFFSET_DAC_CLR_N 32'h00000008
`define FMC_ADC_100MS_CSR_CTL_MAN_BITSLIP_OFFSET 4
`define FMC_ADC_100MS_CSR_CTL_MAN_BITSLIP 32'h00000010
`define FMC_ADC_100MS_CSR_CTL_TEST_DATA_EN_OFFSET 5
`define FMC_ADC_100MS_CSR_CTL_TEST_DATA_EN 32'h00000020
`define FMC_ADC_100MS_CSR_CTL_TRIG_LED_OFFSET 6
`define FMC_ADC_100MS_CSR_CTL_TRIG_LED 32'h00000040
`define FMC_ADC_100MS_CSR_CTL_ACQ_LED_OFFSET 7
`define FMC_ADC_100MS_CSR_CTL_ACQ_LED 32'h00000080
`define ADDR_FMC_ADC_100MS_CSR_STA 10'h4
`define FMC_ADC_100MS_CSR_STA_FSM_OFFSET 0
`define FMC_ADC_100MS_CSR_STA_FSM 32'h00000007
`define FMC_ADC_100MS_CSR_STA_SERDES_PLL_OFFSET 3
`define FMC_ADC_100MS_CSR_STA_SERDES_PLL 32'h00000008
`define FMC_ADC_100MS_CSR_STA_SERDES_SYNCED_OFFSET 4
`define FMC_ADC_100MS_CSR_STA_SERDES_SYNCED 32'h00000010
`define FMC_ADC_100MS_CSR_STA_ACQ_CFG_OFFSET 5
`define FMC_ADC_100MS_CSR_STA_ACQ_CFG 32'h00000020
`define ADDR_FMC_ADC_100MS_CSR_TRIG_STAT 10'h8
`define FMC_ADC_100MS_CSR_TRIG_STAT_EXT_OFFSET 0
`define FMC_ADC_100MS_CSR_TRIG_STAT_EXT 32'h00000001
`define FMC_ADC_100MS_CSR_TRIG_STAT_SW_OFFSET 1
`define FMC_ADC_100MS_CSR_TRIG_STAT_SW 32'h00000002
`define FMC_ADC_100MS_CSR_TRIG_STAT_TIME_OFFSET 4
`define FMC_ADC_100MS_CSR_TRIG_STAT_TIME 32'h00000010
`define FMC_ADC_100MS_CSR_TRIG_STAT_CH1_OFFSET 8
`define FMC_ADC_100MS_CSR_TRIG_STAT_CH1 32'h00000100
`define FMC_ADC_100MS_CSR_TRIG_STAT_CH2_OFFSET 9
`define FMC_ADC_100MS_CSR_TRIG_STAT_CH2 32'h00000200
`define FMC_ADC_100MS_CSR_TRIG_STAT_CH3_OFFSET 10
`define FMC_ADC_100MS_CSR_TRIG_STAT_CH3 32'h00000400
`define FMC_ADC_100MS_CSR_TRIG_STAT_CH4_OFFSET 11
`define FMC_ADC_100MS_CSR_TRIG_STAT_CH4 32'h00000800
`define ADDR_FMC_ADC_100MS_CSR_TRIG_EN 10'hc
`define FMC_ADC_100MS_CSR_TRIG_EN_EXT_OFFSET 0
`define FMC_ADC_100MS_CSR_TRIG_EN_EXT 32'h00000001
`define FMC_ADC_100MS_CSR_TRIG_EN_SW_OFFSET 1
`define FMC_ADC_100MS_CSR_TRIG_EN_SW 32'h00000002
`define FMC_ADC_100MS_CSR_TRIG_EN_TIME_OFFSET 4
`define FMC_ADC_100MS_CSR_TRIG_EN_TIME 32'h00000010
`define FMC_ADC_100MS_CSR_TRIG_EN_CH1_OFFSET 8
`define FMC_ADC_100MS_CSR_TRIG_EN_CH1 32'h00000100
`define FMC_ADC_100MS_CSR_TRIG_EN_CH2_OFFSET 9
`define FMC_ADC_100MS_CSR_TRIG_EN_CH2 32'h00000200
`define FMC_ADC_100MS_CSR_TRIG_EN_CH3_OFFSET 10
`define FMC_ADC_100MS_CSR_TRIG_EN_CH3 32'h00000400
`define FMC_ADC_100MS_CSR_TRIG_EN_CH4_OFFSET 11
`define FMC_ADC_100MS_CSR_TRIG_EN_CH4 32'h00000800
`define ADDR_FMC_ADC_100MS_CSR_TRIG_POL 10'h10
`define FMC_ADC_100MS_CSR_TRIG_POL_EXT_OFFSET 0
`define FMC_ADC_100MS_CSR_TRIG_POL_EXT 32'h00000001
`define FMC_ADC_100MS_CSR_TRIG_POL_CH1_OFFSET 8
`define FMC_ADC_100MS_CSR_TRIG_POL_CH1 32'h00000100
`define FMC_ADC_100MS_CSR_TRIG_POL_CH2_OFFSET 9
`define FMC_ADC_100MS_CSR_TRIG_POL_CH2 32'h00000200
`define FMC_ADC_100MS_CSR_TRIG_POL_CH3_OFFSET 10
`define FMC_ADC_100MS_CSR_TRIG_POL_CH3 32'h00000400
`define FMC_ADC_100MS_CSR_TRIG_POL_CH4_OFFSET 11
`define FMC_ADC_100MS_CSR_TRIG_POL_CH4 32'h00000800
`define ADDR_FMC_ADC_100MS_CSR_TRIG_DLY 10'h14
`define ADDR_FMC_ADC_100MS_CSR_SW_TRIG 10'h18
`define ADDR_FMC_ADC_100MS_CSR_SHOTS 10'h1c
`define FMC_ADC_100MS_CSR_SHOTS_NB_OFFSET 0
`define FMC_ADC_100MS_CSR_SHOTS_NB 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_MULTI_DEPTH 10'h20
`define ADDR_FMC_ADC_100MS_CSR_SHOTS_CNT 10'h24
`define FMC_ADC_100MS_CSR_SHOTS_CNT_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_SHOTS_CNT_VAL 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_TRIG_POS 10'h28
`define ADDR_FMC_ADC_100MS_CSR_FS_FREQ 10'h2c
`define ADDR_FMC_ADC_100MS_CSR_SR 10'h30
`define FMC_ADC_100MS_CSR_SR_UNDERSAMPLE_OFFSET 0
`define FMC_ADC_100MS_CSR_SR_UNDERSAMPLE 32'hffffffff
`define ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES 10'h34
`define ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES 10'h38
`define ADDR_FMC_ADC_100MS_CSR_SAMPLES_CNT 10'h3c
`define ADDR_FMC_ADC_100MS_CSR_CH1_CTL 10'h80
`define FMC_ADC_100MS_CSR_CH1_CTL_SSR_OFFSET 0
`define FMC_ADC_100MS_CSR_CH1_CTL_SSR 32'h0000007f
`define ADDR_FMC_ADC_100MS_CSR_CH1_STA 10'h84
`define FMC_ADC_100MS_CSR_CH1_STA_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH1_STA_VAL 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_CH1_GAIN 10'h88
`define FMC_ADC_100MS_CSR_CH1_GAIN_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH1_GAIN_VAL 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_CH1_OFFSET 10'h8c
`define FMC_ADC_100MS_CSR_CH1_OFFSET_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH1_OFFSET_VAL 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_CH1_SAT 10'h90
`define FMC_ADC_100MS_CSR_CH1_SAT_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH1_SAT_VAL 32'h00007fff
`define ADDR_FMC_ADC_100MS_CSR_CH1_TRIG_THRES 10'h94
`define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_VAL 32'h0000ffff
`define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_HYST_OFFSET 16
`define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_HYST 32'hffff0000
`define ADDR_FMC_ADC_100MS_CSR_CH2_CTL 10'h100
`define FMC_ADC_100MS_CSR_CH2_CTL_SSR_OFFSET 0
`define FMC_ADC_100MS_CSR_CH2_CTL_SSR 32'h0000007f
`define ADDR_FMC_ADC_100MS_CSR_CH2_STA 10'h104
`define FMC_ADC_100MS_CSR_CH2_STA_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH2_STA_VAL 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_CH2_GAIN 10'h108
`define FMC_ADC_100MS_CSR_CH2_GAIN_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH2_GAIN_VAL 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_CH2_OFFSET 10'h10c
`define FMC_ADC_100MS_CSR_CH2_OFFSET_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH2_OFFSET_VAL 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_CH2_SAT 10'h110
`define FMC_ADC_100MS_CSR_CH2_SAT_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH2_SAT_VAL 32'h00007fff
`define ADDR_FMC_ADC_100MS_CSR_CH2_TRIG_THRES 10'h114
`define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_VAL 32'h0000ffff
`define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_HYST_OFFSET 16
`define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_HYST 32'hffff0000
`define ADDR_FMC_ADC_100MS_CSR_CH3_CTL 10'h180
`define FMC_ADC_100MS_CSR_CH3_CTL_SSR_OFFSET 0
`define FMC_ADC_100MS_CSR_CH3_CTL_SSR 32'h0000007f
`define ADDR_FMC_ADC_100MS_CSR_CH3_STA 10'h184
`define FMC_ADC_100MS_CSR_CH3_STA_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH3_STA_VAL 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_CH3_GAIN 10'h188
`define FMC_ADC_100MS_CSR_CH3_GAIN_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH3_GAIN_VAL 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_CH3_OFFSET 10'h18c
`define FMC_ADC_100MS_CSR_CH3_OFFSET_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH3_OFFSET_VAL 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_CH3_SAT 10'h190
`define FMC_ADC_100MS_CSR_CH3_SAT_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH3_SAT_VAL 32'h00007fff
`define ADDR_FMC_ADC_100MS_CSR_CH3_TRIG_THRES 10'h194
`define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_VAL 32'h0000ffff
`define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_HYST_OFFSET 16
`define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_HYST 32'hffff0000
`define ADDR_FMC_ADC_100MS_CSR_CH4_CTL 10'h200
`define FMC_ADC_100MS_CSR_CH4_CTL_SSR_OFFSET 0
`define FMC_ADC_100MS_CSR_CH4_CTL_SSR 32'h0000007f
`define ADDR_FMC_ADC_100MS_CSR_CH4_STA 10'h204
`define FMC_ADC_100MS_CSR_CH4_STA_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH4_STA_VAL 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_CH4_GAIN 10'h208
`define FMC_ADC_100MS_CSR_CH4_GAIN_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH4_GAIN_VAL 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_CH4_OFFSET 10'h20c
`define FMC_ADC_100MS_CSR_CH4_OFFSET_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH4_OFFSET_VAL 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_CH4_SAT 10'h210
`define FMC_ADC_100MS_CSR_CH4_SAT_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH4_SAT_VAL 32'h00007fff
`define ADDR_FMC_ADC_100MS_CSR_CH4_TRIG_THRES 10'h214
`define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_VAL 32'h0000ffff
`define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_HYST_OFFSET 16
`define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_HYST 32'hffff0000
hdl/spec/testbench/top/main.sv
View file @ 6f31510f
......@@ -3,8 +3,10 @@
`include "gn4124_bfm.svh"
`include "if_wb_master.svh"
`include "if_wb_slave.svh"
`include "fmc_adc_100Ms_csr.v"
`define CSR_BASE 'h3000
`define TAG_BASE 'h3900
module main;
reg clk_125m_pllref_p = 0;
......@@ -12,8 +14,13 @@ module main;
reg rst_n = 0;
reg adc0_dco = 0;
reg adc0_fr = 0;
reg adc0_fr = 1'b0;
reg ext_trig = 1'b0;
reg adc_data_dir = 1'b0;
reg[3:0] adc0_dat_odd = 4'h0;
reg[3:0] adc0_dat_even = 4'h0;
reg signed [13:0] adc0_data = 0;
always #1.25ns adc0_dco <= ~adc0_dco;
always #4ns clk_125m_pllref_p <= ~clk_125m_pllref_p;
......@@ -39,16 +46,16 @@ module main;
) DUT (
.clk_125m_pllref_p_i(clk_125m_pllref_p),
.clk_125m_pllref_n_i(clk_125m_pllref_n),
.adc0_ext_trigger_p_i(1'b0),
.adc0_ext_trigger_n_i(1'b1),
.adc0_ext_trigger_p_i(ext_trig),
.adc0_ext_trigger_n_i(~ext_trig),
.adc0_dco_p_i(adc0_dco),
.adc0_dco_n_i(~adc0_dco),
.adc0_fr_p_i(~adc0_fr),
.adc0_fr_n_i(adc0_fr),
.adc0_outa_p_i(4'h0),
.adc0_outa_n_i(4'hf),
.adc0_outb_p_i(4'h0),
.adc0_outb_n_i(4'hf),
.adc0_outa_p_i(adc0_dat_odd),
.adc0_outa_n_i(~adc0_dat_odd),
.adc0_outb_p_i(adc0_dat_even),
.adc0_outb_n_i(~adc0_dat_even),
.DDR3_CAS_N (ddr_cas_n),
.DDR3_CK_N(ddr_ck_n),
.DDR3_CK_P (ddr_ck_p),
......@@ -97,17 +104,55 @@ module main;
int adc_div = 0;
always@(posedge adc0_dco)
if(adc_div==1) begin
always@(negedge adc0_dco)
begin
#625ps;
if(adc_div == 1) begin
adc0_fr <= ~adc0_fr;
adc_div <= 0;
end
else begin
adc_div <= adc_div + 1;
end
end
always@(posedge adc0_fr)
begin
if ((adc0_data > 400) || (adc0_data < -400)) begin
adc_data_dir = ~adc_data_dir;
end
if (adc_data_dir == 0) begin
adc0_data = adc0_data + 8;
end
else begin
adc0_data = adc0_data - 8;
end
adc0_dat_odd = {4{adc0_data[13]}};
adc0_dat_even = {4{adc0_data[12]}};
#1250ps;
adc0_dat_odd = {4{adc0_data[11]}};
adc0_dat_even = {4{adc0_data[10]}};
#1250ps;
adc0_dat_odd = {4{adc0_data[9]}};
adc0_dat_even = {4{adc0_data[8]}};
#1250ps;
adc0_dat_odd = {4{adc0_data[7]}};
adc0_dat_even = {4{adc0_data[6]}};
#1250ps;
adc0_dat_odd = {4{adc0_data[5]}};
adc0_dat_even = {4{adc0_data[4]}};
#1250ps;
adc0_dat_odd = {4{adc0_data[3]}};
adc0_dat_even = {4{adc0_data[2]}};
#1250ps;
adc0_dat_odd = {4{adc0_data[1]}};
adc0_dat_even = {4{adc0_data[0]}};
#1250ps;
adc0_dat_odd = {4{1'b0}};
adc0_dat_even = {4{1'b0}};
end
wire[2:0] acq_fsm_state = DUT.cmp_fmc_adc_mezzanine_0.cmp_fmc_adc_100Ms_core.acq_fsm_state;
initial begin
CBusAccessor acc;
......@@ -121,59 +166,133 @@ module main;
//@(posedge DUT.sys_clk_pll_locked);
#15us;
#5us;
acc.read(0, val);
$display("ID: %x", val);
acc.read('h3304, val); // status
acc.read(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_STA, val); // status
$display("STATUS: %x", val);
acc.write('h3308, 'h00000010); // trigger cfg: enable sw trigger
acc.write('h3328, 'h00000000); // #pre-samples
acc.write('h332C, 'h00000010); // #post-samples
acc.write('h3314, 'h00000001); // #nshots: single-shot acq
acc.read('h3304, val); // status
// FMC-ADC core general configuration
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES, 'h00000000);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES, 'h00000001);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SHOTS, 'h00000001);
// FMC-ADC core channel configuration
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH1_GAIN, 'h00008000);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_GAIN, 'h00008000);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_GAIN, 'h00008000);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_GAIN, 'h00008000);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH1_SAT, 'h00007fff);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_SAT, 'h00007fff);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_SAT, 'h00007fff);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_SAT, 'h00007fff);
// FMC-ADC core trigger configuration
val = (16'h100 << `FMC_ADC_100MS_CSR_CH1_TRIG_THRES_HYST_OFFSET) |
(16'h300 << `FMC_ADC_100MS_CSR_CH1_TRIG_THRES_VAL_OFFSET);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH1_TRIG_THRES, val);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_TRIG_THRES, val);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_TRIG_THRES, val);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_TRIG_THRES, val);
val = (1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_SW_OFFSET);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_EN, val);
acc.read(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_STA, val);
$display("STATUS: %x", val);
#5us;
acc.write('h3600, 'h00000032); // timetag core seconds high
acc.write('h3604, 'h00005a34); // timetag core seconds low
acc.write('h3608, 'h00000000); // timetag core ticks
acc.write(`TAG_BASE + 0, 'h00000032); // timetag core seconds high
acc.write(`TAG_BASE + 4, 'h00005a34); // timetag core seconds low
acc.write(`TAG_BASE + 8, 'h00000000); // timetag core ticks
acc.write('h3300, 'h00000001); // FSM start
wait (acq_fsm_state == 1);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CTL, 'h00000001); // FSM start
#1us;
acc.write('h3310, 'hFFFFFFFF); // soft trigger
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SW_TRIG, 'hFFFFFFFF); // soft trigger
#2us;
wait (acq_fsm_state == 1);
acc.write('h3314, 'h00000003); // #nshots: 3x multi-shot acq
#1us;
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SHOTS, 'h00000003); // #nshots: 3x multi-shot acq
acc.write('h3300, 'h00000001); // FSM start
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CTL, 'h00000001); // FSM start
#1us;
acc.write('h3310, 'hFFFFFFFE); // soft trigger
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SW_TRIG, 'hFFFFFFFE); // soft trigger
#1us;
acc.write('h3310, 'hFFFFFFFD); // soft trigger
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SW_TRIG, 'hFFFFFFFD); // soft trigger
#1us;
acc.write('h3310, 'hFFFFFFFC); // soft trigger
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SW_TRIG, 'hFFFFFFFC); // soft trigger
wait (acq_fsm_state == 1);
#1us;
#2us;
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SHOTS, 'h0000008);
// FMC-ADC core trigger configuration
val = (1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_SW_OFFSET) |
(1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_CH1_OFFSET) |
(1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_CH3_OFFSET);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_EN, val);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CTL, 'h00000001); // FSM start
#1us;
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SW_TRIG, 'hFFFFFFFE); // soft trigger
#1us;
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SW_TRIG, 'hFFFFFFFD); // soft trigger
wait (acq_fsm_state == 1);
#1us;
// set time trigger
acc.write(`TAG_BASE + 'h0c, 'h00000032); // timetag core seconds high
acc.write(`TAG_BASE + 'h10, 'h00005a34); // timetag core seconds low
acc.write(`TAG_BASE + 'h14, 'h00000e00); // timetag core ticks
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES, 'h00000010);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES, 'h00000080);
// FMC-ADC core trigger configuration
val = (1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_TIME_OFFSET) |
(1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_EXT_OFFSET);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_EN, val);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SHOTS, 'h0000002);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CTL, 'h00000001); // FSM start
#5us;
ext_trig <= 1'b1;
#100ns;
ext_trig <= 1'b0;
wait (acq_fsm_state == 1);
#1us;
// DMA transfer
acc.write('h100C, 'h00001000); // host addr
acc.write('h1010, 'h00000000);
acc.write('h1014, 'h00001000); // len
acc.write('h1014, 'h00000100); // len
acc.write('h1018, 'h00000000); // next
acc.write('h101C, 'h00000000);
......@@ -184,7 +303,7 @@ module main;
acc.write('h1000, 'h00000001); // xfer start
acc.read('h3304, val); // status
acc.read(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_STA, val);
$display("STATUS: %x", val);
end
......
hdl/spec/testbench/top/wave.do
View file @ 6f31510f
......@@ -122,6 +122,7 @@ add wave -noupdate -group Top /main/DUT/adc0_dco_p_i
add wave -noupdate -group Top /main/DUT/adc0_dco_n_i
add wave -noupdate -group Top /main/DUT/adc0_fr_p_i
add wave -noupdate -group Top /main/DUT/adc0_fr_n_i
add wave -noupdate -group Top /main/adc0_data
add wave -noupdate -group Top /main/DUT/adc0_outa_p_i
add wave -noupdate -group Top /main/DUT/adc0_outa_n_i
add wave -noupdate -group Top /main/DUT/adc0_outb_p_i
......@@ -216,8 +217,11 @@ add wave -noupdate -group Top /main/DUT/led_pwm_cnt
add wave -noupdate -group Top /main/DUT/led_pwm
add wave -noupdate -radix hexadecimal -group MEZ /main/DUT/cmp_fmc_adc_mezzanine_0/cnx_*
add wave -noupdate -radix hexadecimal -group ADC -group SERDES /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_serdes/*
add wave -noupdate -radix hexadecimal -group ADC -group CSR /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/csr_regin
add wave -noupdate -radix hexadecimal -group ADC -group CSR /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/csr_regout
add wave -noupdate -radix hexadecimal -group ADC -group CSR /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_csr_*
add wave -noupdate -radix hexadecimal -group ADC -group offset0 /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr(0)/cmp_offset_gain_calibr/*
add wave -noupdate -radix hexadecimal -group ADC -group comparator0 /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/g_int_trig(1)/cmp_gc_comparator/*
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sys_clk_i
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sys_rst_n_i
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_csr_adr_i
......@@ -273,6 +277,9 @@ add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/offset_calibr
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/gain_calibr
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d1
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d2
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d3
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_out_fr
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_auto_bitslip
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_man_bitslip
......@@ -280,19 +287,26 @@ add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_synced
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/bitslip_sreg
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/ext_trig_a
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/ext_trig
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/int_trig
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/int_trig_thres
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/ext_trig_p
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/ext_trig_n
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/int_trig_data
add wave -noupdate -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/int_trig_over_thres
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/hw_trig
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/hw_trig_t
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/hw_trig_sel
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/hw_trig_en
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sw_trig
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sw_trig_t
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/int_trig_thres
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/int_ch_trig
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/ext_trig_en
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/int_trig_en
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sw_trig_en
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/time_trig_en
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/ext_trig
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sw_trig
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/time_trig
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_fifo_empty
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_fifo_full
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_fifo_rd
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_fifo_wr
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_fifo_din
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_fifo_dout
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_storage
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_delay
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_delay_cnt
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_d
......@@ -307,6 +321,9 @@ add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_wr
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_rd
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_valid
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_ddr_fifo*
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/dpram0*
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/dpram1*
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/gain_calibr
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/offset_calibr
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/acq_fsm_current_state
......
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