serdes bitslip process reset by sys_rst (as it was before rev75)

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@77 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4

serdes bitslip process reset by sys_rst (as it was before rev75)
git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@77 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
7203a4a4 · mcattin · 3a694fd8 · 7203a4a4
Commit 7203a4a4 authored Nov 04, 2011 by mcattin
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fmc_adc_100Ms_core.vhd hdl/adc/rtl/fmc_adc_100Ms_core.vhd +6 -2

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--- a/hdl/adc/rtl/fmc_adc_100Ms_core.vhd
+++ b/hdl/adc/rtl/fmc_adc_100Ms_core.vhd
@@ -555,9 +555,9 @@ begin


  -- serdes bitslip generation
-  p_auto_bitslip : process (fs_clk, fs_rst_n)
+  p_auto_bitslip : process (fs_clk, sys_rst_n_i)
  begin
-    if fs_rst_n = '0' then
+    if sys_rst_n_i = '0' then
      bitslip_sreg        <= std_logic_vector(to_unsigned(1, bitslip_sreg'length));
      serdes_auto_bitslip <= '0';
      serdes_synced       <= '0';
@@ -779,6 +779,10 @@ begin
      );

  sync_fifo_din <= trig_align & serdes_out_data;
+  -- FOR DEBUG: FR instead of CH1 and SerDes Synced instead of CH2
+  --sync_fifo_din <= trig_align & serdes_out_data(63 downto 32) &
+  --                 "000000000000000" & serdes_synced &
+  --                 "00000000" & serdes_out_fr;

  sync_fifo_wr <= decim_en and serdes_synced and not(sync_fifo_full);
  sync_fifo_rd <= sync_fifo_dreq and not(sync_fifo_empty);