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FMC ADC 100M 14b 4cha - Gateware
Commit 89ee4559 authored by mcattin's avatar mcattin
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Add a bit to the FIFO to pass the trigger as well. Reduce FIFO depth to 64 (was 1024). 

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@94 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
parent cdfee3dd
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Showing with 351 additions and 1139 deletions
hdl/spec/ip_cores/.lso
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blk_mem_gen_v4_2
fifo_generator_v6_2
hdl/spec/ip_cores/_xmsgs/pn_parser.xmsgs
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......@@ -8,7 +8,7 @@
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/ip_cores/tmp/_cg/multishot_dpram.vhd&quot; into library work</arg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/ip_cores/tmp/_cg/wb_ddr_fifo.vhd&quot; into library work</arg>
</msg>
</messages>
......
hdl/spec/ip_cores/_xmsgs/xst.xmsgs
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hdl/spec/ip_cores/coregen.cgc
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hdl/spec/ip_cores/coregen.log
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Welcome to Xilinx CORE Generator.
Help system initialized.
Opening project file
/home/mcattin/projects/ddr3_ctrl_core/hdl/spec/ip_cores/coregen.cgp.
/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/ip_cores/coregen.cgp.
Project, 'coregen', initialised from file
'/home/mcattin/projects/ddr3_ctrl_core/hdl/spec/ip_cores/coregen.cgp'.
'/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/ip_cores/coregen.cgp'.
Recustomize and Generate (Under Original Project Settings)Customizing IP...
Release 12.2 - Xilinx CORE Generator IP GUI Launcher M.63c (lin)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Initializing IP model...
Finished initialising IP model.
Cancelled Customization.
Recustomize and Generate (Under Original Project Settings)Customizing IP...
Release 12.2 - Xilinx CORE Generator IP GUI Launcher M.63c (lin)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Initializing IP model...
Finished initialising IP model.
Finished Customizing.
Generating IP...
WARNING:sim:89 - A core named <wb_ddr_fifo> already exists in the output
directory. Output products for this core may be overwritten.
Initializing IP model...
Finished initialising IP model.
XST: HDL Parsing
XST: HDL Elaboration
XST: HDL Synthesis
XST: Advanced HDL Synthesis
XST: Low Level Synthesis
XST: Partition Report
XST: Design Summary
Generating Implementation files.
Generating ISE symbol file...
Generating NGC file.
Finished Generation Stage.
Generating IP instantiation template...
Generating the VHDL instantiation template.
Finished generating IP instantiation template.
Generating metadata file...
Finished generating metadata file.
Generating metadata file...
Finished generating metadata file.
Generating ISE file...
Finished ISE file generation.
Generating FLIST file...
Finished FLIST file generation.
Preparing output directory...
Finished preparing output directory.
Launching readme viewer...
Launched readme viewer.
Moving files to output directory...
Finished moving files to output directory
Saved options for project 'coregen'.
Recustomize and Generate (Under Original Project Settings)Customizing IP...
Release 12.2 - Xilinx CORE Generator IP GUI Launcher M.63c (lin)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Initializing IP model...
Finished initialising IP model.
Cancelled Customization.
Closed project file.
hdl/spec/ip_cores/wb_ddr_fifo.asy
View file @ 89ee4559
......@@ -4,7 +4,7 @@ TEXT 32 32 LEFT 4 wb_ddr_fifo
RECTANGLE Normal 32 32 544 768
LINE Wide 0 80 32 80
PIN 0 80 LEFT 36
PINATTR PinName din[63:0]
PINATTR PinName din[64:0]
PINATTR Polarity IN
LINE Normal 0 144 32 144
PIN 0 144 LEFT 36
......@@ -24,7 +24,7 @@ PINATTR PinName rst
PINATTR Polarity IN
LINE Wide 576 80 544 80
PIN 576 80 RIGHT 36
PINATTR PinName dout[63:0]
PINATTR PinName dout[64:0]
PINATTR Polarity OUT
LINE Normal 576 208 544 208
PIN 576 208 RIGHT 36
......
hdl/spec/ip_cores/wb_ddr_fifo.ngc
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hdl/spec/ip_cores/wb_ddr_fifo.sym
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<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="wb_ddr_fifo">
<symboltype>BLOCK</symboltype>
<timestamp>2011-3-28T13:14:27</timestamp>
<pin polarity="Input" x="0" y="80" name="din[63:0]" />
<timestamp>2011-11-23T13:10:6</timestamp>
<pin polarity="Input" x="0" y="80" name="din[64:0]" />
<pin polarity="Input" x="0" y="144" name="wr_en" />
<pin polarity="Input" x="0" y="240" name="rd_en" />
<pin polarity="Input" x="0" y="336" name="clk" />
<pin polarity="Input" x="144" y="800" name="rst" />
<pin polarity="Output" x="576" y="80" name="dout[63:0]" />
<pin polarity="Output" x="576" y="80" name="dout[64:0]" />
<pin polarity="Output" x="576" y="208" name="full" />
<pin polarity="Output" x="576" y="432" name="empty" />
<pin polarity="Output" x="576" y="528" name="valid" />
......@@ -15,7 +15,7 @@
<text style="fontsize:40;fontname:Arial" x="32" y="32">wb_ddr_fifo</text>
<rect width="512" x="32" y="32" height="736" />
<line x2="32" y1="80" y2="80" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin din[63:0]" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin din[64:0]" />
<line x2="32" y1="144" y2="144" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="144" type="pin wr_en" />
<line x2="32" y1="240" y2="240" x1="0" />
......@@ -25,7 +25,7 @@
<line x2="144" y1="800" y2="768" x1="144" />
<attrtext style="alignment:BCENTER;fontsize:24;fontname:Arial" attrname="PinName" x="144" y="764" type="pin rst" />
<line x2="544" y1="80" y2="80" style="linewidth:W" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="80" type="pin dout[63:0]" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="80" type="pin dout[64:0]" />
<line x2="544" y1="208" y2="208" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="208" type="pin full" />
<line x2="544" y1="432" y2="432" x1="576" />
......
hdl/spec/ip_cores/wb_ddr_fifo.vhd
View file @ 89ee4559
......@@ -44,10 +44,10 @@ ENTITY wb_ddr_fifo IS
port (
clk: IN std_logic;
rst: IN std_logic;
din: IN std_logic_VECTOR(63 downto 0);
din: IN std_logic_VECTOR(64 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(63 downto 0);
dout: OUT std_logic_VECTOR(64 downto 0);
full: OUT std_logic;
empty: OUT std_logic;
valid: OUT std_logic);
......@@ -59,10 +59,10 @@ component wrapped_wb_ddr_fifo
port (
clk: IN std_logic;
rst: IN std_logic;
din: IN std_logic_VECTOR(63 downto 0);
din: IN std_logic_VECTOR(64 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(63 downto 0);
dout: OUT std_logic_VECTOR(64 downto 0);
full: OUT std_logic;
empty: OUT std_logic;
valid: OUT std_logic);
......@@ -77,7 +77,7 @@ end component;
c_has_srst => 0,
c_enable_rst_sync => 1,
c_has_rd_data_count => 0,
c_din_width => 64,
c_din_width => 65,
c_has_wr_data_count => 0,
c_full_flags_rst_val => 0,
c_implementation_type => 0,
......@@ -90,9 +90,9 @@ end component;
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 1,
c_dout_width => 64,
c_dout_width => 65,
c_msgon_val => 1,
c_rd_depth => 1024,
c_rd_depth => 64,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_error_injection_type => 0,
......@@ -100,35 +100,35 @@ end component;
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 10,
c_data_count_width => 6,
c_has_wr_ack => 0,
c_use_ecc => 0,
c_wr_ack_low => 0,
c_common_clock => 1,
c_rd_pntr_width => 10,
c_rd_pntr_width => 6,
c_use_fwft_data_count => 0,
c_has_almost_empty => 0,
c_rd_data_count_width => 10,
c_rd_data_count_width => 6,
c_enable_rlocs => 0,
c_wr_pntr_width => 10,
c_wr_pntr_width => 6,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 10,
c_wr_data_count_width => 6,
c_preload_regs => 0,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 1021,
c_wr_depth => 1024,
c_prog_full_thresh_negate_val => 61,
c_wr_depth => 64,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_thresh_assert_val => 2,
c_has_valid => 1,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 1022,
c_prog_full_thresh_assert_val => 62,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "1kx36",
c_prim_fifo_type => "512x72",
c_count_type => 0,
c_prog_full_type => 0,
c_memory_type => 1);
......
hdl/spec/ip_cores/wb_ddr_fifo.vho
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......@@ -33,10 +33,10 @@ component wb_ddr_fifo
port (
clk: IN std_logic;
rst: IN std_logic;
din: IN std_logic_VECTOR(63 downto 0);
din: IN std_logic_VECTOR(64 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(63 downto 0);
dout: OUT std_logic_VECTOR(64 downto 0);
full: OUT std_logic;
empty: OUT std_logic;
valid: OUT std_logic);
......
hdl/spec/ip_cores/wb_ddr_fifo.xco
View file @ 89ee4559
##############################################################
#
# Xilinx Core Generator version 12.2
# Date: Mon Mar 28 13:17:52 2011
# Date: Wed Nov 23 13:13:49 2011
#
##############################################################
#
......@@ -39,7 +39,7 @@ CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET component_name=wb_ddr_fifo
CSET data_count=false
CSET data_count_width=10
CSET data_count_width=6
CSET disable_timing_violations=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=2
......@@ -49,14 +49,14 @@ CSET enable_int_clk=false
CSET enable_reset_synchronization=true
CSET fifo_implementation=Common_Clock_Block_RAM
CSET full_flags_reset_value=0
CSET full_threshold_assert_value=1022
CSET full_threshold_negate_value=1021
CSET full_threshold_assert_value=62
CSET full_threshold_negate_value=61
CSET inject_dbit_error=false
CSET inject_sbit_error=false
CSET input_data_width=64
CSET input_depth=1024
CSET output_data_width=64
CSET output_depth=1024
CSET input_data_width=65
CSET input_depth=64
CSET output_data_width=65
CSET output_depth=64
CSET overflow_flag=false
CSET overflow_sense=Active_High
CSET performance_options=Standard_FIFO
......@@ -64,7 +64,7 @@ CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_full_type=No_Programmable_Full_Threshold
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=10
CSET read_data_count_width=6
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET underflow_flag=false
......@@ -78,7 +78,7 @@ CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=10
CSET write_data_count_width=6
# END Parameters
GENERATE
# CRC: af2e406b
# CRC: f501a28c
hdl/spec/ip_cores/wb_ddr_fifo.xise
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......@@ -370,8 +370,8 @@
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-03-28T15:18:01" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="BD49D6EAE61FC1F5DAEE570D61DEB4AF" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-11-23T14:13:58" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="6B49F89A553F49600822491C249086A7" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
......
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