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FMC ADC 100M 14b 4cha - Gateware
Commit 8ce7c235 authored by mcattin's avatar mcattin
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Connect ADC value registers directly to serdes output. 

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@45 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
parent d5592fa4
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Showing with 204 additions and 31 deletions
hdl/spec/ise_project/iseconfig/spec_top.xreport
View file @ 8ce7c235
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2011-03-16T07:57:36</DateModified>
<DateModified>2011-03-16T12:13:39</DateModified>
<ModuleName>spec_top_fmc_adc_100Ms</ModuleName>
<SummaryTimeStamp>2011-03-09T11:19:20</SummaryTimeStamp>
<SavedFilePath>/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/ise_project/iseconfig/spec_top.xreport</SavedFilePath>
......
hdl/spec/ise_project/spec_fmc_adc_100Ms.gise
View file @ 8ce7c235
......@@ -137,7 +137,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1300213822" xil_pn:in_ck="-6698355625770614420" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8197382171204319838" xil_pn:start_ts="1300213598">
<transform xil_pn:end_ts="1300282061" xil_pn:in_ck="-6698355625770614420" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8197382171204319838" xil_pn:start_ts="1300281839">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -159,7 +159,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1300213850" xil_pn:in_ck="6806541686375937701" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7643830140109020653" xil_pn:start_ts="1300213822">
<transform xil_pn:end_ts="1300282088" xil_pn:in_ck="6806541686375937701" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7643830140109020653" xil_pn:start_ts="1300282061">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -169,7 +169,7 @@
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.ngd"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1300214231" xil_pn:in_ck="8313289856678850416" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-525288356180264082" xil_pn:start_ts="1300213850">
<transform xil_pn:end_ts="1300282454" xil_pn:in_ck="8313289856678850416" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-525288356180264082" xil_pn:start_ts="1300282088">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -183,7 +183,7 @@
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_summary.xml"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1300214481" xil_pn:in_ck="-1808195220703275450" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="5879947102106257248" xil_pn:start_ts="1300214231">
<transform xil_pn:end_ts="1300282722" xil_pn:in_ck="-1808195220703275450" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="5879947102106257248" xil_pn:start_ts="1300282454">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -198,7 +198,7 @@
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_pad.txt"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1300214546" xil_pn:in_ck="1401670161614903244" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="1554780821134721645" xil_pn:start_ts="1300214481">
<transform xil_pn:end_ts="1300282789" xil_pn:in_ck="1401670161614903244" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="1554780821134721645" xil_pn:start_ts="1300282722">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -211,7 +211,7 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1300214481" xil_pn:in_ck="8313289856678850284" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="4435602129065547965" xil_pn:start_ts="1300214439">
<transform xil_pn:end_ts="1300282722" xil_pn:in_ck="8313289856678850284" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="4435602129065547965" xil_pn:start_ts="1300282681">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/spec/rtl/fmc_adc_100Ms_core.vhd
View file @ 8ce7c235
......@@ -571,13 +571,13 @@ begin
fmc_adc_core_post_samples_o => post_trig_value,
fmc_adc_core_samp_cnt_i => X"00000000",
fmc_adc_core_ch1_ssr_o => gpio_ssr_ch1_o,
fmc_adc_core_ch1_val_i => sync_fifo_dout(15 downto 0),
fmc_adc_core_ch1_val_i => serdes_out_data(15 downto 0),
fmc_adc_core_ch2_ssr_o => gpio_ssr_ch2_o,
fmc_adc_core_ch2_val_i => sync_fifo_dout(31 downto 16),
fmc_adc_core_ch2_val_i => serdes_out_data(31 downto 16),
fmc_adc_core_ch3_ssr_o => gpio_ssr_ch3_o,
fmc_adc_core_ch3_val_i => sync_fifo_dout(47 downto 32),
fmc_adc_core_ch3_val_i => serdes_out_data(47 downto 32),
fmc_adc_core_ch4_ssr_o => gpio_ssr_ch4_o,
fmc_adc_core_ch4_val_i => sync_fifo_dout(63 downto 48)
fmc_adc_core_ch4_val_i => serdes_out_data(63 downto 48)
);
------------------------------------------------------------------------------
......
hdl/spec/rtl/fmc_adc_100Ms_csr.vhd
View file @ 8ce7c235
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/fmc_adc_100Ms_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Created : Wed Mar 16 11:36:21 2011
-- Created : Wed Mar 16 15:49:27 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -34,7 +34,7 @@ entity fmc_adc_100Ms_csr is
fmc_adc_core_ctl_fmc_clk_oe_o : out std_logic;
-- Port for BIT field: 'Offset DACs clear (active low)' in reg: 'Control register'
fmc_adc_core_ctl_offset_dac_clr_n_o : out std_logic;
-- Port for BIT field: 'Manual serdes bitslip' in reg: 'Control register'
-- Port for asynchronous (clock: fs_clk_i) MONOSTABLE field: 'Manual serdes bitslip' in reg: 'Control register'
fmc_adc_core_ctl_man_bitslip_o : out std_logic;
-- Port for std_logic_vector field: 'State machine status' in reg: 'Status register'
fmc_adc_core_sta_fsm_i : in std_logic_vector(2 downto 0);
......@@ -85,19 +85,19 @@ entity fmc_adc_100Ms_csr is
fmc_adc_core_samp_cnt_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Solid state relays control for channel 1' in reg: 'Solid state relays control for channel 1'
fmc_adc_core_ch1_ssr_o : out std_logic_vector(6 downto 0);
-- Port for std_logic_vector field: 'Channel 1 current value' in reg: 'Channel 1 current value'
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Channel 1 current value' in reg: 'Channel 1 current value'
fmc_adc_core_ch1_val_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Solid state relays control for channel 2' in reg: 'Solid state relays control for channel 2'
fmc_adc_core_ch2_ssr_o : out std_logic_vector(6 downto 0);
-- Port for std_logic_vector field: 'Channel 2 current value' in reg: 'Channel 2 current value'
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Channel 2 current value' in reg: 'Channel 2 current value'
fmc_adc_core_ch2_val_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Solid state relays control for channel 3' in reg: 'Solid state relays control for channel 3'
fmc_adc_core_ch3_ssr_o : out std_logic_vector(6 downto 0);
-- Port for std_logic_vector field: 'Channel 3 current value' in reg: 'Channel 3 current value'
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Channel 3 current value' in reg: 'Channel 3 current value'
fmc_adc_core_ch3_val_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Solid state relays control for channel 4' in reg: 'Solid state relays control for channel 4'
fmc_adc_core_ch4_ssr_o : out std_logic_vector(6 downto 0);
-- Port for std_logic_vector field: 'Channel 4 current value' in reg: 'Channel 4 current value'
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Channel 4 current value' in reg: 'Channel 4 current value'
fmc_adc_core_ch4_val_i : in std_logic_vector(15 downto 0)
);
end fmc_adc_100Ms_csr;
......@@ -107,6 +107,10 @@ architecture syn of fmc_adc_100Ms_csr is
signal fmc_adc_core_ctl_fmc_clk_oe_int : std_logic ;
signal fmc_adc_core_ctl_offset_dac_clr_n_int : std_logic ;
signal fmc_adc_core_ctl_man_bitslip_int : std_logic ;
signal fmc_adc_core_ctl_man_bitslip_int_delay : std_logic ;
signal fmc_adc_core_ctl_man_bitslip_sync0 : std_logic ;
signal fmc_adc_core_ctl_man_bitslip_sync1 : std_logic ;
signal fmc_adc_core_ctl_man_bitslip_sync2 : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_sel_int : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_sel_sync0 : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_sel_sync1 : std_logic ;
......@@ -148,9 +152,37 @@ signal fmc_adc_core_sr_deci_swb_s2 : std_logic ;
signal fmc_adc_core_pre_samples_int : std_logic_vector(31 downto 0);
signal fmc_adc_core_post_samples_int : std_logic_vector(31 downto 0);
signal fmc_adc_core_ch1_ssr_int : std_logic_vector(6 downto 0);
signal fmc_adc_core_ch1_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch1_val_lwb : std_logic ;
signal fmc_adc_core_ch1_val_lwb_delay : std_logic ;
signal fmc_adc_core_ch1_val_lwb_in_progress : std_logic ;
signal fmc_adc_core_ch1_val_lwb_s0 : std_logic ;
signal fmc_adc_core_ch1_val_lwb_s1 : std_logic ;
signal fmc_adc_core_ch1_val_lwb_s2 : std_logic ;
signal fmc_adc_core_ch2_ssr_int : std_logic_vector(6 downto 0);
signal fmc_adc_core_ch2_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch2_val_lwb : std_logic ;
signal fmc_adc_core_ch2_val_lwb_delay : std_logic ;
signal fmc_adc_core_ch2_val_lwb_in_progress : std_logic ;
signal fmc_adc_core_ch2_val_lwb_s0 : std_logic ;
signal fmc_adc_core_ch2_val_lwb_s1 : std_logic ;
signal fmc_adc_core_ch2_val_lwb_s2 : std_logic ;
signal fmc_adc_core_ch3_ssr_int : std_logic_vector(6 downto 0);
signal fmc_adc_core_ch3_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch3_val_lwb : std_logic ;
signal fmc_adc_core_ch3_val_lwb_delay : std_logic ;
signal fmc_adc_core_ch3_val_lwb_in_progress : std_logic ;
signal fmc_adc_core_ch3_val_lwb_s0 : std_logic ;
signal fmc_adc_core_ch3_val_lwb_s1 : std_logic ;
signal fmc_adc_core_ch3_val_lwb_s2 : std_logic ;
signal fmc_adc_core_ch4_ssr_int : std_logic_vector(6 downto 0);
signal fmc_adc_core_ch4_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_core_ch4_val_lwb : std_logic ;
signal fmc_adc_core_ch4_val_lwb_delay : std_logic ;
signal fmc_adc_core_ch4_val_lwb_in_progress : std_logic ;
signal fmc_adc_core_ch4_val_lwb_s0 : std_logic ;
signal fmc_adc_core_ch4_val_lwb_s1 : std_logic ;
signal fmc_adc_core_ch4_val_lwb_s2 : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
......@@ -184,6 +216,7 @@ begin
fmc_adc_core_ctl_fmc_clk_oe_int <= '0';
fmc_adc_core_ctl_offset_dac_clr_n_int <= '0';
fmc_adc_core_ctl_man_bitslip_int <= '0';
fmc_adc_core_ctl_man_bitslip_int_delay <= '0';
fmc_adc_core_trig_cfg_hw_trig_sel_int <= '0';
fmc_adc_core_trig_cfg_ext_trig_pol_int <= '0';
fmc_adc_core_trig_cfg_hw_trig_en_int <= '0';
......@@ -205,9 +238,21 @@ begin
fmc_adc_core_pre_samples_int <= "00000000000000000000000000000000";
fmc_adc_core_post_samples_int <= "00000000000000000000000000000000";
fmc_adc_core_ch1_ssr_int <= "0000000";
fmc_adc_core_ch1_val_lwb <= '0';
fmc_adc_core_ch1_val_lwb_delay <= '0';
fmc_adc_core_ch1_val_lwb_in_progress <= '0';
fmc_adc_core_ch2_ssr_int <= "0000000";
fmc_adc_core_ch2_val_lwb <= '0';
fmc_adc_core_ch2_val_lwb_delay <= '0';
fmc_adc_core_ch2_val_lwb_in_progress <= '0';
fmc_adc_core_ch3_ssr_int <= "0000000";
fmc_adc_core_ch3_val_lwb <= '0';
fmc_adc_core_ch3_val_lwb_delay <= '0';
fmc_adc_core_ch3_val_lwb_in_progress <= '0';
fmc_adc_core_ch4_ssr_int <= "0000000";
fmc_adc_core_ch4_val_lwb <= '0';
fmc_adc_core_ch4_val_lwb_delay <= '0';
fmc_adc_core_ch4_val_lwb_in_progress <= '0';
elsif rising_edge(bus_clock_int) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
......@@ -218,6 +263,8 @@ begin
ack_in_progress <= '0';
else
fmc_adc_core_ctl_fsm_cmd_wr_o <= '0';
fmc_adc_core_ctl_man_bitslip_int <= fmc_adc_core_ctl_man_bitslip_int_delay;
fmc_adc_core_ctl_man_bitslip_int_delay <= '0';
fmc_adc_core_trig_cfg_int_trig_sel_swb <= fmc_adc_core_trig_cfg_int_trig_sel_swb_delay;
fmc_adc_core_trig_cfg_int_trig_sel_swb_delay <= '0';
fmc_adc_core_trig_cfg_int_trig_thres_swb <= fmc_adc_core_trig_cfg_int_trig_thres_swb_delay;
......@@ -226,6 +273,30 @@ begin
fmc_adc_core_sw_trig_wr_int_delay <= '0';
fmc_adc_core_sr_deci_swb <= fmc_adc_core_sr_deci_swb_delay;
fmc_adc_core_sr_deci_swb_delay <= '0';
fmc_adc_core_ch1_val_lwb <= fmc_adc_core_ch1_val_lwb_delay;
fmc_adc_core_ch1_val_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (fmc_adc_core_ch1_val_lwb_in_progress = '1')) then
rddata_reg(15 downto 0) <= fmc_adc_core_ch1_val_int;
fmc_adc_core_ch1_val_lwb_in_progress <= '0';
end if;
fmc_adc_core_ch2_val_lwb <= fmc_adc_core_ch2_val_lwb_delay;
fmc_adc_core_ch2_val_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (fmc_adc_core_ch2_val_lwb_in_progress = '1')) then
rddata_reg(15 downto 0) <= fmc_adc_core_ch2_val_int;
fmc_adc_core_ch2_val_lwb_in_progress <= '0';
end if;
fmc_adc_core_ch3_val_lwb <= fmc_adc_core_ch3_val_lwb_delay;
fmc_adc_core_ch3_val_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (fmc_adc_core_ch3_val_lwb_in_progress = '1')) then
rddata_reg(15 downto 0) <= fmc_adc_core_ch3_val_int;
fmc_adc_core_ch3_val_lwb_in_progress <= '0';
end if;
fmc_adc_core_ch4_val_lwb <= fmc_adc_core_ch4_val_lwb_delay;
fmc_adc_core_ch4_val_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (fmc_adc_core_ch4_val_lwb_in_progress = '1')) then
rddata_reg(15 downto 0) <= fmc_adc_core_ch4_val_int;
fmc_adc_core_ch4_val_lwb_in_progress <= '0';
end if;
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
......@@ -236,10 +307,10 @@ begin
fmc_adc_core_ctl_fmc_clk_oe_int <= wrdata_reg(2);
fmc_adc_core_ctl_offset_dac_clr_n_int <= wrdata_reg(3);
fmc_adc_core_ctl_man_bitslip_int <= wrdata_reg(4);
fmc_adc_core_ctl_man_bitslip_int_delay <= wrdata_reg(4);
else
rddata_reg(2) <= fmc_adc_core_ctl_fmc_clk_oe_int;
rddata_reg(3) <= fmc_adc_core_ctl_offset_dac_clr_n_int;
rddata_reg(4) <= fmc_adc_core_ctl_man_bitslip_int;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(5) <= 'X';
......@@ -270,7 +341,7 @@ begin
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_sreg(4) <= '1';
ack_in_progress <= '1';
when "00001" =>
if (wb_we_i = '1') then
......@@ -531,7 +602,9 @@ begin
when "10001" =>
if (wb_we_i = '1') then
else
rddata_reg(15 downto 0) <= fmc_adc_core_ch1_val_i;
fmc_adc_core_ch1_val_lwb <= '1';
fmc_adc_core_ch1_val_lwb_delay <= '1';
fmc_adc_core_ch1_val_lwb_in_progress <= '1';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
......@@ -549,7 +622,7 @@ begin
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "10010" =>
if (wb_we_i = '1') then
......@@ -587,7 +660,9 @@ begin
when "10011" =>
if (wb_we_i = '1') then
else
rddata_reg(15 downto 0) <= fmc_adc_core_ch2_val_i;
fmc_adc_core_ch2_val_lwb <= '1';
fmc_adc_core_ch2_val_lwb_delay <= '1';
fmc_adc_core_ch2_val_lwb_in_progress <= '1';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
......@@ -605,7 +680,7 @@ begin
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "10100" =>
if (wb_we_i = '1') then
......@@ -643,7 +718,9 @@ begin
when "10101" =>
if (wb_we_i = '1') then
else
rddata_reg(15 downto 0) <= fmc_adc_core_ch3_val_i;
fmc_adc_core_ch3_val_lwb <= '1';
fmc_adc_core_ch3_val_lwb_delay <= '1';
fmc_adc_core_ch3_val_lwb_in_progress <= '1';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
......@@ -661,7 +738,7 @@ begin
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "10110" =>
if (wb_we_i = '1') then
......@@ -699,7 +776,9 @@ begin
when "10111" =>
if (wb_we_i = '1') then
else
rddata_reg(15 downto 0) <= fmc_adc_core_ch4_val_i;
fmc_adc_core_ch4_val_lwb <= '1';
fmc_adc_core_ch4_val_lwb_delay <= '1';
fmc_adc_core_ch4_val_lwb_in_progress <= '1';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
......@@ -717,7 +796,7 @@ begin
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
......@@ -740,7 +819,22 @@ begin
-- Offset DACs clear (active low)
fmc_adc_core_ctl_offset_dac_clr_n_o <= fmc_adc_core_ctl_offset_dac_clr_n_int;
-- Manual serdes bitslip
fmc_adc_core_ctl_man_bitslip_o <= fmc_adc_core_ctl_man_bitslip_int;
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_core_ctl_man_bitslip_o <= '0';
fmc_adc_core_ctl_man_bitslip_sync0 <= '0';
fmc_adc_core_ctl_man_bitslip_sync1 <= '0';
fmc_adc_core_ctl_man_bitslip_sync2 <= '0';
elsif rising_edge(fs_clk_i) then
fmc_adc_core_ctl_man_bitslip_sync0 <= fmc_adc_core_ctl_man_bitslip_int;
fmc_adc_core_ctl_man_bitslip_sync1 <= fmc_adc_core_ctl_man_bitslip_sync0;
fmc_adc_core_ctl_man_bitslip_sync2 <= fmc_adc_core_ctl_man_bitslip_sync1;
fmc_adc_core_ctl_man_bitslip_o <= fmc_adc_core_ctl_man_bitslip_sync2 and (not fmc_adc_core_ctl_man_bitslip_sync1);
end if;
end process;
-- State machine status
-- SerDes PLL status
-- SerDes synchronization status
......@@ -906,15 +1000,91 @@ begin
-- Solid state relays control for channel 1
fmc_adc_core_ch1_ssr_o <= fmc_adc_core_ch1_ssr_int;
-- Channel 1 current value
-- asynchronous std_logic_vector register : Channel 1 current value (type RO/WO, fs_clk_i <-> bus_clock_int)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_core_ch1_val_lwb_s0 <= '0';
fmc_adc_core_ch1_val_lwb_s1 <= '0';
fmc_adc_core_ch1_val_lwb_s2 <= '0';
fmc_adc_core_ch1_val_int <= "0000000000000000";
elsif rising_edge(fs_clk_i) then
fmc_adc_core_ch1_val_lwb_s0 <= fmc_adc_core_ch1_val_lwb;
fmc_adc_core_ch1_val_lwb_s1 <= fmc_adc_core_ch1_val_lwb_s0;
fmc_adc_core_ch1_val_lwb_s2 <= fmc_adc_core_ch1_val_lwb_s1;
if ((fmc_adc_core_ch1_val_lwb_s1 = '1') and (fmc_adc_core_ch1_val_lwb_s2 = '0')) then
fmc_adc_core_ch1_val_int <= fmc_adc_core_ch1_val_i;
end if;
end if;
end process;
-- Solid state relays control for channel 2
fmc_adc_core_ch2_ssr_o <= fmc_adc_core_ch2_ssr_int;
-- Channel 2 current value
-- asynchronous std_logic_vector register : Channel 2 current value (type RO/WO, fs_clk_i <-> bus_clock_int)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_core_ch2_val_lwb_s0 <= '0';
fmc_adc_core_ch2_val_lwb_s1 <= '0';
fmc_adc_core_ch2_val_lwb_s2 <= '0';
fmc_adc_core_ch2_val_int <= "0000000000000000";
elsif rising_edge(fs_clk_i) then
fmc_adc_core_ch2_val_lwb_s0 <= fmc_adc_core_ch2_val_lwb;
fmc_adc_core_ch2_val_lwb_s1 <= fmc_adc_core_ch2_val_lwb_s0;
fmc_adc_core_ch2_val_lwb_s2 <= fmc_adc_core_ch2_val_lwb_s1;
if ((fmc_adc_core_ch2_val_lwb_s1 = '1') and (fmc_adc_core_ch2_val_lwb_s2 = '0')) then
fmc_adc_core_ch2_val_int <= fmc_adc_core_ch2_val_i;
end if;
end if;
end process;
-- Solid state relays control for channel 3
fmc_adc_core_ch3_ssr_o <= fmc_adc_core_ch3_ssr_int;
-- Channel 3 current value
-- asynchronous std_logic_vector register : Channel 3 current value (type RO/WO, fs_clk_i <-> bus_clock_int)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_core_ch3_val_lwb_s0 <= '0';
fmc_adc_core_ch3_val_lwb_s1 <= '0';
fmc_adc_core_ch3_val_lwb_s2 <= '0';
fmc_adc_core_ch3_val_int <= "0000000000000000";
elsif rising_edge(fs_clk_i) then
fmc_adc_core_ch3_val_lwb_s0 <= fmc_adc_core_ch3_val_lwb;
fmc_adc_core_ch3_val_lwb_s1 <= fmc_adc_core_ch3_val_lwb_s0;
fmc_adc_core_ch3_val_lwb_s2 <= fmc_adc_core_ch3_val_lwb_s1;
if ((fmc_adc_core_ch3_val_lwb_s1 = '1') and (fmc_adc_core_ch3_val_lwb_s2 = '0')) then
fmc_adc_core_ch3_val_int <= fmc_adc_core_ch3_val_i;
end if;
end if;
end process;
-- Solid state relays control for channel 4
fmc_adc_core_ch4_ssr_o <= fmc_adc_core_ch4_ssr_int;
-- Channel 4 current value
-- asynchronous std_logic_vector register : Channel 4 current value (type RO/WO, fs_clk_i <-> bus_clock_int)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_core_ch4_val_lwb_s0 <= '0';
fmc_adc_core_ch4_val_lwb_s1 <= '0';
fmc_adc_core_ch4_val_lwb_s2 <= '0';
fmc_adc_core_ch4_val_int <= "0000000000000000";
elsif rising_edge(fs_clk_i) then
fmc_adc_core_ch4_val_lwb_s0 <= fmc_adc_core_ch4_val_lwb;
fmc_adc_core_ch4_val_lwb_s1 <= fmc_adc_core_ch4_val_lwb_s0;
fmc_adc_core_ch4_val_lwb_s2 <= fmc_adc_core_ch4_val_lwb_s1;
if ((fmc_adc_core_ch4_val_lwb_s1 = '1') and (fmc_adc_core_ch4_val_lwb_s2 = '0')) then
fmc_adc_core_ch4_val_int <= fmc_adc_core_ch4_val_i;
end if;
end if;
end process;
rwaddr_reg <= wb_addr_i;
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
......
hdl/spec/wb_gen/fmc_adc_100Ms_csr.wb
View file @ 8ce7c235
......@@ -38,9 +38,8 @@ peripheral {
field {
name = "Manual serdes bitslip";
prefix = "man_bitslip";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = MONOSTABLE;
clock = "fs_clk_i"
};
};
......@@ -361,6 +360,7 @@ peripheral {
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "fs_clk_i";
};
};
......@@ -389,6 +389,7 @@ peripheral {
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "fs_clk_i";
};
};
......@@ -417,6 +418,7 @@ peripheral {
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "fs_clk_i";
};
};
......@@ -445,6 +447,7 @@ peripheral {
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "fs_clk_i";
};
};
......
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