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FMC ADC 100M 14b 4cha - Gateware
Commit 8f87d9ba authored by Matthieu Cattin's avatar Matthieu Cattin
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hdl: Remove "reserved" fields from svec/spec carrier csr cores.

parent 23fbb478
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documentation/manuals/gateware/spec/carrier_csr.tex
View file @ 8f87d9ba
...@@ -66,11 +66,6 @@ System clock PLL status ...@@ -66,11 +66,6 @@ System clock PLL status
@code{DDR3_CAL_DONE} @code{DDR3_CAL_DONE}
@tab @code{X} @tab @tab @code{X} @tab
DDR3 calibration status DDR3 calibration status
@item @code{31...4}
@tab R/O @tab
@code{RESERVED}
@tab @code{X} @tab
Reserved
@end multitable @end multitable
@multitable @columnfractions 0.15 0.85 @multitable @columnfractions 0.15 0.85
@headitem Field @tab Description @headitem Field @tab Description
...@@ -78,7 +73,6 @@ Reserved ...@@ -78,7 +73,6 @@ Reserved
@item @code{p2l_pll_lck} @tab 0: not locked@*1: locked. @item @code{p2l_pll_lck} @tab 0: not locked@*1: locked.
@item @code{sys_pll_lck} @tab 0: not locked@*1: locked. @item @code{sys_pll_lck} @tab 0: not locked@*1: locked.
@item @code{ddr3_cal_done} @tab 0: not done@*1: done. @item @code{ddr3_cal_done} @tab 0: not done@*1: done.
@item @code{reserved} @tab Ignore on read, write with 0's.
@end multitable @end multitable
@regsection @code{ctrl} - Control @regsection @code{ctrl} - Control
@multitable @columnfractions .10 .10 .15 .10 .55 @multitable @columnfractions .10 .10 .15 .10 .55
...@@ -98,18 +92,12 @@ Red LED ...@@ -98,18 +92,12 @@ Red LED
@code{DAC_CLR_N} @code{DAC_CLR_N}
@tab @code{0} @tab @tab @code{0} @tab
DAC clear DAC clear
@item @code{31...3}
@tab R/W @tab
@code{RESERVED}
@tab @code{0} @tab
Reserved
@end multitable @end multitable
@multitable @columnfractions 0.15 0.85 @multitable @columnfractions 0.15 0.85
@headitem Field @tab Description @headitem Field @tab Description
@item @code{led_green} @tab Manual control of the front panel green LED (unused in the fmc-adc application) @item @code{led_green} @tab Manual control of the front panel green LED (unused in the fmc-adc application)
@item @code{led_red} @tab Manual control of the front panel red LED (unused in the fmc-adc application) @item @code{led_red} @tab Manual control of the front panel red LED (unused in the fmc-adc application)
@item @code{dac_clr_n} @tab Active low clear signal for VCXO DACs @item @code{dac_clr_n} @tab Active low clear signal for VCXO DACs
@item @code{reserved} @tab Ignore on read, write with 0's
@end multitable @end multitable
@regsection @code{rst} - Reset Register @regsection @code{rst} - Reset Register
Controls software reset of the mezzanine including the ddr interface and the time-tagging core. Controls software reset of the mezzanine including the ddr interface and the time-tagging core.
...@@ -120,14 +108,8 @@ Controls software reset of the mezzanine including the ddr interface and the tim ...@@ -120,14 +108,8 @@ Controls software reset of the mezzanine including the ddr interface and the tim
@code{FMC0_N} @code{FMC0_N}
@tab @code{X} @tab @tab @code{X} @tab
State of the reset line State of the reset line
@item @code{31...1}
@tab R/W @tab
@code{RESERVED}
@tab @code{0} @tab
Reserved
@end multitable @end multitable
@multitable @columnfractions 0.15 0.85 @multitable @columnfractions 0.15 0.85
@headitem Field @tab Description @headitem Field @tab Description
@item @code{fmc0_n} @tab write 0: FMC is held in reset@* write 1: Normal FMC operation (default) @item @code{fmc0_n} @tab write 0: FMC is held in reset@* write 1: Normal FMC operation (default)
@item @code{reserved} @tab Ignore on read, write with 0's
@end multitable @end multitable
documentation/manuals/gateware/svec/carrier_csr.tex
View file @ 8f87d9ba
...@@ -71,11 +71,6 @@ DDR3 bank 4 calibration status ...@@ -71,11 +71,6 @@ DDR3 bank 4 calibration status
@code{DDR1_CAL_DONE} @code{DDR1_CAL_DONE}
@tab @code{X} @tab @tab @code{X} @tab
DDR3 bank 5 calibration status DDR3 bank 5 calibration status
@item @code{31...5}
@tab R/O @tab
@code{RESERVED}
@tab @code{X} @tab
Reserved
@end multitable @end multitable
@multitable @columnfractions 0.15 0.85 @multitable @columnfractions 0.15 0.85
@headitem Field @tab Description @headitem Field @tab Description
...@@ -84,7 +79,6 @@ Reserved ...@@ -84,7 +79,6 @@ Reserved
@item @code{sys_pll_lck} @tab 0: not locked@*1: locked. @item @code{sys_pll_lck} @tab 0: not locked@*1: locked.
@item @code{ddr0_cal_done} @tab 0: not done@*1: done. @item @code{ddr0_cal_done} @tab 0: not done@*1: done.
@item @code{ddr1_cal_done} @tab 0: not done@*1: done. @item @code{ddr1_cal_done} @tab 0: not done@*1: done.
@item @code{reserved} @tab Ignore on read, write with 0's.
@end multitable @end multitable
@regsection @code{ctrl} - Control @regsection @code{ctrl} - Control
@multitable @columnfractions .10 .10 .15 .10 .55 @multitable @columnfractions .10 .10 .15 .10 .55
...@@ -94,16 +88,10 @@ Reserved ...@@ -94,16 +88,10 @@ Reserved
@code{FP_LEDS_MAN} @code{FP_LEDS_MAN}
@tab @code{0} @tab @tab @code{0} @tab
Front panel LED manual control Front panel LED manual control
@item @code{31...16}
@tab R/W @tab
@code{RESERVED}
@tab @code{0} @tab
Reserved
@end multitable @end multitable
@multitable @columnfractions 0.15 0.85 @multitable @columnfractions 0.15 0.85
@headitem Field @tab Description @headitem Field @tab Description
@item @code{fp_leds_man} @tab Height front panel LED, two bits per LED.@*00 = OFF@*01 = Green@*10 = Red@*11 = Orange @item @code{fp_leds_man} @tab Height front panel LED, two bits per LED.@*00 = OFF@*01 = Green@*10 = Red@*11 = Orange
@item @code{reserved} @tab Ignore on read, write with 0's
@end multitable @end multitable
@regsection @code{rst} - Reset Register @regsection @code{rst} - Reset Register
Controls software reset of the mezzanines including the ddr interface and the time-tagging core. Controls software reset of the mezzanines including the ddr interface and the time-tagging core.
...@@ -119,15 +107,9 @@ State of the FMC 1 reset line ...@@ -119,15 +107,9 @@ State of the FMC 1 reset line
@code{FMC1_N} @code{FMC1_N}
@tab @code{X} @tab @tab @code{X} @tab
State of the FMC 2 reset line State of the FMC 2 reset line
@item @code{31...2}
@tab R/W @tab
@code{RESERVED}
@tab @code{0} @tab
Reserved
@end multitable @end multitable
@multitable @columnfractions 0.15 0.85 @multitable @columnfractions 0.15 0.85
@headitem Field @tab Description @headitem Field @tab Description
@item @code{fmc0_n} @tab write 0: FMC is held in reset@* write 1: Normal FMC operation (default) @item @code{fmc0_n} @tab write 0: FMC is held in reset@* write 1: Normal FMC operation (default)
@item @code{fmc1_n} @tab write 0: FMC is held in reset@* write 1: Normal FMC operation (default) @item @code{fmc1_n} @tab write 0: FMC is held in reset@* write 1: Normal FMC operation (default)
@item @code{reserved} @tab Ignore on read, write with 0's
@end multitable @end multitable
hdl/spec/rtl/carrier_csr.vhd
View file @ 8f87d9ba
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr.vhd -- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb -- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Tue Jan 14 11:45:49 2014 -- Created : Wed Apr 23 10:05:23 2014
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
...@@ -41,22 +41,16 @@ entity carrier_csr is ...@@ -41,22 +41,16 @@ entity carrier_csr is
carrier_csr_stat_sys_pll_lck_i : in std_logic; carrier_csr_stat_sys_pll_lck_i : in std_logic;
-- Port for BIT field: 'DDR3 calibration status' in reg: 'Status' -- Port for BIT field: 'DDR3 calibration status' in reg: 'Status'
carrier_csr_stat_ddr3_cal_done_i : in std_logic; carrier_csr_stat_ddr3_cal_done_i : in std_logic;
-- Port for std_logic_vector field: 'Reserved' in reg: 'Status'
carrier_csr_stat_reserved_i : in std_logic_vector(27 downto 0);
-- Port for BIT field: 'Green LED' in reg: 'Control' -- Port for BIT field: 'Green LED' in reg: 'Control'
carrier_csr_ctrl_led_green_o : out std_logic; carrier_csr_ctrl_led_green_o : out std_logic;
-- Port for BIT field: 'Red LED' in reg: 'Control' -- Port for BIT field: 'Red LED' in reg: 'Control'
carrier_csr_ctrl_led_red_o : out std_logic; carrier_csr_ctrl_led_red_o : out std_logic;
-- Port for BIT field: 'DAC clear' in reg: 'Control' -- Port for BIT field: 'DAC clear' in reg: 'Control'
carrier_csr_ctrl_dac_clr_n_o : out std_logic; carrier_csr_ctrl_dac_clr_n_o : out std_logic;
-- Port for std_logic_vector field: 'Reserved' in reg: 'Control'
carrier_csr_ctrl_reserved_o : out std_logic_vector(28 downto 0);
-- Ports for BIT field: 'State of the reset line' in reg: 'Reset Register' -- Ports for BIT field: 'State of the reset line' in reg: 'Reset Register'
carrier_csr_rst_fmc0_n_o : out std_logic; carrier_csr_rst_fmc0_n_o : out std_logic;
carrier_csr_rst_fmc0_n_i : in std_logic; carrier_csr_rst_fmc0_n_i : in std_logic;
carrier_csr_rst_fmc0_n_load_o : out std_logic; carrier_csr_rst_fmc0_n_load_o : out std_logic
-- Port for std_logic_vector field: 'Reserved' in reg: 'Reset Register'
carrier_csr_rst_reserved_o : out std_logic_vector(30 downto 0)
); );
end carrier_csr; end carrier_csr;
...@@ -65,8 +59,6 @@ architecture syn of carrier_csr is ...@@ -65,8 +59,6 @@ architecture syn of carrier_csr is
signal carrier_csr_ctrl_led_green_int : std_logic ; signal carrier_csr_ctrl_led_green_int : std_logic ;
signal carrier_csr_ctrl_led_red_int : std_logic ; signal carrier_csr_ctrl_led_red_int : std_logic ;
signal carrier_csr_ctrl_dac_clr_n_int : std_logic ; signal carrier_csr_ctrl_dac_clr_n_int : std_logic ;
signal carrier_csr_ctrl_reserved_int : std_logic_vector(28 downto 0);
signal carrier_csr_rst_reserved_int : std_logic_vector(30 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0); signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0); signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0); signal wrdata_reg : std_logic_vector(31 downto 0);
...@@ -97,9 +89,7 @@ begin ...@@ -97,9 +89,7 @@ begin
carrier_csr_ctrl_led_green_int <= '0'; carrier_csr_ctrl_led_green_int <= '0';
carrier_csr_ctrl_led_red_int <= '0'; carrier_csr_ctrl_led_red_int <= '0';
carrier_csr_ctrl_dac_clr_n_int <= '0'; carrier_csr_ctrl_dac_clr_n_int <= '0';
carrier_csr_ctrl_reserved_int <= "00000000000000000000000000000";
carrier_csr_rst_fmc0_n_load_o <= '0'; carrier_csr_rst_fmc0_n_load_o <= '0';
carrier_csr_rst_reserved_int <= "0000000000000000000000000000000";
elsif rising_edge(clk_sys_i) then elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register -- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1); ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
...@@ -129,7 +119,34 @@ begin ...@@ -129,7 +119,34 @@ begin
rddata_reg(1) <= carrier_csr_stat_p2l_pll_lck_i; rddata_reg(1) <= carrier_csr_stat_p2l_pll_lck_i;
rddata_reg(2) <= carrier_csr_stat_sys_pll_lck_i; rddata_reg(2) <= carrier_csr_stat_sys_pll_lck_i;
rddata_reg(3) <= carrier_csr_stat_ddr3_cal_done_i; rddata_reg(3) <= carrier_csr_stat_ddr3_cal_done_i;
rddata_reg(31 downto 4) <= carrier_csr_stat_reserved_i; rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "10" => when "10" =>
...@@ -137,21 +154,77 @@ begin ...@@ -137,21 +154,77 @@ begin
carrier_csr_ctrl_led_green_int <= wrdata_reg(0); carrier_csr_ctrl_led_green_int <= wrdata_reg(0);
carrier_csr_ctrl_led_red_int <= wrdata_reg(1); carrier_csr_ctrl_led_red_int <= wrdata_reg(1);
carrier_csr_ctrl_dac_clr_n_int <= wrdata_reg(2); carrier_csr_ctrl_dac_clr_n_int <= wrdata_reg(2);
carrier_csr_ctrl_reserved_int <= wrdata_reg(31 downto 3);
end if; end if;
rddata_reg(0) <= carrier_csr_ctrl_led_green_int; rddata_reg(0) <= carrier_csr_ctrl_led_green_int;
rddata_reg(1) <= carrier_csr_ctrl_led_red_int; rddata_reg(1) <= carrier_csr_ctrl_led_red_int;
rddata_reg(2) <= carrier_csr_ctrl_dac_clr_n_int; rddata_reg(2) <= carrier_csr_ctrl_dac_clr_n_int;
rddata_reg(31 downto 3) <= carrier_csr_ctrl_reserved_int; rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "11" => when "11" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
carrier_csr_rst_fmc0_n_load_o <= '1'; carrier_csr_rst_fmc0_n_load_o <= '1';
carrier_csr_rst_reserved_int <= wrdata_reg(31 downto 1);
end if; end if;
rddata_reg(0) <= carrier_csr_rst_fmc0_n_i; rddata_reg(0) <= carrier_csr_rst_fmc0_n_i;
rddata_reg(31 downto 1) <= carrier_csr_rst_reserved_int; rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when others => when others =>
...@@ -174,19 +247,14 @@ begin ...@@ -174,19 +247,14 @@ begin
-- GN4142 core P2L PLL status -- GN4142 core P2L PLL status
-- System clock PLL status -- System clock PLL status
-- DDR3 calibration status -- DDR3 calibration status
-- Reserved
-- Green LED -- Green LED
carrier_csr_ctrl_led_green_o <= carrier_csr_ctrl_led_green_int; carrier_csr_ctrl_led_green_o <= carrier_csr_ctrl_led_green_int;
-- Red LED -- Red LED
carrier_csr_ctrl_led_red_o <= carrier_csr_ctrl_led_red_int; carrier_csr_ctrl_led_red_o <= carrier_csr_ctrl_led_red_int;
-- DAC clear -- DAC clear
carrier_csr_ctrl_dac_clr_n_o <= carrier_csr_ctrl_dac_clr_n_int; carrier_csr_ctrl_dac_clr_n_o <= carrier_csr_ctrl_dac_clr_n_int;
-- Reserved
carrier_csr_ctrl_reserved_o <= carrier_csr_ctrl_reserved_int;
-- State of the reset line -- State of the reset line
carrier_csr_rst_fmc0_n_o <= wrdata_reg(0); carrier_csr_rst_fmc0_n_o <= wrdata_reg(0);
-- Reserved
carrier_csr_rst_reserved_o <= carrier_csr_rst_reserved_int;
rwaddr_reg <= wb_adr_i; rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i); wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter. -- ACK signal generation. Just pass the LSB of ACK counter.
......
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
View file @ 8f87d9ba
...@@ -197,15 +197,12 @@ architecture rtl of spec_top_fmc_adc_100Ms is ...@@ -197,15 +197,12 @@ architecture rtl of spec_top_fmc_adc_100Ms is
carrier_csr_stat_p2l_pll_lck_i : in std_logic; carrier_csr_stat_p2l_pll_lck_i : in std_logic;
carrier_csr_stat_sys_pll_lck_i : in std_logic; carrier_csr_stat_sys_pll_lck_i : in std_logic;
carrier_csr_stat_ddr3_cal_done_i : in std_logic; carrier_csr_stat_ddr3_cal_done_i : in std_logic;
carrier_csr_stat_reserved_i : in std_logic_vector(27 downto 0);
carrier_csr_ctrl_led_green_o : out std_logic; carrier_csr_ctrl_led_green_o : out std_logic;
carrier_csr_ctrl_led_red_o : out std_logic; carrier_csr_ctrl_led_red_o : out std_logic;
carrier_csr_ctrl_dac_clr_n_o : out std_logic; carrier_csr_ctrl_dac_clr_n_o : out std_logic;
carrier_csr_ctrl_reserved_o : out std_logic_vector(28 downto 0);
carrier_csr_rst_fmc0_n_o : out std_logic; carrier_csr_rst_fmc0_n_o : out std_logic;
carrier_csr_rst_fmc0_n_i : in std_logic; carrier_csr_rst_fmc0_n_i : in std_logic;
carrier_csr_rst_fmc0_n_load_o : out std_logic; carrier_csr_rst_fmc0_n_load_o : out std_logic
carrier_csr_rst_reserved_o : out std_logic_vector(30 downto 0)
); );
end component carrier_csr; end component carrier_csr;
...@@ -729,15 +726,12 @@ begin ...@@ -729,15 +726,12 @@ begin
carrier_csr_stat_p2l_pll_lck_i => p2l_pll_locked, carrier_csr_stat_p2l_pll_lck_i => p2l_pll_locked,
carrier_csr_stat_sys_pll_lck_i => sys_clk_pll_locked, carrier_csr_stat_sys_pll_lck_i => sys_clk_pll_locked,
carrier_csr_stat_ddr3_cal_done_i => ddr3_calib_done, carrier_csr_stat_ddr3_cal_done_i => ddr3_calib_done,
carrier_csr_stat_reserved_i => (others => '0'),
carrier_csr_ctrl_led_green_o => led_green, carrier_csr_ctrl_led_green_o => led_green,
carrier_csr_ctrl_led_red_o => led_red, carrier_csr_ctrl_led_red_o => led_red,
carrier_csr_ctrl_dac_clr_n_o => open, carrier_csr_ctrl_dac_clr_n_o => open,
carrier_csr_ctrl_reserved_o => open,
carrier_csr_rst_fmc0_n_o => sw_rst_fmc0_n_o, carrier_csr_rst_fmc0_n_o => sw_rst_fmc0_n_o,
carrier_csr_rst_fmc0_n_i => sw_rst_fmc0_n_i, carrier_csr_rst_fmc0_n_i => sw_rst_fmc0_n_i,
carrier_csr_rst_fmc0_n_load_o => sw_rst_fmc0_n_load, carrier_csr_rst_fmc0_n_load_o => sw_rst_fmc0_n_load
carrier_csr_rst_reserved_o => open
); );
-- Unused wishbone signals -- Unused wishbone signals
......
hdl/spec/wb_gen/carrier_csr.h
View file @ 8f87d9ba
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
* File : carrier_csr.h * File : carrier_csr.h
* Author : auto-generated by wbgen2 from carrier_csr.wb * Author : auto-generated by wbgen2 from carrier_csr.wb
* Created : Tue Jan 14 11:45:49 2014 * Created : Wed Apr 23 10:05:23 2014
* Standard : ANSI C * Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
...@@ -65,12 +65,6 @@ ...@@ -65,12 +65,6 @@
/* definitions for field: DDR3 calibration status in reg: Status */ /* definitions for field: DDR3 calibration status in reg: Status */
#define CARRIER_CSR_STAT_DDR3_CAL_DONE WBGEN2_GEN_MASK(3, 1) #define CARRIER_CSR_STAT_DDR3_CAL_DONE WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Reserved in reg: Status */
#define CARRIER_CSR_STAT_RESERVED_MASK WBGEN2_GEN_MASK(4, 28)
#define CARRIER_CSR_STAT_RESERVED_SHIFT 4
#define CARRIER_CSR_STAT_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 4, 28)
#define CARRIER_CSR_STAT_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 4, 28)
/* definitions for register: Control */ /* definitions for register: Control */
/* definitions for field: Green LED in reg: Control */ /* definitions for field: Green LED in reg: Control */
...@@ -82,23 +76,11 @@ ...@@ -82,23 +76,11 @@
/* definitions for field: DAC clear in reg: Control */ /* definitions for field: DAC clear in reg: Control */
#define CARRIER_CSR_CTRL_DAC_CLR_N WBGEN2_GEN_MASK(2, 1) #define CARRIER_CSR_CTRL_DAC_CLR_N WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Reserved in reg: Control */
#define CARRIER_CSR_CTRL_RESERVED_MASK WBGEN2_GEN_MASK(3, 29)
#define CARRIER_CSR_CTRL_RESERVED_SHIFT 3
#define CARRIER_CSR_CTRL_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 3, 29)
#define CARRIER_CSR_CTRL_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 3, 29)
/* definitions for register: Reset Register */ /* definitions for register: Reset Register */
/* definitions for field: State of the reset line in reg: Reset Register */ /* definitions for field: State of the reset line in reg: Reset Register */
#define CARRIER_CSR_RST_FMC0_N WBGEN2_GEN_MASK(0, 1) #define CARRIER_CSR_RST_FMC0_N WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Reserved in reg: Reset Register */
#define CARRIER_CSR_RST_RESERVED_MASK WBGEN2_GEN_MASK(1, 31)
#define CARRIER_CSR_RST_RESERVED_SHIFT 1
#define CARRIER_CSR_RST_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 1, 31)
#define CARRIER_CSR_RST_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 1, 31)
PACKED struct CARRIER_CSR_WB { PACKED struct CARRIER_CSR_WB {
/* [0x0]: REG Carrier type and PCB version */ /* [0x0]: REG Carrier type and PCB version */
uint32_t CARRIER; uint32_t CARRIER;
......
hdl/spec/wb_gen/carrier_csr.htm
View file @ 8f87d9ba
...@@ -305,23 +305,6 @@ carrier_csr_stat_ddr3_cal_done_i ...@@ -305,23 +305,6 @@ carrier_csr_stat_ddr3_cal_done_i
</td> </td>
<td class="td_pblock_left"> <td class="td_pblock_left">
wb_stall_o wb_stall_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_stat_reserved_i[27:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td> </td>
<td class="td_sym_center"> <td class="td_sym_center">
&nbsp; &nbsp;
...@@ -407,23 +390,6 @@ carrier_csr_ctrl_dac_clr_n_o ...@@ -407,23 +390,6 @@ carrier_csr_ctrl_dac_clr_n_o
</td> </td>
<td class="td_pblock_left"> <td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_ctrl_reserved_o[28:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td> </td>
<td class="td_sym_center"> <td class="td_sym_center">
&nbsp; &nbsp;
...@@ -503,23 +469,6 @@ carrier_csr_rst_fmc0_n_load_o ...@@ -503,23 +469,6 @@ carrier_csr_rst_fmc0_n_load_o
&rarr; &rarr;
</td> </td>
</tr> </tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_rst_reserved_o[30:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
</table> </table>
<h3><a name="sect_3_0">3. Register description</a></h3> <h3><a name="sect_3_0">3. Register description</a></h3>
...@@ -853,29 +802,29 @@ STAT ...@@ -853,29 +802,29 @@ STAT
</td> </td>
</tr> </tr>
<tr> <tr>
<td style="border: solid 1px black;" colspan=8 class="td_field"> <td class="td_unused">
RESERVED[27:20] -
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
</tr> </tr>
</table> </table>
...@@ -907,29 +856,29 @@ RESERVED[27:20] ...@@ -907,29 +856,29 @@ RESERVED[27:20]
</td> </td>
</tr> </tr>
<tr> <tr>
<td style="border: solid 1px black;" colspan=8 class="td_field"> <td class="td_unused">
RESERVED[19:12] -
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
</tr> </tr>
</table> </table>
...@@ -961,29 +910,29 @@ RESERVED[19:12] ...@@ -961,29 +910,29 @@ RESERVED[19:12]
</td> </td>
</tr> </tr>
<tr> <tr>
<td style="border: solid 1px black;" colspan=8 class="td_field"> <td class="td_unused">
RESERVED[11:4] -
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
</tr> </tr>
</table> </table>
...@@ -1015,8 +964,17 @@ RESERVED[11:4] ...@@ -1015,8 +964,17 @@ RESERVED[11:4]
</td> </td>
</tr> </tr>
<tr> <tr>
<td style="border: solid 1px black;" colspan=4 class="td_field"> <td class="td_unused">
RESERVED[3:0] -
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td> </td>
<td style="border: solid 1px black;" colspan=1 class="td_field"> <td style="border: solid 1px black;" colspan=1 class="td_field">
DDR3_CAL_DONE DDR3_CAL_DONE
...@@ -1029,15 +987,6 @@ P2L_PLL_LCK ...@@ -1029,15 +987,6 @@ P2L_PLL_LCK
</td> </td>
<td style="border: solid 1px black;" colspan=1 class="td_field"> <td style="border: solid 1px black;" colspan=1 class="td_field">
FMC_PRES FMC_PRES
</td>
<td >
</td>
<td >
</td>
<td >
</td> </td>
</tr> </tr>
</table> </table>
...@@ -1058,10 +1007,6 @@ SYS_PLL_LCK ...@@ -1058,10 +1007,6 @@ SYS_PLL_LCK
DDR3_CAL_DONE DDR3_CAL_DONE
</b>[<i>read-only</i>]: DDR3 calibration status </b>[<i>read-only</i>]: DDR3 calibration status
<br>0: not done<br>1: done. <br>0: not done<br>1: done.
<li><b>
RESERVED
</b>[<i>read-only</i>]: Reserved
<br>Ignore on read, write with 0's.
</ul> </ul>
<a name="CTRL"></a> <a name="CTRL"></a>
<h3><a name="sect_3_3">3.3. Control</a></h3> <h3><a name="sect_3_3">3.3. Control</a></h3>
...@@ -1127,29 +1072,29 @@ CTRL ...@@ -1127,29 +1072,29 @@ CTRL
</td> </td>
</tr> </tr>
<tr> <tr>
<td style="border: solid 1px black;" colspan=8 class="td_field"> <td class="td_unused">
RESERVED[28:21] -
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
</tr> </tr>
</table> </table>
...@@ -1181,29 +1126,29 @@ RESERVED[28:21] ...@@ -1181,29 +1126,29 @@ RESERVED[28:21]
</td> </td>
</tr> </tr>
<tr> <tr>
<td style="border: solid 1px black;" colspan=8 class="td_field"> <td class="td_unused">
RESERVED[20:13] -
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
</tr> </tr>
</table> </table>
...@@ -1235,29 +1180,29 @@ RESERVED[20:13] ...@@ -1235,29 +1180,29 @@ RESERVED[20:13]
</td> </td>
</tr> </tr>
<tr> <tr>
<td style="border: solid 1px black;" colspan=8 class="td_field"> <td class="td_unused">
RESERVED[12:5] -
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
</tr> </tr>
</table> </table>
...@@ -1289,8 +1234,20 @@ RESERVED[12:5] ...@@ -1289,8 +1234,20 @@ RESERVED[12:5]
</td> </td>
</tr> </tr>
<tr> <tr>
<td style="border: solid 1px black;" colspan=5 class="td_field"> <td class="td_unused">
RESERVED[4:0] -
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td> </td>
<td style="border: solid 1px black;" colspan=1 class="td_field"> <td style="border: solid 1px black;" colspan=1 class="td_field">
DAC_CLR_N DAC_CLR_N
...@@ -1300,18 +1257,6 @@ LED_RED ...@@ -1300,18 +1257,6 @@ LED_RED
</td> </td>
<td style="border: solid 1px black;" colspan=1 class="td_field"> <td style="border: solid 1px black;" colspan=1 class="td_field">
LED_GREEN LED_GREEN
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td> </td>
</tr> </tr>
</table> </table>
...@@ -1328,10 +1273,6 @@ LED_RED ...@@ -1328,10 +1273,6 @@ LED_RED
DAC_CLR_N DAC_CLR_N
</b>[<i>read/write</i>]: DAC clear </b>[<i>read/write</i>]: DAC clear
<br>Active low clear signal for VCXO DACs <br>Active low clear signal for VCXO DACs
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul> </ul>
<a name="RST"></a> <a name="RST"></a>
<h3><a name="sect_3_4">3.4. Reset Register</a></h3> <h3><a name="sect_3_4">3.4. Reset Register</a></h3>
...@@ -1400,29 +1341,29 @@ Controls software reset of the mezzanine including the ddr interface and the tim ...@@ -1400,29 +1341,29 @@ Controls software reset of the mezzanine including the ddr interface and the tim
</td> </td>
</tr> </tr>
<tr> <tr>
<td style="border: solid 1px black;" colspan=8 class="td_field"> <td class="td_unused">
RESERVED[30:23] -
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
</tr> </tr>
</table> </table>
...@@ -1454,29 +1395,29 @@ RESERVED[30:23] ...@@ -1454,29 +1395,29 @@ RESERVED[30:23]
</td> </td>
</tr> </tr>
<tr> <tr>
<td style="border: solid 1px black;" colspan=8 class="td_field"> <td class="td_unused">
RESERVED[22:15] -
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
</tr> </tr>
</table> </table>
...@@ -1508,29 +1449,29 @@ RESERVED[22:15] ...@@ -1508,29 +1449,29 @@ RESERVED[22:15]
</td> </td>
</tr> </tr>
<tr> <tr>
<td style="border: solid 1px black;" colspan=8 class="td_field"> <td class="td_unused">
RESERVED[14:7] -
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
</tr> </tr>
</table> </table>
...@@ -1562,29 +1503,29 @@ RESERVED[14:7] ...@@ -1562,29 +1503,29 @@ RESERVED[14:7]
</td> </td>
</tr> </tr>
<tr> <tr>
<td style="border: solid 1px black;" colspan=7 class="td_field"> <td class="td_unused">
RESERVED[6:0] -
</td> </td>
<td style="border: solid 1px black;" colspan=1 class="td_field"> <td class="td_unused">
FMC0_N -
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td style="border: solid 1px black;" colspan=1 class="td_field">
FMC0_N
</td> </td>
</tr> </tr>
</table> </table>
...@@ -1593,10 +1534,6 @@ FMC0_N ...@@ -1593,10 +1534,6 @@ FMC0_N
FMC0_N FMC0_N
</b>[<i>read/write</i>]: State of the reset line </b>[<i>read/write</i>]: State of the reset line
<br>write 0: FMC is held in reset<br> write 1: Normal FMC operation (default) <br>write 0: FMC is held in reset<br> write 1: Normal FMC operation (default)
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul> </ul>
......
hdl/spec/wb_gen/carrier_csr.wb
View file @ 8f87d9ba
...@@ -79,16 +79,6 @@ peripheral { ...@@ -79,16 +79,6 @@ peripheral {
access_bus = READ_ONLY; access_bus = READ_ONLY;
access_dev = WRITE_ONLY; access_dev = WRITE_ONLY;
}; };
field {
name = "Reserved";
description = "Ignore on read, write with 0's.";
prefix = "reserved";
type = SLV;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
}; };
reg { reg {
...@@ -121,16 +111,6 @@ peripheral { ...@@ -121,16 +111,6 @@ peripheral {
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_ONLY; access_dev = READ_ONLY;
}; };
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 29;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
}; };
reg { reg {
...@@ -148,27 +128,7 @@ peripheral { ...@@ -148,27 +128,7 @@ peripheral {
prefix = "fmc0_n"; prefix = "fmc0_n";
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_WRITE; access_dev = READ_WRITE;
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 31;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
}; };
}; };
-- ram {
-- name = "Release tag";
-- description = "256-byte ASCII area for text generated by versionning tool";
-- prefix = "rel_tag";
-- size = 64;
-- width = 32;
-- access_bus = READ_ONLY;
-- access_dev = WRITE_ONLY;
-- };
}; };
hdl/svec/rtl/carrier_csr.vhd
View file @ 8f87d9ba
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr.vhd -- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb -- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Tue Jan 14 12:04:45 2014 -- Created : Wed Apr 23 10:01:52 2014
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
...@@ -43,12 +43,8 @@ entity carrier_csr is ...@@ -43,12 +43,8 @@ entity carrier_csr is
carrier_csr_stat_ddr0_cal_done_i : in std_logic; carrier_csr_stat_ddr0_cal_done_i : in std_logic;
-- Port for BIT field: 'DDR3 bank 5 calibration status' in reg: 'Status' -- Port for BIT field: 'DDR3 bank 5 calibration status' in reg: 'Status'
carrier_csr_stat_ddr1_cal_done_i : in std_logic; carrier_csr_stat_ddr1_cal_done_i : in std_logic;
-- Port for std_logic_vector field: 'Reserved' in reg: 'Status'
carrier_csr_stat_reserved_i : in std_logic_vector(26 downto 0);
-- Port for std_logic_vector field: 'Front panel LED manual control' in reg: 'Control' -- Port for std_logic_vector field: 'Front panel LED manual control' in reg: 'Control'
carrier_csr_ctrl_fp_leds_man_o : out std_logic_vector(15 downto 0); carrier_csr_ctrl_fp_leds_man_o : out std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Control'
carrier_csr_ctrl_reserved_o : out std_logic_vector(15 downto 0);
-- Ports for BIT field: 'State of the FMC 1 reset line' in reg: 'Reset Register' -- Ports for BIT field: 'State of the FMC 1 reset line' in reg: 'Reset Register'
carrier_csr_rst_fmc0_n_o : out std_logic; carrier_csr_rst_fmc0_n_o : out std_logic;
carrier_csr_rst_fmc0_n_i : in std_logic; carrier_csr_rst_fmc0_n_i : in std_logic;
...@@ -56,17 +52,13 @@ entity carrier_csr is ...@@ -56,17 +52,13 @@ entity carrier_csr is
-- Ports for BIT field: 'State of the FMC 2 reset line' in reg: 'Reset Register' -- Ports for BIT field: 'State of the FMC 2 reset line' in reg: 'Reset Register'
carrier_csr_rst_fmc1_n_o : out std_logic; carrier_csr_rst_fmc1_n_o : out std_logic;
carrier_csr_rst_fmc1_n_i : in std_logic; carrier_csr_rst_fmc1_n_i : in std_logic;
carrier_csr_rst_fmc1_n_load_o : out std_logic; carrier_csr_rst_fmc1_n_load_o : out std_logic
-- Port for std_logic_vector field: 'Reserved' in reg: 'Reset Register'
carrier_csr_rst_reserved_o : out std_logic_vector(29 downto 0)
); );
end carrier_csr; end carrier_csr;
architecture syn of carrier_csr is architecture syn of carrier_csr is
signal carrier_csr_ctrl_fp_leds_man_int : std_logic_vector(15 downto 0); signal carrier_csr_ctrl_fp_leds_man_int : std_logic_vector(15 downto 0);
signal carrier_csr_ctrl_reserved_int : std_logic_vector(15 downto 0);
signal carrier_csr_rst_reserved_int : std_logic_vector(29 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0); signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0); signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0); signal wrdata_reg : std_logic_vector(31 downto 0);
...@@ -95,10 +87,8 @@ begin ...@@ -95,10 +87,8 @@ begin
ack_in_progress <= '0'; ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000"; rddata_reg <= "00000000000000000000000000000000";
carrier_csr_ctrl_fp_leds_man_int <= "0000000000000000"; carrier_csr_ctrl_fp_leds_man_int <= "0000000000000000";
carrier_csr_ctrl_reserved_int <= "0000000000000000";
carrier_csr_rst_fmc0_n_load_o <= '0'; carrier_csr_rst_fmc0_n_load_o <= '0';
carrier_csr_rst_fmc1_n_load_o <= '0'; carrier_csr_rst_fmc1_n_load_o <= '0';
carrier_csr_rst_reserved_int <= "000000000000000000000000000000";
elsif rising_edge(clk_sys_i) then elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register -- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1); ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
...@@ -131,27 +121,95 @@ begin ...@@ -131,27 +121,95 @@ begin
rddata_reg(2) <= carrier_csr_stat_sys_pll_lck_i; rddata_reg(2) <= carrier_csr_stat_sys_pll_lck_i;
rddata_reg(3) <= carrier_csr_stat_ddr0_cal_done_i; rddata_reg(3) <= carrier_csr_stat_ddr0_cal_done_i;
rddata_reg(4) <= carrier_csr_stat_ddr1_cal_done_i; rddata_reg(4) <= carrier_csr_stat_ddr1_cal_done_i;
rddata_reg(31 downto 5) <= carrier_csr_stat_reserved_i; rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "10" => when "10" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
carrier_csr_ctrl_fp_leds_man_int <= wrdata_reg(15 downto 0); carrier_csr_ctrl_fp_leds_man_int <= wrdata_reg(15 downto 0);
carrier_csr_ctrl_reserved_int <= wrdata_reg(31 downto 16);
end if; end if;
rddata_reg(15 downto 0) <= carrier_csr_ctrl_fp_leds_man_int; rddata_reg(15 downto 0) <= carrier_csr_ctrl_fp_leds_man_int;
rddata_reg(31 downto 16) <= carrier_csr_ctrl_reserved_int; rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "11" => when "11" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
carrier_csr_rst_fmc0_n_load_o <= '1'; carrier_csr_rst_fmc0_n_load_o <= '1';
carrier_csr_rst_fmc1_n_load_o <= '1'; carrier_csr_rst_fmc1_n_load_o <= '1';
carrier_csr_rst_reserved_int <= wrdata_reg(31 downto 2);
end if; end if;
rddata_reg(0) <= carrier_csr_rst_fmc0_n_i; rddata_reg(0) <= carrier_csr_rst_fmc0_n_i;
rddata_reg(1) <= carrier_csr_rst_fmc1_n_i; rddata_reg(1) <= carrier_csr_rst_fmc1_n_i;
rddata_reg(31 downto 2) <= carrier_csr_rst_reserved_int; rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when others => when others =>
...@@ -175,17 +233,12 @@ begin ...@@ -175,17 +233,12 @@ begin
-- System clock PLL status -- System clock PLL status
-- DDR3 bank 4 calibration status -- DDR3 bank 4 calibration status
-- DDR3 bank 5 calibration status -- DDR3 bank 5 calibration status
-- Reserved
-- Front panel LED manual control -- Front panel LED manual control
carrier_csr_ctrl_fp_leds_man_o <= carrier_csr_ctrl_fp_leds_man_int; carrier_csr_ctrl_fp_leds_man_o <= carrier_csr_ctrl_fp_leds_man_int;
-- Reserved
carrier_csr_ctrl_reserved_o <= carrier_csr_ctrl_reserved_int;
-- State of the FMC 1 reset line -- State of the FMC 1 reset line
carrier_csr_rst_fmc0_n_o <= wrdata_reg(0); carrier_csr_rst_fmc0_n_o <= wrdata_reg(0);
-- State of the FMC 2 reset line -- State of the FMC 2 reset line
carrier_csr_rst_fmc1_n_o <= wrdata_reg(1); carrier_csr_rst_fmc1_n_o <= wrdata_reg(1);
-- Reserved
carrier_csr_rst_reserved_o <= carrier_csr_rst_reserved_int;
rwaddr_reg <= wb_adr_i; rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i); wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter. -- ACK signal generation. Just pass the LSB of ACK counter.
......
hdl/svec/rtl/svec_top_fmc_adc_100Ms.vhd
View file @ 8f87d9ba
...@@ -277,16 +277,13 @@ architecture rtl of svec_top_fmc_adc_100Ms is ...@@ -277,16 +277,13 @@ architecture rtl of svec_top_fmc_adc_100Ms is
carrier_csr_stat_sys_pll_lck_i : in std_logic; carrier_csr_stat_sys_pll_lck_i : in std_logic;
carrier_csr_stat_ddr0_cal_done_i : in std_logic; carrier_csr_stat_ddr0_cal_done_i : in std_logic;
carrier_csr_stat_ddr1_cal_done_i : in std_logic; carrier_csr_stat_ddr1_cal_done_i : in std_logic;
carrier_csr_stat_reserved_i : in std_logic_vector(26 downto 0);
carrier_csr_ctrl_fp_leds_man_o : out std_logic_vector(15 downto 0); carrier_csr_ctrl_fp_leds_man_o : out std_logic_vector(15 downto 0);
carrier_csr_ctrl_reserved_o : out std_logic_vector(15 downto 0);
carrier_csr_rst_fmc0_n_o : out std_logic; carrier_csr_rst_fmc0_n_o : out std_logic;
carrier_csr_rst_fmc0_n_i : in std_logic; carrier_csr_rst_fmc0_n_i : in std_logic;
carrier_csr_rst_fmc0_n_load_o : out std_logic; carrier_csr_rst_fmc0_n_load_o : out std_logic;
carrier_csr_rst_fmc1_n_o : out std_logic; carrier_csr_rst_fmc1_n_o : out std_logic;
carrier_csr_rst_fmc1_n_i : in std_logic; carrier_csr_rst_fmc1_n_i : in std_logic;
carrier_csr_rst_fmc1_n_load_o : out std_logic; carrier_csr_rst_fmc1_n_load_o : out std_logic
carrier_csr_rst_reserved_o : out std_logic_vector(29 downto 0)
); );
end component carrier_csr; end component carrier_csr;
...@@ -877,16 +874,13 @@ begin ...@@ -877,16 +874,13 @@ begin
carrier_csr_stat_sys_pll_lck_i => sys_clk_pll_locked, carrier_csr_stat_sys_pll_lck_i => sys_clk_pll_locked,
carrier_csr_stat_ddr0_cal_done_i => ddr0_calib_done, carrier_csr_stat_ddr0_cal_done_i => ddr0_calib_done,
carrier_csr_stat_ddr1_cal_done_i => ddr1_calib_done, carrier_csr_stat_ddr1_cal_done_i => ddr1_calib_done,
carrier_csr_stat_reserved_i => (others => '0'),
carrier_csr_ctrl_fp_leds_man_o => led_state_man, carrier_csr_ctrl_fp_leds_man_o => led_state_man,
carrier_csr_ctrl_reserved_o => open,
carrier_csr_rst_fmc0_n_o => sw_rst_fmc0_n_o, carrier_csr_rst_fmc0_n_o => sw_rst_fmc0_n_o,
carrier_csr_rst_fmc0_n_i => sw_rst_fmc0_n_i, carrier_csr_rst_fmc0_n_i => sw_rst_fmc0_n_i,
carrier_csr_rst_fmc0_n_load_o => sw_rst_fmc0_n_load, carrier_csr_rst_fmc0_n_load_o => sw_rst_fmc0_n_load,
carrier_csr_rst_fmc1_n_o => sw_rst_fmc1_n_o, carrier_csr_rst_fmc1_n_o => sw_rst_fmc1_n_o,
carrier_csr_rst_fmc1_n_i => sw_rst_fmc1_n_i, carrier_csr_rst_fmc1_n_i => sw_rst_fmc1_n_i,
carrier_csr_rst_fmc1_n_load_o => sw_rst_fmc1_n_load, carrier_csr_rst_fmc1_n_load_o => sw_rst_fmc1_n_load
carrier_csr_rst_reserved_o => open
); );
-- Unused wishbone signals -- Unused wishbone signals
......
hdl/svec/wb_gen/carrier_csr.h
View file @ 8f87d9ba
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
* File : carrier_csr.h * File : carrier_csr.h
* Author : auto-generated by wbgen2 from carrier_csr.wb * Author : auto-generated by wbgen2 from carrier_csr.wb
* Created : Tue Jan 14 12:04:45 2014 * Created : Wed Apr 23 10:01:52 2014
* Standard : ANSI C * Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
...@@ -68,12 +68,6 @@ ...@@ -68,12 +68,6 @@
/* definitions for field: DDR3 bank 5 calibration status in reg: Status */ /* definitions for field: DDR3 bank 5 calibration status in reg: Status */
#define CARRIER_CSR_STAT_DDR1_CAL_DONE WBGEN2_GEN_MASK(4, 1) #define CARRIER_CSR_STAT_DDR1_CAL_DONE WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Reserved in reg: Status */
#define CARRIER_CSR_STAT_RESERVED_MASK WBGEN2_GEN_MASK(5, 27)
#define CARRIER_CSR_STAT_RESERVED_SHIFT 5
#define CARRIER_CSR_STAT_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 5, 27)
#define CARRIER_CSR_STAT_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 5, 27)
/* definitions for register: Control */ /* definitions for register: Control */
/* definitions for field: Front panel LED manual control in reg: Control */ /* definitions for field: Front panel LED manual control in reg: Control */
...@@ -82,12 +76,6 @@ ...@@ -82,12 +76,6 @@
#define CARRIER_CSR_CTRL_FP_LEDS_MAN_W(value) WBGEN2_GEN_WRITE(value, 0, 16) #define CARRIER_CSR_CTRL_FP_LEDS_MAN_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define CARRIER_CSR_CTRL_FP_LEDS_MAN_R(reg) WBGEN2_GEN_READ(reg, 0, 16) #define CARRIER_CSR_CTRL_FP_LEDS_MAN_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Reserved in reg: Control */
#define CARRIER_CSR_CTRL_RESERVED_MASK WBGEN2_GEN_MASK(16, 16)
#define CARRIER_CSR_CTRL_RESERVED_SHIFT 16
#define CARRIER_CSR_CTRL_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define CARRIER_CSR_CTRL_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Reset Register */ /* definitions for register: Reset Register */
/* definitions for field: State of the FMC 1 reset line in reg: Reset Register */ /* definitions for field: State of the FMC 1 reset line in reg: Reset Register */
...@@ -96,12 +84,6 @@ ...@@ -96,12 +84,6 @@
/* definitions for field: State of the FMC 2 reset line in reg: Reset Register */ /* definitions for field: State of the FMC 2 reset line in reg: Reset Register */
#define CARRIER_CSR_RST_FMC1_N WBGEN2_GEN_MASK(1, 1) #define CARRIER_CSR_RST_FMC1_N WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Reserved in reg: Reset Register */
#define CARRIER_CSR_RST_RESERVED_MASK WBGEN2_GEN_MASK(2, 30)
#define CARRIER_CSR_RST_RESERVED_SHIFT 2
#define CARRIER_CSR_RST_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 2, 30)
#define CARRIER_CSR_RST_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 2, 30)
PACKED struct CARRIER_CSR_WB { PACKED struct CARRIER_CSR_WB {
/* [0x0]: REG Carrier type and PCB version */ /* [0x0]: REG Carrier type and PCB version */
uint32_t CARRIER; uint32_t CARRIER;
......
hdl/svec/wb_gen/carrier_csr.htm
View file @ 8f87d9ba
...@@ -322,23 +322,6 @@ carrier_csr_stat_ddr1_cal_done_i ...@@ -322,23 +322,6 @@ carrier_csr_stat_ddr1_cal_done_i
</td> </td>
<td class="td_pblock_left"> <td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_stat_reserved_i[26:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td> </td>
<td class="td_sym_center"> <td class="td_sym_center">
&nbsp; &nbsp;
...@@ -390,23 +373,6 @@ carrier_csr_ctrl_fp_leds_man_o[15:0] ...@@ -390,23 +373,6 @@ carrier_csr_ctrl_fp_leds_man_o[15:0]
</td> </td>
<td class="td_pblock_left"> <td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_ctrl_reserved_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td> </td>
<td class="td_sym_center"> <td class="td_sym_center">
&nbsp; &nbsp;
...@@ -537,23 +503,6 @@ carrier_csr_rst_fmc1_n_load_o ...@@ -537,23 +503,6 @@ carrier_csr_rst_fmc1_n_load_o
&rarr; &rarr;
</td> </td>
</tr> </tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_rst_reserved_o[29:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
</table> </table>
<h3><a name="sect_3_0">3. Register description</a></h3> <h3><a name="sect_3_0">3. Register description</a></h3>
...@@ -887,29 +836,29 @@ STAT ...@@ -887,29 +836,29 @@ STAT
</td> </td>
</tr> </tr>
<tr> <tr>
<td style="border: solid 1px black;" colspan=8 class="td_field"> <td class="td_unused">
RESERVED[26:19] -
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
</tr> </tr>
</table> </table>
...@@ -941,29 +890,29 @@ RESERVED[26:19] ...@@ -941,29 +890,29 @@ RESERVED[26:19]
</td> </td>
</tr> </tr>
<tr> <tr>
<td style="border: solid 1px black;" colspan=8 class="td_field"> <td class="td_unused">
RESERVED[18:11] -
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
</tr> </tr>
</table> </table>
...@@ -995,29 +944,29 @@ RESERVED[18:11] ...@@ -995,29 +944,29 @@ RESERVED[18:11]
</td> </td>
</tr> </tr>
<tr> <tr>
<td style="border: solid 1px black;" colspan=8 class="td_field"> <td class="td_unused">
RESERVED[10:3] -
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
</tr> </tr>
</table> </table>
...@@ -1049,8 +998,14 @@ RESERVED[10:3] ...@@ -1049,8 +998,14 @@ RESERVED[10:3]
</td> </td>
</tr> </tr>
<tr> <tr>
<td style="border: solid 1px black;" colspan=3 class="td_field"> <td class="td_unused">
RESERVED[2:0] -
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td> </td>
<td style="border: solid 1px black;" colspan=1 class="td_field"> <td style="border: solid 1px black;" colspan=1 class="td_field">
DDR1_CAL_DONE DDR1_CAL_DONE
...@@ -1066,12 +1021,6 @@ FMC1_PRES ...@@ -1066,12 +1021,6 @@ FMC1_PRES
</td> </td>
<td style="border: solid 1px black;" colspan=1 class="td_field"> <td style="border: solid 1px black;" colspan=1 class="td_field">
FMC0_PRES FMC0_PRES
</td>
<td >
</td>
<td >
</td> </td>
</tr> </tr>
</table> </table>
...@@ -1096,10 +1045,6 @@ DDR0_CAL_DONE ...@@ -1096,10 +1045,6 @@ DDR0_CAL_DONE
DDR1_CAL_DONE DDR1_CAL_DONE
</b>[<i>read-only</i>]: DDR3 bank 5 calibration status </b>[<i>read-only</i>]: DDR3 bank 5 calibration status
<br>0: not done<br>1: done. <br>0: not done<br>1: done.
<li><b>
RESERVED
</b>[<i>read-only</i>]: Reserved
<br>Ignore on read, write with 0's.
</ul> </ul>
<a name="CTRL"></a> <a name="CTRL"></a>
<h3><a name="sect_3_3">3.3. Control</a></h3> <h3><a name="sect_3_3">3.3. Control</a></h3>
...@@ -1165,29 +1110,29 @@ CTRL ...@@ -1165,29 +1110,29 @@ CTRL
</td> </td>
</tr> </tr>
<tr> <tr>
<td style="border: solid 1px black;" colspan=8 class="td_field"> <td class="td_unused">
RESERVED[15:8] -
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
</tr> </tr>
</table> </table>
...@@ -1219,29 +1164,29 @@ RESERVED[15:8] ...@@ -1219,29 +1164,29 @@ RESERVED[15:8]
</td> </td>
</tr> </tr>
<tr> <tr>
<td style="border: solid 1px black;" colspan=8 class="td_field"> <td class="td_unused">
RESERVED[7:0] -
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
</tr> </tr>
</table> </table>
...@@ -1358,10 +1303,6 @@ FP_LEDS_MAN[7:0] ...@@ -1358,10 +1303,6 @@ FP_LEDS_MAN[7:0]
FP_LEDS_MAN FP_LEDS_MAN
</b>[<i>read/write</i>]: Front panel LED manual control </b>[<i>read/write</i>]: Front panel LED manual control
<br>Height front panel LED, two bits per LED.<br>00 = OFF<br>01 = Green<br>10 = Red<br>11 = Orange <br>Height front panel LED, two bits per LED.<br>00 = OFF<br>01 = Green<br>10 = Red<br>11 = Orange
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul> </ul>
<a name="RST"></a> <a name="RST"></a>
<h3><a name="sect_3_4">3.4. Reset Register</a></h3> <h3><a name="sect_3_4">3.4. Reset Register</a></h3>
...@@ -1430,29 +1371,29 @@ Controls software reset of the mezzanines including the ddr interface and the ti ...@@ -1430,29 +1371,29 @@ Controls software reset of the mezzanines including the ddr interface and the ti
</td> </td>
</tr> </tr>
<tr> <tr>
<td style="border: solid 1px black;" colspan=8 class="td_field"> <td class="td_unused">
RESERVED[29:22] -
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
</tr> </tr>
</table> </table>
...@@ -1484,29 +1425,29 @@ RESERVED[29:22] ...@@ -1484,29 +1425,29 @@ RESERVED[29:22]
</td> </td>
</tr> </tr>
<tr> <tr>
<td style="border: solid 1px black;" colspan=8 class="td_field"> <td class="td_unused">
RESERVED[21:14] -
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
</tr> </tr>
</table> </table>
...@@ -1538,29 +1479,29 @@ RESERVED[21:14] ...@@ -1538,29 +1479,29 @@ RESERVED[21:14]
</td> </td>
</tr> </tr>
<tr> <tr>
<td style="border: solid 1px black;" colspan=8 class="td_field"> <td class="td_unused">
RESERVED[13:6] -
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
</tr> </tr>
</table> </table>
...@@ -1592,29 +1533,29 @@ RESERVED[13:6] ...@@ -1592,29 +1533,29 @@ RESERVED[13:6]
</td> </td>
</tr> </tr>
<tr> <tr>
<td style="border: solid 1px black;" colspan=6 class="td_field"> <td class="td_unused">
RESERVED[5:0] -
</td> </td>
<td style="border: solid 1px black;" colspan=1 class="td_field"> <td class="td_unused">
FMC1_N -
</td> </td>
<td style="border: solid 1px black;" colspan=1 class="td_field"> <td class="td_unused">
FMC0_N -
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td style="border: solid 1px black;" colspan=1 class="td_field">
FMC1_N
</td> </td>
<td > <td style="border: solid 1px black;" colspan=1 class="td_field">
FMC0_N
</td> </td>
</tr> </tr>
</table> </table>
...@@ -1627,10 +1568,6 @@ FMC0_N ...@@ -1627,10 +1568,6 @@ FMC0_N
FMC1_N FMC1_N
</b>[<i>read/write</i>]: State of the FMC 2 reset line </b>[<i>read/write</i>]: State of the FMC 2 reset line
<br>write 0: FMC is held in reset<br> write 1: Normal FMC operation (default) <br>write 0: FMC is held in reset<br> write 1: Normal FMC operation (default)
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul> </ul>
......
hdl/svec/wb_gen/carrier_csr.wb
View file @ 8f87d9ba
...@@ -88,16 +88,6 @@ peripheral { ...@@ -88,16 +88,6 @@ peripheral {
access_bus = READ_ONLY; access_bus = READ_ONLY;
access_dev = WRITE_ONLY; access_dev = WRITE_ONLY;
}; };
field {
name = "Reserved";
description = "Ignore on read, write with 0's.";
prefix = "reserved";
type = SLV;
size = 27;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
}; };
reg { reg {
...@@ -113,16 +103,6 @@ peripheral { ...@@ -113,16 +103,6 @@ peripheral {
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_ONLY; access_dev = READ_ONLY;
}; };
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
}; };
reg { reg {
...@@ -152,16 +132,6 @@ peripheral { ...@@ -152,16 +132,6 @@ peripheral {
prefix = "fmc1_n"; prefix = "fmc1_n";
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_WRITE; access_dev = READ_WRITE;
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 30;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
}; };
}; };
......
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