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FMC ADC 100M 14b 4cha - Gateware
Commit 91268c4f authored by mcattin's avatar mcattin
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Fix timing issues. 

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@42 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
parent 72c71b2c
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Showing with 951 additions and 216 deletions
hdl/spec/ise_project/_xmsgs/pn_parser.xmsgs
View file @ 91268c4f
......@@ -8,8 +8,5 @@
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/rtl/fmc_adc_100Ms_core.vhd&quot; into library work</arg>
</msg>
</messages>
hdl/spec/ise_project/iseconfig/spec_fmc_adc_100Ms.projectmgr
View file @ 91268c4f
......@@ -6,36 +6,45 @@
<!--This is an ISE project configuration file.-->
<ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
<ClosedNodes>
<ClosedNode>/Automatic `includes</ClosedNode>
<ClosedNode>/ddr3_ctrl - rtl</ClosedNode>
<ClosedNode>/gn4124_core - rtl</ClosedNode>
<ClosedNode>/spec_top - rtl/cmp_ddr_ctrl - ddr3_ctrl - rtl</ClosedNode>
<ClosedNode>/spec_top - rtl/cmp_fmc_adc_100Ms_core - fmc_adc_100Ms_core - rtl</ClosedNode>
<ClosedNode>/spec_top - rtl/cmp_fmc_i2c - i2c_master_top - structural</ClosedNode>
<ClosedNode>/spec_top - rtl/cmp_fmc_spi - wb_spi_master</ClosedNode>
<ClosedNode>/spec_top - rtl/cmp_gn4124_core - gn4124_core - rtl</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>xc6slx45t-3fgg484</SelectedItem>
<SelectedItem>spec_top - rtl (/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd)</SelectedItem>
</SelectedItems>
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<CurrentItem>xc6slx45t-3fgg484</CurrentItem>
<CurrentItem>spec_top - rtl (/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd)</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
<ClosedNodes>
<ClosedNode>Configure Target Device</ClosedNode>
<ClosedNode>Design Utilities</ClosedNode>
<ClosedNode>Implement Design</ClosedNode>
<ClosedNode>Implement Design/Map</ClosedNode>
<ClosedNode>Implement Design/Place &amp; Route</ClosedNode>
<ClosedNode>Implement Design/Place &amp; Route/Back-annotate Pin Locations</ClosedNode>
<ClosedNode>Implement Design/Place &amp; Route/Generate IBIS Model</ClosedNode>
<ClosedNode>Implement Design/Place &amp; Route/Generate Post-Place &amp; Route Static Timing</ClosedNode>
<ClosedNode>Implement Design/Translate</ClosedNode>
<ClosedNode>Synthesize - XST</ClosedNode>
<ClosedNode>User Constraints</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem/>
<SelectedItem>Place &amp; Route</SelectedItem>
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<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
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<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem/>
<CurrentItem>Place &amp; Route</CurrentItem>
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<ItemView guiview="File" >
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......@@ -57,7 +66,7 @@
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>work</CurrentItem>
</ItemView>
<SourceProcessView>000000ff00000000000000020000014c0000011d01000000060100000002</SourceProcessView>
<SourceProcessView>000000ff000000000000000200000101000000ec01000000060100000002</SourceProcessView>
<CurrentView>Implementation</CurrentView>
<ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
<ClosedNodes>
......@@ -72,4 +81,28 @@
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Add Existing Source</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_NGC" guiview="Process" >
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<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Add Existing Source</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" >
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<ClosedNode>Design Utilities</ClosedNode>
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<SelectedItems>
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<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Add Existing Source</CurrentItem>
</ItemView>
</Project>
hdl/spec/ise_project/iseconfig/spec_top.xreport
View file @ 91268c4f
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2011-03-04T18:20:06</DateModified>
<DateModified>2011-03-09T11:16:52</DateModified>
<ModuleName>spec_top</ModuleName>
<SummaryTimeStamp>Unknown</SummaryTimeStamp>
<SummaryTimeStamp>2011-03-09T11:15:37</SummaryTimeStamp>
<SavedFilePath>/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/ise_project/iseconfig/spec_top.xreport</SavedFilePath>
<ImplementationReportsDirectory>/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/ise_project/</ImplementationReportsDirectory>
<DateInitialized>2011-02-24T10:24:34</DateInitialized>
......@@ -19,11 +19,11 @@
<toc-item title="Detailed Reports" target="Detailed Reports" />
</view>
<view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="spec_top_envsettings.html" label="System Settings" />
<view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="spec_top_map.xrpt" label="IOB Properties" />
<view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="spec_top_map.xrpt" showConstraints="0" label="IOB Properties" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="spec_top_map.xrpt" label="Control Set Information" />
<view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="spec_top_map.xrpt" label="Module Level Utilization" />
<view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="spec_top.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
<view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="spec_top_par.xrpt" label="Pinout Report" />
<view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="spec_top.ptwx" showConstraints="0" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
<view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="spec_top_par.xrpt" showConstraints="0" label="Pinout Report" />
<view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="spec_top_par.xrpt" label="Clock Report" />
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="spec_top.twx" label="Static Timing" />
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="spec_top_html/fit/report.htm" label="CPLD Fitter Report" />
......
hdl/spec/ise_project/spec_top_summary.html
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This diff is collapsed.
hdl/spec/rtl/fmc_adc_100Ms_core.vhd
View file @ 91268c4f
......@@ -79,7 +79,7 @@ entity fmc_adc_100Ms_core is
gpio_ssr_ch2_o : out std_logic_vector(6 downto 0); -- Channel 2 solid state relays control
gpio_ssr_ch3_o : out std_logic_vector(6 downto 0); -- Channel 3 solid state relays control
gpio_ssr_ch4_o : out std_logic_vector(6 downto 0); -- Channel 4 solid state relays control
gpio_si750_oe_o : out std_logic -- Si750 (programmable oscillator) output enable
gpio_si570_oe_o : out std_logic -- Si570 (programmable oscillator) output enable
);
end fmc_adc_100Ms_core;
......@@ -215,6 +215,23 @@ architecture rtl of fmc_adc_100Ms_core is
valid : out std_logic);
end component wb_sync_fifo;
component monostable
generic(
g_INPUT_POLARITY : std_logic := '1'; --! trigger_i polarity
--! ('0'=negative, 1=positive)
g_OUTPUT_POLARITY : std_logic := '1'; --! pulse_o polarity
--! ('0'=negative, 1=positive)
g_OUTPUT_RETRIG : boolean := false; --! Retriggerable output monostable
g_OUTPUT_LENGTH : natural := 1 --! pulse_o lenght (in clk_i ticks)
);
port (
rst_n_i : in std_logic; --! Reset (active low)
clk_i : in std_logic; --! Clock
trigger_i : in std_logic; --! Trigger input pulse
pulse_o : out std_logic --! Monostable output pulse
);
end component monostable;
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
......@@ -332,6 +349,25 @@ architecture rtl of fmc_adc_100Ms_core is
begin
------------------------------------------------------------------------------
-- LEDs
------------------------------------------------------------------------------
gpio_led_power_o <= serdes_synced;
cmp_trig_led_monostable : monostable
generic map(
g_INPUT_POLARITY => '1',
g_OUTPUT_POLARITY => '1',
g_OUTPUT_RETRIG => true,
g_OUTPUT_LENGTH => 12500000
)
port map(
rst_n_i => sys_rst_n_i,
clk_i => sys_clk_i,
trigger_i => acq_fsm_trig,
pulse_o => gpio_led_trigger_o
);
------------------------------------------------------------------------------
-- Resets
------------------------------------------------------------------------------
......@@ -454,13 +490,13 @@ begin
-- serdes bitslip generation
p_bitslip : process (serdes_clk, sys_rst_n_i)
p_bitslip : process (fs_clk, sys_rst_n_i)
begin
if sys_rst_n_i = '0' then
bitslip_sreg <= std_logic_vector(to_unsigned(1, bitslip_sreg'length));
serdes_bitslip <= '0';
serdes_synced <= '0';
elsif rising_edge(serdes_clk) then
elsif rising_edge(fs_clk) then
-- Shift register to generate bitslip enable (serdes_clk/8)
bitslip_sreg <= bitslip_sreg(0) & bitslip_sreg(bitslip_sreg'length-1 downto 1);
......@@ -499,7 +535,7 @@ begin
fs_clk_i => fs_clk,
fmc_adc_core_ctl_fsm_cmd_o => fsm_cmd,
fmc_adc_core_ctl_fsm_cmd_wr_o => fsm_cmd_wr,
fmc_adc_core_ctl_fmc_clk_oe_o => gpio_si750_oe_o,
fmc_adc_core_ctl_fmc_clk_oe_o => gpio_si570_oe_o,
fmc_adc_core_ctl_offset_dac_clr_n_o => gpio_dac_clr_n_o,
fmc_adc_core_sta_fsm_i => "000",
fmc_adc_core_sta_serdes_pll_i => locked_out,
......@@ -865,7 +901,7 @@ begin
wb_sync_fifo_din <= sync_fifo_dout(63 downto 0);
wb_sync_fifo_wr <= wb_sync_fifo_wr_en and not(wb_sync_fifo_full);
wb_sync_fifo_rd <= wb_sync_fifo_dreq and not(wb_sync_fifo_empty);
wb_sync_fifo_rd <= wb_sync_fifo_dreq and not(wb_sync_fifo_empty); -- and not(wb_ddr_stall_i)
wb_sync_fifo_dreq <= '1';
------------------------------------------------------------------------------
......@@ -910,7 +946,7 @@ begin
wb_ddr_adr_o <= (others => '0');
wb_ddr_dat_o <= (others => '0');
elsif rising_edge(wb_ddr_clk_i) then
if (wb_sync_fifo_valid = '1') and (wb_ddr_stall_i = '0') then
if wb_sync_fifo_valid = '1' then --if (wb_sync_fifo_valid = '1') and (wb_ddr_stall_i = '0') then
wb_ddr_cyc_o <= '1';
wb_ddr_we_o <= '1';
wb_ddr_stb_o <= '1';
......
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
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This diff is collapsed.
hdl/spec/spec_top_fmc_adc_100Ms.ucf
View file @ 91268c4f
......@@ -197,9 +197,9 @@ NET "GPIO[1]" IOSTANDARD = "LVCMOS25";
# FMC slot
#----------------------------------------
NET "ext_trigger_n_i" LOC = AB13; # LA17_N
NET "ext_trigger_n_i" IOSTANDARD = "LVCMOS25";
NET "ext_trigger_n_i" IOSTANDARD = "LVDS_25";
NET "ext_trigger_p_i" LOC = Y13; # LA17_P
NET "ext_trigger_p_i" IOSTANDARD = "LVCMOS25";
NET "ext_trigger_p_i" IOSTANDARD = "LVDS_25";
# dco_p and dco_n are swapped compared to the FMC ADC schematics
# this is to be coherent in the hdl design
......@@ -208,9 +208,9 @@ NET "adc_dco_n_i" IOSTANDARD = "LVDS_25";
NET "adc_dco_p_i" LOC = Y11; # LA00_P
NET "adc_dco_p_i" IOSTANDARD = "LVDS_25";
NET "adc_fr_p_i" LOC = AB12; # LA01_N
NET "adc_fr_p_i" LOC = AA12; # LA01_N
NET "adc_fr_p_i" IOSTANDARD = "LVDS_25";
NET "adc_fr_n_i" LOC = AA12; # LA01_P
NET "adc_fr_n_i" LOC = AB12; # LA01_P
NET "adc_fr_n_i" IOSTANDARD = "LVDS_25";
NET "adc_outa_n_i[0]" LOC = AB4; # LA14_N
......@@ -334,10 +334,10 @@ NET "gpio_ssr_ch4_o[6]" IOSTANDARD = "LVCMOS25";
NET "gpio_si570_oe_o" LOC = AB5; # LA06_N
NET "gpio_si570_oe_o" IOSTANDARD = "LVCMOS25";
NET "si750_thermo_scl_b" LOC = U12; # LA18_N
NET "si750_thermo_scl_b" IOSTANDARD = "LVCMOS25";
NET "si750_thermo_sda_b" LOC = T12; # LA18_P
NET "si750_thermo_sda_b" IOSTANDARD = "LVCMOS25";
NET "si570_thermo_scl_b" LOC = U12; # LA18_N
NET "si570_thermo_scl_b" IOSTANDARD = "LVCMOS25";
NET "si570_thermo_sda_b" LOC = T12; # LA18_P
NET "si570_thermo_sda_b" IOSTANDARD = "LVCMOS25";
NET "prsnt_m2c_n_i" LOC = A2; # PRSNT_M2C_L
NET "prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
......@@ -531,6 +531,9 @@ NET "DDR3_DQ[15]" IOSTANDARD = "SSTL15_II";
INST "cmp_gn4124_core/l2p_rdy_t" IOB=FALSE;
INST "cmp_gn4124_core/l_wr_rdy_t*" IOB=FALSE;
INST "cmp_fmc_spi/shift/s_out" IOB=FALSE;
INST "cmp_fmc_spi/clgen/clk_out" IOB=FALSE;
#===============================================================================
# Terminations
......
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