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FMC ADC 100M 14b 4cha - Gateware
Commit b7fbece5 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: Introduce separate trigger delays for external and internal (channel) triggers.

parent d7472f32
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doc/manual/fmc_adc_100Ms_csr.tex
View file @ b7fbece5
......@@ -23,8 +23,8 @@ REG @tab
Trigger polarity
@item @code{0x14} @tab
REG @tab
@code{trig_dly} @tab
Trigger delay
@code{ext_trig_dly} @tab
External trigger delay
@item @code{0x18} @tab
REG @tab
@code{sw_trig} @tab
......@@ -89,6 +89,10 @@ Channel 1 saturation register
REG @tab
@code{ch1_trig_thres} @tab
Channel 1 trigger threshold configuration register
@item @code{0x98} @tab
REG @tab
@code{ch1_trig_dly} @tab
Channel 1 trigger delay
@item @code{0x100} @tab
REG @tab
@code{ch2_ctl} @tab
......@@ -113,6 +117,10 @@ Channel 2 saturation register
REG @tab
@code{ch2_trig_thres} @tab
Channel 2 trigger threshold configuration register
@item @code{0x118} @tab
REG @tab
@code{ch2_trig_dly} @tab
Channel 2 trigger delay
@item @code{0x180} @tab
REG @tab
@code{ch3_ctl} @tab
......@@ -137,6 +145,10 @@ Channel 3 saturation register
REG @tab
@code{ch3_trig_thres} @tab
Channel 3 trigger threshold configuration register
@item @code{0x198} @tab
REG @tab
@code{ch3_trig_dly} @tab
Channel 3 trigger delay
@item @code{0x200} @tab
REG @tab
@code{ch4_ctl} @tab
......@@ -161,6 +173,10 @@ Channel 4 saturation register
REG @tab
@code{ch4_trig_thres} @tab
Channel 4 trigger threshold configuration register
@item @code{0x218} @tab
REG @tab
@code{ch4_trig_dly} @tab
Channel 4 trigger delay
@end multitable
@regsection @code{ctl} - Control register
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -375,18 +391,18 @@ Channel 4 internal threshold trigger
@item @code{ch3} @tab 0: positive edge/slope@*1: negative edge/slope
@item @code{ch4} @tab 0: positive edge/slope@*1: negative edge/slope
@end multitable
@regsection @code{trig_dly} - Trigger delay
@regsection @code{ext_trig_dly} - External trigger delay
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/W @tab
@code{TRIG_DLY}
@code{EXT_TRIG_DLY}
@tab @code{0} @tab
Trigger delay value
External trigger delay value
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{trig_dly} @tab Delay to apply on the trigger in sampling clock period.@*The default clock frequency is 100MHz (period = 10ns).
@item @code{ext_trig_dly} @tab Delay to apply on the trigger in sampling clock period.@*The default clock frequency is 100MHz (period = 10ns).
@end multitable
@regsection @code{sw_trig} - Software trigger
Writing (anything) to this register generates a software trigger.
......@@ -599,6 +615,19 @@ Internal trigger threshold hysteresis
@item @code{val} @tab Treated as binary two's complement and compared to raw ADC data.
@item @code{hyst} @tab Configures the internal trigger threshold hysteresis (two's complement).
@end multitable
@regsection @code{ch1_trig_dly} - Channel 1 trigger delay
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/W @tab
@code{CH1_TRIG_DLY}
@tab @code{0} @tab
Channel 1 trigger delay value
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{ch1_trig_dly} @tab Delay to apply on the trigger in sampling clock period.@*The default clock frequency is 100MHz (period = 10ns).
@end multitable
@regsection @code{ch2_ctl} - Channel 2 control register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
......@@ -683,6 +712,19 @@ Internal trigger threshold hysteresis
@item @code{val} @tab Treated as binary two's complement and compared to raw ADC data.
@item @code{hyst} @tab Configures the internal trigger threshold hysteresis (two's complement).
@end multitable
@regsection @code{ch2_trig_dly} - Channel 2 trigger delay
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/W @tab
@code{CH2_TRIG_DLY}
@tab @code{0} @tab
Channel 2 trigger delay value
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{ch2_trig_dly} @tab Delay to apply on the trigger in sampling clock period.@*The default clock frequency is 100MHz (period = 10ns).
@end multitable
@regsection @code{ch3_ctl} - Channel 3 control register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
......@@ -767,6 +809,19 @@ Internal trigger threshold hysteresis
@item @code{val} @tab Treated as binary two's complement and compared to raw ADC data.
@item @code{hyst} @tab Configures the internal trigger threshold hysteresis (two's complement).
@end multitable
@regsection @code{ch3_trig_dly} - Channel 3 trigger delay
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/W @tab
@code{CH3_TRIG_DLY}
@tab @code{0} @tab
Channel 3 trigger delay value
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{ch3_trig_dly} @tab Delay to apply on the trigger in sampling clock period.@*The default clock frequency is 100MHz (period = 10ns).
@end multitable
@regsection @code{ch4_ctl} - Channel 4 control register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
......@@ -851,3 +906,16 @@ Internal trigger threshold hysteresis
@item @code{val} @tab Treated as binary two's complement and compared to raw ADC data.
@item @code{hyst} @tab Configures the internal trigger threshold hysteresis (two's complement).
@end multitable
@regsection @code{ch4_trig_dly} - Channel 4 trigger delay
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/W @tab
@code{CH4_TRIG_DLY}
@tab @code{0} @tab
Channel 4 trigger delay value
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{ch4_trig_dly} @tab Delay to apply on the trigger in sampling clock period.@*The default clock frequency is 100MHz (period = 10ns).
@end multitable
hdl/adc/rtl/fmc_adc_100Ms_core.vhd
View file @ b7fbece5
......@@ -9,7 +9,7 @@
-- Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-02-24
-- Last update: 2018-01-25
-- Last update: 2018-01-26
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: FMC ADC 100Ms/s core.
......@@ -195,6 +195,8 @@ architecture rtl of fmc_adc_100Ms_core is
------------------------------------------------------------------------------
type t_acq_fsm_state is (IDLE, PRE_TRIG, WAIT_TRIG, POST_TRIG, TRIG_TAG, DECR_SHOT);
type t_fmc_adc_vec16_array is array (positive range<>) of std_logic_vector(15 downto 0);
type t_fmc_adc_vec32_array is array (positive range<>) of std_logic_vector(31 downto 0);
type t_fmc_adc_uint32_array is array (positive range<>) of unsigned(31 downto 0);
------------------------------------------------------------------------------
-- Signals declaration
......@@ -233,34 +235,37 @@ architecture rtl of fmc_adc_100Ms_core is
-- Trigger
signal ext_trig_a, ext_trig : std_logic;
signal ext_trig_p, ext_trig_n : std_logic;
signal ext_trig_d : std_logic;
signal time_trig : std_logic;
signal time_trig_d : std_logic;
signal int_ch_trig : std_logic_vector(1 to 4);
signal ext_trig_delay : std_logic_vector(31 downto 0);
signal ext_trig_delay_cnt : unsigned(31 downto 0);
signal ext_trig_en : std_logic;
signal ext_trig_fixed_delay : std_logic_vector(7 downto 0);
signal ext_trig_p, ext_trig_n : std_logic;
signal ext_trig_pol : std_logic;
signal int_trig : std_logic_vector(1 to 4);
signal int_trig_d : std_logic_vector(1 to 4);
signal int_trig_data : t_fmc_adc_vec16_array(1 to 4);
signal int_trig_delay : t_fmc_adc_vec32_array(1 to 4);
signal int_trig_delay_cnt : t_fmc_adc_uint32_array(1 to 4);
signal int_trig_en : std_logic_vector(1 to 4);
signal int_trig_pol : std_logic_vector(1 to 4);
signal int_trig_thres : t_fmc_adc_vec16_array(1 to 4);
signal int_trig_thres_hyst : t_fmc_adc_vec16_array(1 to 4);
signal ext_trig_pol : std_logic;
signal int_trig_pol : std_logic_vector(1 to 4);
signal ext_trig_en : std_logic;
signal int_trig_en : std_logic_vector(1 to 4);
signal time_trig_en : std_logic;
signal sw_trig : std_logic;
signal sw_trig_d : std_logic;
signal sw_trig_en : std_logic;
signal sw_trig_fixed_delay : std_logic_vector(4 downto 0);
signal time_trig : std_logic;
signal time_trig_en : std_logic;
signal time_trig_fixed_delay : std_logic_vector(4 downto 0);
signal trig : std_logic;
signal trig_delay : std_logic_vector(31 downto 0);
signal trig_delay_cnt : unsigned(31 downto 0);
signal trig_d : std_logic;
signal trig_align : std_logic;
signal trig_storage : std_logic_vector(31 downto 0);
signal trig_fifo_wr : std_logic;
signal trig_fifo_rd : std_logic;
signal trig_fifo_empty : std_logic;
signal trig_fifo_full : std_logic;
signal trig_fifo_din : std_logic_vector(32 downto 0);
signal trig_fifo_dout : std_logic_vector(32 downto 0);
signal trig_fifo_empty : std_logic;
signal trig_fifo_full : std_logic;
signal trig_fifo_rd : std_logic;
signal trig_fifo_wr : std_logic;
signal trig_storage : std_logic_vector(31 downto 0);
-- Under-sampling
signal undersample_factor : std_logic_vector(31 downto 0);
......@@ -679,28 +684,32 @@ begin
test_data_en <= csr_regout.ctl_test_data_en_o;
trig_led_man <= csr_regout.ctl_trig_led_o;
acq_led_man <= csr_regout.ctl_acq_led_o;
ext_trig_delay <= csr_regout.ext_trig_dly_o;
ext_trig_en <= csr_regout.trig_en_ext_o;
sw_trig_en <= csr_regout.trig_en_sw_o;
time_trig_en <= csr_regout.trig_en_time_o;
ext_trig_pol <= csr_regout.trig_pol_ext_o;
int_trig_delay(1) <= csr_regout.ch1_trig_dly_o;
int_trig_delay(2) <= csr_regout.ch2_trig_dly_o;
int_trig_delay(3) <= csr_regout.ch3_trig_dly_o;
int_trig_delay(4) <= csr_regout.ch4_trig_dly_o;
int_trig_en(1) <= csr_regout.trig_en_ch1_o;
int_trig_en(2) <= csr_regout.trig_en_ch2_o;
int_trig_en(3) <= csr_regout.trig_en_ch3_o;
int_trig_en(4) <= csr_regout.trig_en_ch4_o;
ext_trig_pol <= csr_regout.trig_pol_ext_o;
int_trig_pol(1) <= csr_regout.trig_pol_ch1_o;
int_trig_pol(2) <= csr_regout.trig_pol_ch2_o;
int_trig_pol(3) <= csr_regout.trig_pol_ch3_o;
int_trig_pol(4) <= csr_regout.trig_pol_ch4_o;
int_trig_thres_hyst(1) <= csr_regout.ch1_trig_thres_hyst_o;
int_trig_thres_hyst(2) <= csr_regout.ch2_trig_thres_hyst_o;
int_trig_thres_hyst(3) <= csr_regout.ch3_trig_thres_hyst_o;
int_trig_thres_hyst(4) <= csr_regout.ch4_trig_thres_hyst_o;
int_trig_thres(1) <= csr_regout.ch1_trig_thres_val_o;
int_trig_thres(2) <= csr_regout.ch2_trig_thres_val_o;
int_trig_thres(3) <= csr_regout.ch3_trig_thres_val_o;
int_trig_thres(4) <= csr_regout.ch4_trig_thres_val_o;
trig_delay <= csr_regout.trig_dly_o;
int_trig_thres_hyst(1) <= csr_regout.ch1_trig_thres_hyst_o;
int_trig_thres_hyst(2) <= csr_regout.ch2_trig_thres_hyst_o;
int_trig_thres_hyst(3) <= csr_regout.ch3_trig_thres_hyst_o;
int_trig_thres_hyst(4) <= csr_regout.ch4_trig_thres_hyst_o;
sw_trig <= csr_regout.sw_trig_wr_o;
sw_trig_en <= csr_regout.trig_en_sw_o;
time_trig_en <= csr_regout.trig_en_time_o;
shots_value <= csr_regout.shots_nb_o;
undersample_factor <= csr_regout.sr_undersample_o;
pre_trig_value <= csr_regout.pre_samples_o;
......@@ -766,6 +775,42 @@ begin
ext_trig_n when '1',
'0' when others;
-- Configurable trigger delay, adds ext_trig_delay+1 clock cycles
-- to the trigger signal
p_ext_trig_delay_cnt : process(fs_clk, fs_rst_n)
begin
if fs_rst_n = '0' then
ext_trig_delay_cnt <= (others => '0');
elsif rising_edge(fs_clk) then
if ext_trig = '1' then
ext_trig_delay_cnt <= unsigned(ext_trig_delay);
elsif ext_trig_delay_cnt /= 0 then
ext_trig_delay_cnt <= ext_trig_delay_cnt - 1;
end if;
end if;
end process p_ext_trig_delay_cnt;
p_ext_trig_delay : process(fs_clk, fs_rst_n)
begin
if fs_rst_n = '0' then
ext_trig_d <= '0';
elsif rising_edge(fs_clk) then
if ext_trig_delay = X"00000000" then
if ext_trig = '1' then
ext_trig_d <= '1';
else
ext_trig_d <= '0';
end if;
else
if ext_trig_delay_cnt = X"00000001" then
ext_trig_d <= '1';
else
ext_trig_d <= '0';
end if;
end if;
end if;
end process p_ext_trig_delay;
-- Time trigger synchronization (from 125MHz timetag core)
cmp_time_trig_sync : gc_sync_ffs
port map (
......@@ -792,78 +837,105 @@ begin
inn_i => int_trig_thres(I),
hys_i => int_trig_thres_hyst(I),
out_o => open,
out_p_o => int_ch_trig(I));
out_p_o => int_trig(I));
-- Configurable trigger delay, adds int_trig_delay(I)+1 clock cycles
-- to the trigger signal
p_int_trig_delay_cnt : process(fs_clk, fs_rst_n)
begin
if fs_rst_n = '0' then
int_trig_delay_cnt(I) <= (others => '0');
elsif rising_edge(fs_clk) then
if int_trig(I) = '1' then
int_trig_delay_cnt(I) <= unsigned(int_trig_delay(I));
elsif int_trig_delay_cnt(I) /= 0 then
int_trig_delay_cnt(I) <= int_trig_delay_cnt(I) - 1;
end if;
end if;
end process p_int_trig_delay_cnt;
p_int_trig_delay : process(fs_clk, fs_rst_n)
begin
if fs_rst_n = '0' then
int_trig_d(I) <= '0';
elsif rising_edge(fs_clk) then
if int_trig_delay(I) = X"00000000" then
if int_trig(I) = '1' then
int_trig_d(I) <= '1';
else
int_trig_d(I) <= '0';
end if;
else
if int_trig_delay_cnt(I) = X"00000001" then
int_trig_d(I) <= '1';
else
int_trig_d(I) <= '0';
end if;
end if;
end if;
end process p_int_trig_delay;
end generate g_int_trig;
-- Internal triggers take one more cycle to propagate, so delay all other sources
-- to properly align everything with the acquired data.
p_trig_shift : process(fs_clk, fs_rst_n)
-- Due to the comparator, configurable trigger delay and trigger align logic,
-- internal threshold triggers are misaligned with respect to the incoming
-- data (triggers are late by 3 sampling clock cycles).
--
-- We solve this by delaying the sampled data by 3 clock cycles on-chip.
--
-- At the same time, all the other triggers (external, time and soft) are
-- also misaligned with respect to the incoming data (triggers arrive earlier
-- in these cases) because it takes more time to digitize the analogue signals
-- serialize them, transmit them, receive them in the FPGA, de-serialize, etc.
--
-- We solve this by introducing individual delays to the other triggers. In doing
-- so, we always add more to account for the 3 clock cycles data delays mentioned
-- before. Thus:
-- * EXT triggers are delayed by 8 (5+3) cycles
-- * TIME triggers are delayed by 5 (2+3) cycles TODO: confirm
-- * SOFT triggers are delayed by 5 (2+3) cycles TODO: confirm
p_data_shift : process (fs_clk)
begin
if fs_rst_n = '0' then
sw_trig_d <= '0';
ext_trig_d <= '0';
time_trig_d <= '0';
elsif rising_edge(fs_clk) then
sw_trig_d <= sw_trig;
ext_trig_d <= ext_trig;
time_trig_d <= time_trig;
if rising_edge(fs_clk) then
data_calibr_out_d1 <= data_calibr_out;
data_calibr_out_d2 <= data_calibr_out_d1;
data_calibr_out_d3 <= data_calibr_out_d2;
end if;
end process p_trig_shift;
end process p_data_shift;
-- Trigger sources ORing
trig <= (sw_trig_d and sw_trig_en) or
(ext_trig_d and ext_trig_en) or
(int_ch_trig(1) and int_trig_en(1)) or
(int_ch_trig(2) and int_trig_en(2)) or
(int_ch_trig(3) and int_trig_en(3)) or
(int_ch_trig(4) and int_trig_en(4)) or
(time_trig_d and time_trig_en);
-- Trigger delay
p_trig_delay_cnt : process(fs_clk, fs_rst_n)
p_trig_shift : process(fs_clk, fs_rst_n)
begin
if fs_rst_n = '0' then
trig_delay_cnt <= (others => '0');
sw_trig_fixed_delay <= (others => '0');
ext_trig_fixed_delay <= (others => '0');
time_trig_fixed_delay <= (others => '0');
elsif rising_edge(fs_clk) then
if trig = '1' then
trig_delay_cnt <= unsigned(trig_delay);
elsif trig_delay_cnt /= 0 then
trig_delay_cnt <= trig_delay_cnt - 1;
end if;
sw_trig_fixed_delay <= sw_trig_fixed_delay(sw_trig_fixed_delay'HIGH -1 downto 0) & sw_trig;
ext_trig_fixed_delay <= ext_trig_fixed_delay(ext_trig_fixed_delay'HIGH -1 downto 0) & ext_trig_d;
time_trig_fixed_delay <= time_trig_fixed_delay(time_trig_fixed_delay'HIGH -1 downto 0) & time_trig;
end if;
end process p_trig_delay_cnt;
end process p_trig_shift;
p_trig_delay : process(fs_clk, fs_rst_n)
begin
if fs_rst_n = '0' then
trig_d <= '0';
elsif rising_edge(fs_clk) then
if trig_delay = X"00000000" then
if trig = '1' then
trig_d <= '1';
else
trig_d <= '0';
end if;
else
if trig_delay_cnt = X"00000001" then
trig_d <= '1';
else
trig_d <= '0';
end if;
end if;
end if;
end process p_trig_delay;
-- Trigger sources ORing
trig <= (sw_trig_fixed_delay(sw_trig_fixed_delay'HIGH) and sw_trig_en) or
(ext_trig_fixed_delay(ext_trig_fixed_delay'HIGH) and ext_trig_en) or
(int_trig_d(1) and int_trig_en(1)) or
(int_trig_d(2) and int_trig_en(2)) or
(int_trig_d(3) and int_trig_en(3)) or
(int_trig_d(4) and int_trig_en(4)) or
(time_trig_fixed_delay(time_trig_fixed_delay'HIGH) and time_trig_en);
------------------------------------------------------------------------------
-- Trigger storage and synchronisation to system clock domain
-- Trigger source storage and synchronisation to system clock domain
------------------------------------------------------------------------------
trig_fifo_din <= trig & X"00000" &
int_ch_trig(4) & int_ch_trig(3) &
int_ch_trig(2) & int_ch_trig(1) &
"000" & time_trig_d &
"00" & sw_trig_d & ext_trig_d;
int_trig_d(4) & int_trig_d(3) &
int_trig_d(2) & int_trig_d(1) &
"000" & time_trig_fixed_delay(time_trig_fixed_delay'HIGH) &
"00" & sw_trig_fixed_delay(sw_trig_fixed_delay'HIGH) &
ext_trig_fixed_delay(ext_trig_fixed_delay'HIGH);
trig_fifo_wr <= not trig_fifo_full;
......@@ -946,7 +1018,7 @@ begin
if fs_rst_n = '0' then
trig_align <= '0';
elsif rising_edge(fs_clk) then
if trig_d = '1' then
if trig = '1' then
trig_align <= '1';
elsif undersample_en = '1' then
trig_align <= '0';
......@@ -1008,16 +1080,6 @@ begin
end if;
end process;
-- Delay data to compensate for trigger processing
p_data_delay : process (fs_clk)
begin
if rising_edge(fs_clk) then
data_calibr_out_d1 <= data_calibr_out;
data_calibr_out_d2 <= data_calibr_out_d1;
data_calibr_out_d3 <= data_calibr_out_d2;
end if;
end process p_data_delay;
-- Data to FIFO
sync_fifo_din(64) <= trig_align;
sync_fifo_din(63 downto 0) <= data_calibr_out_d3;
......
hdl/adc/rtl/fmc_adc_100Ms_csr.vhd
View file @ b7fbece5
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/fmc_adc_100Ms_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Created : Thu Jan 25 09:51:59 2018
-- Created : Fri Jan 26 15:37:35 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -84,7 +84,7 @@ signal fmc_adc_100ms_csr_trig_pol_ch3_sync1 : std_logic ;
signal fmc_adc_100ms_csr_trig_pol_ch4_int : std_logic ;
signal fmc_adc_100ms_csr_trig_pol_ch4_sync0 : std_logic ;
signal fmc_adc_100ms_csr_trig_pol_ch4_sync1 : std_logic ;
signal fmc_adc_100ms_csr_trig_dly_int : std_logic_vector(31 downto 0);
signal fmc_adc_100ms_csr_ext_trig_dly_int : std_logic_vector(31 downto 0);
signal fmc_adc_100ms_csr_sw_trig_wr_int : std_logic ;
signal fmc_adc_100ms_csr_sw_trig_wr_int_delay : std_logic ;
signal fmc_adc_100ms_csr_sw_trig_wr_sync0 : std_logic ;
......@@ -129,6 +129,7 @@ signal fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_delay : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_s0 : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_s1 : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_s2 : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_dly_int : std_logic_vector(31 downto 0);
signal fmc_adc_100ms_csr_ch2_ctl_ssr_int : std_logic_vector(6 downto 0);
signal fmc_adc_100ms_csr_ch2_sta_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch2_sta_val_lwb : std_logic ;
......@@ -152,6 +153,7 @@ signal fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_delay : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_s0 : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_s1 : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_s2 : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_dly_int : std_logic_vector(31 downto 0);
signal fmc_adc_100ms_csr_ch3_ctl_ssr_int : std_logic_vector(6 downto 0);
signal fmc_adc_100ms_csr_ch3_sta_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch3_sta_val_lwb : std_logic ;
......@@ -175,6 +177,7 @@ signal fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_delay : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_s0 : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_s1 : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_s2 : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_dly_int : std_logic_vector(31 downto 0);
signal fmc_adc_100ms_csr_ch4_ctl_ssr_int : std_logic_vector(6 downto 0);
signal fmc_adc_100ms_csr_ch4_sta_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch4_sta_val_lwb : std_logic ;
......@@ -198,6 +201,7 @@ signal fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_delay : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_s0 : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_s1 : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_s2 : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_dly_int : std_logic_vector(31 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
......@@ -235,7 +239,7 @@ begin
fmc_adc_100ms_csr_trig_pol_ch2_int <= '0';
fmc_adc_100ms_csr_trig_pol_ch3_int <= '0';
fmc_adc_100ms_csr_trig_pol_ch4_int <= '0';
fmc_adc_100ms_csr_trig_dly_int <= "00000000000000000000000000000000";
fmc_adc_100ms_csr_ext_trig_dly_int <= "00000000000000000000000000000000";
fmc_adc_100ms_csr_sw_trig_wr_int <= '0';
fmc_adc_100ms_csr_sw_trig_wr_int_delay <= '0';
fmc_adc_100ms_csr_shots_nb_int <= "0000000000000000";
......@@ -260,6 +264,7 @@ begin
fmc_adc_100ms_csr_ch1_trig_thres_hyst_int <= "0000000000000000";
fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb <= '0';
fmc_adc_100ms_csr_ch1_trig_thres_hyst_swb_delay <= '0';
fmc_adc_100ms_csr_ch1_trig_dly_int <= "00000000000000000000000000000000";
fmc_adc_100ms_csr_ch2_ctl_ssr_int <= "0000000";
fmc_adc_100ms_csr_ch2_sta_val_lwb <= '0';
fmc_adc_100ms_csr_ch2_sta_val_lwb_delay <= '0';
......@@ -273,6 +278,7 @@ begin
fmc_adc_100ms_csr_ch2_trig_thres_hyst_int <= "0000000000000000";
fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb <= '0';
fmc_adc_100ms_csr_ch2_trig_thres_hyst_swb_delay <= '0';
fmc_adc_100ms_csr_ch2_trig_dly_int <= "00000000000000000000000000000000";
fmc_adc_100ms_csr_ch3_ctl_ssr_int <= "0000000";
fmc_adc_100ms_csr_ch3_sta_val_lwb <= '0';
fmc_adc_100ms_csr_ch3_sta_val_lwb_delay <= '0';
......@@ -286,6 +292,7 @@ begin
fmc_adc_100ms_csr_ch3_trig_thres_hyst_int <= "0000000000000000";
fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb <= '0';
fmc_adc_100ms_csr_ch3_trig_thres_hyst_swb_delay <= '0';
fmc_adc_100ms_csr_ch3_trig_dly_int <= "00000000000000000000000000000000";
fmc_adc_100ms_csr_ch4_ctl_ssr_int <= "0000000";
fmc_adc_100ms_csr_ch4_sta_val_lwb <= '0';
fmc_adc_100ms_csr_ch4_sta_val_lwb_delay <= '0';
......@@ -299,6 +306,7 @@ begin
fmc_adc_100ms_csr_ch4_trig_thres_hyst_int <= "0000000000000000";
fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb <= '0';
fmc_adc_100ms_csr_ch4_trig_thres_hyst_swb_delay <= '0';
fmc_adc_100ms_csr_ch4_trig_dly_int <= "00000000000000000000000000000000";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
......@@ -570,9 +578,9 @@ begin
ack_in_progress <= '1';
when "00000101" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_trig_dly_int <= wrdata_reg(31 downto 0);
fmc_adc_100ms_csr_ext_trig_dly_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= fmc_adc_100ms_csr_trig_dly_int;
rddata_reg(31 downto 0) <= fmc_adc_100ms_csr_ext_trig_dly_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00000110" =>
......@@ -851,6 +859,13 @@ begin
rddata_reg(31 downto 16) <= fmc_adc_100ms_csr_ch1_trig_thres_hyst_int;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "00100110" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch1_trig_dly_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= fmc_adc_100ms_csr_ch1_trig_dly_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000000" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch2_ctl_ssr_int <= wrdata_reg(6 downto 0);
......@@ -992,6 +1007,13 @@ begin
rddata_reg(31 downto 16) <= fmc_adc_100ms_csr_ch2_trig_thres_hyst_int;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "01000110" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch2_trig_dly_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= fmc_adc_100ms_csr_ch2_trig_dly_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100000" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch3_ctl_ssr_int <= wrdata_reg(6 downto 0);
......@@ -1133,6 +1155,13 @@ begin
rddata_reg(31 downto 16) <= fmc_adc_100ms_csr_ch3_trig_thres_hyst_int;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "01100110" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch3_trig_dly_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= fmc_adc_100ms_csr_ch3_trig_dly_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000000" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch4_ctl_ssr_int <= wrdata_reg(6 downto 0);
......@@ -1274,6 +1303,13 @@ begin
rddata_reg(31 downto 16) <= fmc_adc_100ms_csr_ch4_trig_thres_hyst_int;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "10000110" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch4_trig_dly_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= fmc_adc_100ms_csr_ch4_trig_dly_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
......@@ -1520,8 +1556,8 @@ begin
end process;
-- Trigger delay value
regs_o.trig_dly_o <= fmc_adc_100ms_csr_trig_dly_int;
-- External trigger delay value
regs_o.ext_trig_dly_o <= fmc_adc_100ms_csr_ext_trig_dly_int;
-- Software trigger (ignore on read)
-- pass-through field: Software trigger (ignore on read) in register: Software trigger
regs_o.sw_trig_o <= wrdata_reg(31 downto 0);
......@@ -1658,6 +1694,8 @@ begin
end process;
-- Channel 1 trigger delay value
regs_o.ch1_trig_dly_o <= fmc_adc_100ms_csr_ch1_trig_dly_int;
-- Solid state relays control for channel 2
regs_o.ch2_ctl_ssr_o <= fmc_adc_100ms_csr_ch2_ctl_ssr_int;
-- Channel 2 current ACD value
......@@ -1726,6 +1764,8 @@ begin
end process;
-- Channel 2 trigger delay value
regs_o.ch2_trig_dly_o <= fmc_adc_100ms_csr_ch2_trig_dly_int;
-- Solid state relays control for channel 3
regs_o.ch3_ctl_ssr_o <= fmc_adc_100ms_csr_ch3_ctl_ssr_int;
-- Channel 3 current ADC value
......@@ -1794,6 +1834,8 @@ begin
end process;
-- Channel 3 trigger delay value
regs_o.ch3_trig_dly_o <= fmc_adc_100ms_csr_ch3_trig_dly_int;
-- Solid state relays control for channel 4
regs_o.ch4_ctl_ssr_o <= fmc_adc_100ms_csr_ch4_ctl_ssr_int;
-- Channel 4 current ADC value
......@@ -1862,6 +1904,8 @@ begin
end process;
-- Channel 4 trigger delay value
regs_o.ch4_trig_dly_o <= fmc_adc_100ms_csr_ch4_trig_dly_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
......
hdl/adc/rtl/fmc_adc_100Ms_csr_wbgen2_pkg.vhd
View file @ b7fbece5
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/fmc_adc_100Ms_csr_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Created : Thu Jan 25 09:51:59 2018
-- Created : Fri Jan 26 15:37:35 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -88,7 +88,7 @@ package fmc_adc_100ms_csr_wbgen2_pkg is
trig_pol_ch2_o : std_logic;
trig_pol_ch3_o : std_logic;
trig_pol_ch4_o : std_logic;
trig_dly_o : std_logic_vector(31 downto 0);
ext_trig_dly_o : std_logic_vector(31 downto 0);
sw_trig_o : std_logic_vector(31 downto 0);
sw_trig_wr_o : std_logic;
shots_nb_o : std_logic_vector(15 downto 0);
......@@ -101,24 +101,28 @@ package fmc_adc_100ms_csr_wbgen2_pkg is
ch1_sat_val_o : std_logic_vector(14 downto 0);
ch1_trig_thres_val_o : std_logic_vector(15 downto 0);
ch1_trig_thres_hyst_o : std_logic_vector(15 downto 0);
ch1_trig_dly_o : std_logic_vector(31 downto 0);
ch2_ctl_ssr_o : std_logic_vector(6 downto 0);
ch2_gain_val_o : std_logic_vector(15 downto 0);
ch2_offset_val_o : std_logic_vector(15 downto 0);
ch2_sat_val_o : std_logic_vector(14 downto 0);
ch2_trig_thres_val_o : std_logic_vector(15 downto 0);
ch2_trig_thres_hyst_o : std_logic_vector(15 downto 0);
ch2_trig_dly_o : std_logic_vector(31 downto 0);
ch3_ctl_ssr_o : std_logic_vector(6 downto 0);
ch3_gain_val_o : std_logic_vector(15 downto 0);
ch3_offset_val_o : std_logic_vector(15 downto 0);
ch3_sat_val_o : std_logic_vector(14 downto 0);
ch3_trig_thres_val_o : std_logic_vector(15 downto 0);
ch3_trig_thres_hyst_o : std_logic_vector(15 downto 0);
ch3_trig_dly_o : std_logic_vector(31 downto 0);
ch4_ctl_ssr_o : std_logic_vector(6 downto 0);
ch4_gain_val_o : std_logic_vector(15 downto 0);
ch4_offset_val_o : std_logic_vector(15 downto 0);
ch4_sat_val_o : std_logic_vector(14 downto 0);
ch4_trig_thres_val_o : std_logic_vector(15 downto 0);
ch4_trig_thres_hyst_o : std_logic_vector(15 downto 0);
ch4_trig_dly_o : std_logic_vector(31 downto 0);
end record;
constant c_fmc_adc_100ms_csr_out_registers_init_value: t_fmc_adc_100ms_csr_out_registers := (
......@@ -142,7 +146,7 @@ package fmc_adc_100ms_csr_wbgen2_pkg is
trig_pol_ch2_o => '0',
trig_pol_ch3_o => '0',
trig_pol_ch4_o => '0',
trig_dly_o => (others => '0'),
ext_trig_dly_o => (others => '0'),
sw_trig_o => (others => '0'),
sw_trig_wr_o => '0',
shots_nb_o => (others => '0'),
......@@ -155,24 +159,28 @@ package fmc_adc_100ms_csr_wbgen2_pkg is
ch1_sat_val_o => (others => '0'),
ch1_trig_thres_val_o => (others => '0'),
ch1_trig_thres_hyst_o => (others => '0'),
ch1_trig_dly_o => (others => '0'),
ch2_ctl_ssr_o => (others => '0'),
ch2_gain_val_o => (others => '0'),
ch2_offset_val_o => (others => '0'),
ch2_sat_val_o => (others => '0'),
ch2_trig_thres_val_o => (others => '0'),
ch2_trig_thres_hyst_o => (others => '0'),
ch2_trig_dly_o => (others => '0'),
ch3_ctl_ssr_o => (others => '0'),
ch3_gain_val_o => (others => '0'),
ch3_offset_val_o => (others => '0'),
ch3_sat_val_o => (others => '0'),
ch3_trig_thres_val_o => (others => '0'),
ch3_trig_thres_hyst_o => (others => '0'),
ch3_trig_dly_o => (others => '0'),
ch4_ctl_ssr_o => (others => '0'),
ch4_gain_val_o => (others => '0'),
ch4_offset_val_o => (others => '0'),
ch4_sat_val_o => (others => '0'),
ch4_trig_thres_val_o => (others => '0'),
ch4_trig_thres_hyst_o => (others => '0')
ch4_trig_thres_hyst_o => (others => '0'),
ch4_trig_dly_o => (others => '0')
);
function "or" (left, right: t_fmc_adc_100ms_csr_in_registers) return t_fmc_adc_100ms_csr_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
......
hdl/adc/wb_gen/fmc_adc_100Ms_csr.h
View file @ b7fbece5
......@@ -3,7 +3,7 @@
* File : fmc_adc_100Ms_csr.h
* Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
* Created : Thu Jan 25 09:52:00 2018
* Created : Fri Jan 26 15:37:35 2018
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -141,7 +141,7 @@
/* definitions for field: Channel 4 internal threshold trigger in reg: Trigger polarity */
#define FMC_ADC_100MS_CSR_TRIG_POL_CH4 WBGEN2_GEN_MASK(11, 1)
/* definitions for register: Trigger delay */
/* definitions for register: External trigger delay */
/* definitions for register: Software trigger */
......@@ -235,6 +235,8 @@
#define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_HYST_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_HYST_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 1 trigger delay */
/* definitions for register: Channel 2 control register */
/* definitions for field: Solid state relays control for channel 2 in reg: Channel 2 control register */
......@@ -289,6 +291,8 @@
#define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_HYST_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_HYST_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 2 trigger delay */
/* definitions for register: Channel 3 control register */
/* definitions for field: Solid state relays control for channel 3 in reg: Channel 3 control register */
......@@ -343,6 +347,8 @@
#define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_HYST_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_HYST_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 3 trigger delay */
/* definitions for register: Channel 4 control register */
/* definitions for field: Solid state relays control for channel 4 in reg: Channel 4 control register */
......@@ -397,6 +403,8 @@
#define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_HYST_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_HYST_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 4 trigger delay */
PACKED struct FMC_ADC_100MS_CSR_WB {
/* [0x0]: REG Control register */
uint32_t CTL;
......@@ -408,8 +416,8 @@ PACKED struct FMC_ADC_100MS_CSR_WB {
uint32_t TRIG_EN;
/* [0x10]: REG Trigger polarity */
uint32_t TRIG_POL;
/* [0x14]: REG Trigger delay */
uint32_t TRIG_DLY;
/* [0x14]: REG External trigger delay */
uint32_t EXT_TRIG_DLY;
/* [0x18]: REG Software trigger */
uint32_t SW_TRIG;
/* [0x1c]: REG Number of shots */
......@@ -444,8 +452,10 @@ PACKED struct FMC_ADC_100MS_CSR_WB {
uint32_t CH1_SAT;
/* [0x94]: REG Channel 1 trigger threshold configuration register */
uint32_t CH1_TRIG_THRES;
/* [0x98]: REG Channel 1 trigger delay */
uint32_t CH1_TRIG_DLY;
/* padding to: 64 words */
uint32_t __padding_1[26];
uint32_t __padding_1[25];
/* [0x100]: REG Channel 2 control register */
uint32_t CH2_CTL;
/* [0x104]: REG Channel 2 status register */
......@@ -458,8 +468,10 @@ PACKED struct FMC_ADC_100MS_CSR_WB {
uint32_t CH2_SAT;
/* [0x114]: REG Channel 2 trigger threshold configuration register */
uint32_t CH2_TRIG_THRES;
/* [0x118]: REG Channel 2 trigger delay */
uint32_t CH2_TRIG_DLY;
/* padding to: 96 words */
uint32_t __padding_2[26];
uint32_t __padding_2[25];
/* [0x180]: REG Channel 3 control register */
uint32_t CH3_CTL;
/* [0x184]: REG Channel 3 status register */
......@@ -472,8 +484,10 @@ PACKED struct FMC_ADC_100MS_CSR_WB {
uint32_t CH3_SAT;
/* [0x194]: REG Channel 3 trigger threshold configuration register */
uint32_t CH3_TRIG_THRES;
/* [0x198]: REG Channel 3 trigger delay */
uint32_t CH3_TRIG_DLY;
/* padding to: 128 words */
uint32_t __padding_3[26];
uint32_t __padding_3[25];
/* [0x200]: REG Channel 4 control register */
uint32_t CH4_CTL;
/* [0x204]: REG Channel 4 status register */
......@@ -486,6 +500,8 @@ PACKED struct FMC_ADC_100MS_CSR_WB {
uint32_t CH4_SAT;
/* [0x214]: REG Channel 4 trigger threshold configuration register */
uint32_t CH4_TRIG_THRES;
/* [0x218]: REG Channel 4 trigger delay */
uint32_t CH4_TRIG_DLY;
};
#endif
hdl/adc/wb_gen/fmc_adc_100Ms_csr.htm
View file @ b7fbece5
......@@ -39,7 +39,7 @@
<span style="margin-left: 20px; ">3.3. <A href="#sect_3_3">Trigger status</a></span><br/>
<span style="margin-left: 20px; ">3.4. <A href="#sect_3_4">Trigger enable</a></span><br/>
<span style="margin-left: 20px; ">3.5. <A href="#sect_3_5">Trigger polarity</a></span><br/>
<span style="margin-left: 20px; ">3.6. <A href="#sect_3_6">Trigger delay</a></span><br/>
<span style="margin-left: 20px; ">3.6. <A href="#sect_3_6">External trigger delay</a></span><br/>
<span style="margin-left: 20px; ">3.7. <A href="#sect_3_7">Software trigger</a></span><br/>
<span style="margin-left: 20px; ">3.8. <A href="#sect_3_8">Number of shots</a></span><br/>
<span style="margin-left: 20px; ">3.9. <A href="#sect_3_9">Multi-shot sample depth register</a></span><br/>
......@@ -56,24 +56,28 @@
<span style="margin-left: 20px; ">3.20. <A href="#sect_3_20">Channel 1 offset calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.21. <A href="#sect_3_21">Channel 1 saturation register</a></span><br/>
<span style="margin-left: 20px; ">3.22. <A href="#sect_3_22">Channel 1 trigger threshold configuration register</a></span><br/>
<span style="margin-left: 20px; ">3.23. <A href="#sect_3_23">Channel 2 control register</a></span><br/>
<span style="margin-left: 20px; ">3.24. <A href="#sect_3_24">Channel 2 status register</a></span><br/>
<span style="margin-left: 20px; ">3.25. <A href="#sect_3_25">Channel 2 gain calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.26. <A href="#sect_3_26">Channel 2 offset calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.27. <A href="#sect_3_27">Channel 2 saturation register</a></span><br/>
<span style="margin-left: 20px; ">3.28. <A href="#sect_3_28">Channel 2 trigger threshold configuration register</a></span><br/>
<span style="margin-left: 20px; ">3.29. <A href="#sect_3_29">Channel 3 control register</a></span><br/>
<span style="margin-left: 20px; ">3.30. <A href="#sect_3_30">Channel 3 status register</a></span><br/>
<span style="margin-left: 20px; ">3.31. <A href="#sect_3_31">Channel 3 gain calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.32. <A href="#sect_3_32">Channel 3 offset calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.33. <A href="#sect_3_33">Channel 3 saturation register</a></span><br/>
<span style="margin-left: 20px; ">3.34. <A href="#sect_3_34">Channel 3 trigger threshold configuration register</a></span><br/>
<span style="margin-left: 20px; ">3.35. <A href="#sect_3_35">Channel 4 control register</a></span><br/>
<span style="margin-left: 20px; ">3.36. <A href="#sect_3_36">Channel 4 status register</a></span><br/>
<span style="margin-left: 20px; ">3.37. <A href="#sect_3_37">Channel 4 gain calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.38. <A href="#sect_3_38">Channel 4 offset calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.39. <A href="#sect_3_39">Channel 4 saturation register</a></span><br/>
<span style="margin-left: 20px; ">3.40. <A href="#sect_3_40">Channel 4 trigger threshold configuration register</a></span><br/>
<span style="margin-left: 20px; ">3.23. <A href="#sect_3_23">Channel 1 trigger delay</a></span><br/>
<span style="margin-left: 20px; ">3.24. <A href="#sect_3_24">Channel 2 control register</a></span><br/>
<span style="margin-left: 20px; ">3.25. <A href="#sect_3_25">Channel 2 status register</a></span><br/>
<span style="margin-left: 20px; ">3.26. <A href="#sect_3_26">Channel 2 gain calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.27. <A href="#sect_3_27">Channel 2 offset calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.28. <A href="#sect_3_28">Channel 2 saturation register</a></span><br/>
<span style="margin-left: 20px; ">3.29. <A href="#sect_3_29">Channel 2 trigger threshold configuration register</a></span><br/>
<span style="margin-left: 20px; ">3.30. <A href="#sect_3_30">Channel 2 trigger delay</a></span><br/>
<span style="margin-left: 20px; ">3.31. <A href="#sect_3_31">Channel 3 control register</a></span><br/>
<span style="margin-left: 20px; ">3.32. <A href="#sect_3_32">Channel 3 status register</a></span><br/>
<span style="margin-left: 20px; ">3.33. <A href="#sect_3_33">Channel 3 gain calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.34. <A href="#sect_3_34">Channel 3 offset calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.35. <A href="#sect_3_35">Channel 3 saturation register</a></span><br/>
<span style="margin-left: 20px; ">3.36. <A href="#sect_3_36">Channel 3 trigger threshold configuration register</a></span><br/>
<span style="margin-left: 20px; ">3.37. <A href="#sect_3_37">Channel 3 trigger delay</a></span><br/>
<span style="margin-left: 20px; ">3.38. <A href="#sect_3_38">Channel 4 control register</a></span><br/>
<span style="margin-left: 20px; ">3.39. <A href="#sect_3_39">Channel 4 status register</a></span><br/>
<span style="margin-left: 20px; ">3.40. <A href="#sect_3_40">Channel 4 gain calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.41. <A href="#sect_3_41">Channel 4 offset calibration register</a></span><br/>
<span style="margin-left: 20px; ">3.42. <A href="#sect_3_42">Channel 4 saturation register</a></span><br/>
<span style="margin-left: 20px; ">3.43. <A href="#sect_3_43">Channel 4 trigger threshold configuration register</a></span><br/>
<span style="margin-left: 20px; ">3.44. <A href="#sect_3_44">Channel 4 trigger delay</a></span><br/>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -186,13 +190,13 @@ TRIG_POL
REG
</td>
<td >
<A href="#TRIG_DLY">Trigger delay</a>
<A href="#EXT_TRIG_DLY">External trigger delay</a>
</td>
<td class="td_code">
fmc_adc_100ms_csr_trig_dly
fmc_adc_100ms_csr_ext_trig_dly
</td>
<td class="td_code">
TRIG_DLY
EXT_TRIG_DLY
</td>
</tr>
<tr class="tr_odd">
......@@ -469,6 +473,23 @@ CH1_TRIG_THRES
</tr>
<tr class="tr_odd">
<td class="td_code">
0x26
</td>
<td >
REG
</td>
<td >
<A href="#CH1_TRIG_DLY">Channel 1 trigger delay</a>
</td>
<td class="td_code">
fmc_adc_100ms_csr_ch1_trig_dly
</td>
<td class="td_code">
CH1_TRIG_DLY
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x40
</td>
<td >
......@@ -484,7 +505,7 @@ fmc_adc_100ms_csr_ch2_ctl
CH2_CTL
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x41
</td>
......@@ -501,7 +522,7 @@ fmc_adc_100ms_csr_ch2_sta
CH2_STA
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x42
</td>
......@@ -518,7 +539,7 @@ fmc_adc_100ms_csr_ch2_gain
CH2_GAIN
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x43
</td>
......@@ -535,7 +556,7 @@ fmc_adc_100ms_csr_ch2_offset
CH2_OFFSET
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x44
</td>
......@@ -552,7 +573,7 @@ fmc_adc_100ms_csr_ch2_sat
CH2_SAT
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x45
</td>
......@@ -569,6 +590,23 @@ fmc_adc_100ms_csr_ch2_trig_thres
CH2_TRIG_THRES
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x46
</td>
<td >
REG
</td>
<td >
<A href="#CH2_TRIG_DLY">Channel 2 trigger delay</a>
</td>
<td class="td_code">
fmc_adc_100ms_csr_ch2_trig_dly
</td>
<td class="td_code">
CH2_TRIG_DLY
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x60
......@@ -673,6 +711,23 @@ CH3_TRIG_THRES
</tr>
<tr class="tr_odd">
<td class="td_code">
0x66
</td>
<td >
REG
</td>
<td >
<A href="#CH3_TRIG_DLY">Channel 3 trigger delay</a>
</td>
<td class="td_code">
fmc_adc_100ms_csr_ch3_trig_dly
</td>
<td class="td_code">
CH3_TRIG_DLY
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x80
</td>
<td >
......@@ -688,7 +743,7 @@ fmc_adc_100ms_csr_ch4_ctl
CH4_CTL
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x81
</td>
......@@ -705,7 +760,7 @@ fmc_adc_100ms_csr_ch4_sta
CH4_STA
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x82
</td>
......@@ -722,7 +777,7 @@ fmc_adc_100ms_csr_ch4_gain
CH4_GAIN
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x83
</td>
......@@ -739,7 +794,7 @@ fmc_adc_100ms_csr_ch4_offset
CH4_OFFSET
</td>
</tr>
<tr class="tr_odd">
<tr class="tr_even">
<td class="td_code">
0x84
</td>
......@@ -756,7 +811,7 @@ fmc_adc_100ms_csr_ch4_sat
CH4_SAT
</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">
0x85
</td>
......@@ -773,6 +828,23 @@ fmc_adc_100ms_csr_ch4_trig_thres
CH4_TRIG_THRES
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x86
</td>
<td >
REG
</td>
<td >
<A href="#CH4_TRIG_DLY">Channel 4 trigger delay</a>
</td>
<td class="td_code">
fmc_adc_100ms_csr_ch4_trig_dly
</td>
<td class="td_code">
CH4_TRIG_DLY
</td>
</tr>
</table>
<h3><a name="sect_2_0">2. HDL symbol</a></h3>
......@@ -1485,7 +1557,7 @@ fmc_adc_100ms_csr_trig_pol_ch4_o
</td>
<td class="td_pblock_right">
<b>Trigger delay:</b>
<b>External trigger delay:</b>
</td>
<td class="td_arrow_right">
......@@ -1502,7 +1574,7 @@ fmc_adc_100ms_csr_trig_pol_ch4_o
</td>
<td class="td_pblock_right">
fmc_adc_100ms_csr_trig_dly_o[31:0]
fmc_adc_100ms_csr_ext_trig_dly_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -2384,6 +2456,57 @@ fmc_adc_100ms_csr_ch1_trig_thres_hyst_o[15:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Channel 1 trigger delay:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_100ms_csr_ch1_trig_dly_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Channel 2 control register:</b>
......@@ -2707,6 +2830,57 @@ fmc_adc_100ms_csr_ch2_trig_thres_hyst_o[15:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Channel 2 trigger delay:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_100ms_csr_ch2_trig_dly_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Channel 3 control register:</b>
......@@ -3030,6 +3204,57 @@ fmc_adc_100ms_csr_ch3_trig_thres_hyst_o[15:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Channel 3 trigger delay:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_100ms_csr_ch3_trig_dly_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Channel 4 control register:</b>
......@@ -3327,39 +3552,90 @@ fmc_adc_100ms_csr_ch4_trig_thres_hyst_o[15:0]
&rArr;
</td>
</tr>
</table>
<h3><a name="sect_3_0">3. Register description</a></h3>
<a name="CTL"></a>
<h3><a name="sect_3_1">3.1. Control register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_100ms_csr_ctl
<td class="td_arrow_left">
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
<td class="td_pblock_left">
</td>
<td class="td_code">
0x0
<td class="td_sym_center">
&nbsp;
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
<td class="td_pblock_right">
</td>
<td class="td_code">
CTL
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Channel 4 trigger delay:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_100ms_csr_ch4_trig_dly_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
</table>
<h3><a name="sect_3_0">3. Register description</a></h3>
<a name="CTL"></a>
<h3><a name="sect_3_1">3.1. Control register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_100ms_csr_ctl
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x0
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
CTL
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x0
......@@ -4720,15 +4996,15 @@ CH4
</b>[<i>read/write</i>]: Channel 4 internal threshold trigger
<br>0: positive edge/slope<br>1: negative edge/slope
</ul>
<a name="TRIG_DLY"></a>
<h3><a name="sect_3_6">3.6. Trigger delay</a></h3>
<a name="EXT_TRIG_DLY"></a>
<h3><a name="sect_3_6">3.6. External trigger delay</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_100ms_csr_trig_dly
fmc_adc_100ms_csr_ext_trig_dly
</td>
</tr>
<tr>
......@@ -4744,7 +5020,7 @@ fmc_adc_100ms_csr_trig_dly
<b>C prefix: </b>
</td>
<td class="td_code">
TRIG_DLY
EXT_TRIG_DLY
</td>
</tr>
<tr>
......@@ -4785,7 +5061,7 @@ TRIG_DLY
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_DLY[31:24]
EXT_TRIG_DLY[31:24]
</td>
<td >
......@@ -4839,7 +5115,7 @@ TRIG_DLY[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_DLY[23:16]
EXT_TRIG_DLY[23:16]
</td>
<td >
......@@ -4893,7 +5169,7 @@ TRIG_DLY[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_DLY[15:8]
EXT_TRIG_DLY[15:8]
</td>
<td >
......@@ -4947,7 +5223,7 @@ TRIG_DLY[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_DLY[7:0]
EXT_TRIG_DLY[7:0]
</td>
<td >
......@@ -4974,8 +5250,8 @@ TRIG_DLY[7:0]
</table>
<ul>
<li><b>
TRIG_DLY
</b>[<i>read/write</i>]: Trigger delay value
EXT_TRIG_DLY
</b>[<i>read/write</i>]: External trigger delay value
<br>Delay to apply on the trigger in sampling clock period.<br>The default clock frequency is 100MHz (period = 10ns).
</ul>
<a name="SW_TRIG"></a>
......@@ -9112,15 +9388,15 @@ HYST
</b>[<i>read/write</i>]: Internal trigger threshold hysteresis
<br>Configures the internal trigger threshold hysteresis (two's complement).
</ul>
<a name="CH2_CTL"></a>
<h3><a name="sect_3_23">3.23. Channel 2 control register</a></h3>
<a name="CH1_TRIG_DLY"></a>
<h3><a name="sect_3_23">3.23. Channel 1 trigger delay</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_100ms_csr_ch2_ctl
fmc_adc_100ms_csr_ch1_trig_dly
</td>
</tr>
<tr>
......@@ -9128,7 +9404,7 @@ fmc_adc_100ms_csr_ch2_ctl
<b>HW address: </b>
</td>
<td class="td_code">
0x40
0x26
</td>
</tr>
<tr>
......@@ -9136,7 +9412,7 @@ fmc_adc_100ms_csr_ch2_ctl
<b>C prefix: </b>
</td>
<td class="td_code">
CH2_CTL
CH1_TRIG_DLY
</td>
</tr>
<tr>
......@@ -9144,7 +9420,7 @@ CH2_CTL
<b>C offset: </b>
</td>
<td class="td_code">
0x100
0x98
</td>
</tr>
</table>
......@@ -9176,29 +9452,29 @@ CH2_CTL
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH1_TRIG_DLY[31:24]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -9230,29 +9506,29 @@ CH2_CTL
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH1_TRIG_DLY[23:16]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -9284,29 +9560,29 @@ CH2_CTL
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH1_TRIG_DLY[15:8]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -9338,11 +9614,11 @@ CH2_CTL
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH1_TRIG_DLY[7:0]
</td>
<td style="border: solid 1px black;" colspan=7 class="td_field">
SSR[6:0]
<td >
</td>
<td >
......@@ -9366,19 +9642,19 @@ SSR[6:0]
</table>
<ul>
<li><b>
SSR
</b>[<i>read/write</i>]: Solid state relays control for channel 2
<br>Controls input voltage range, termination and DC offset error calibration<br>0x23: 100mV range<br>0x11: 1V range<br>0x45: 10V range<br>0x00: Open input<br>0x42: 100mV range calibration<br>0x40: 1V range calibration<br>0x44: 10V range calibration<br>Bit3 is indepandant of the others and enables the 50ohms termination.
CH1_TRIG_DLY
</b>[<i>read/write</i>]: Channel 1 trigger delay value
<br>Delay to apply on the trigger in sampling clock period.<br>The default clock frequency is 100MHz (period = 10ns).
</ul>
<a name="CH2_STA"></a>
<h3><a name="sect_3_24">3.24. Channel 2 status register</a></h3>
<a name="CH2_CTL"></a>
<h3><a name="sect_3_24">3.24. Channel 2 control register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_100ms_csr_ch2_sta
fmc_adc_100ms_csr_ch2_ctl
</td>
</tr>
<tr>
......@@ -9386,7 +9662,7 @@ fmc_adc_100ms_csr_ch2_sta
<b>HW address: </b>
</td>
<td class="td_code">
0x41
0x40
</td>
</tr>
<tr>
......@@ -9394,7 +9670,7 @@ fmc_adc_100ms_csr_ch2_sta
<b>C prefix: </b>
</td>
<td class="td_code">
CH2_STA
CH2_CTL
</td>
</tr>
<tr>
......@@ -9402,7 +9678,7 @@ CH2_STA
<b>C offset: </b>
</td>
<td class="td_code">
0x104
0x100
</td>
</tr>
</table>
......@@ -9542,29 +9818,29 @@ CH2_STA
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
VAL[15:8]
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
</tr>
</table>
......@@ -9596,11 +9872,11 @@ VAL[15:8]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
VAL[7:0]
<td class="td_unused">
-
</td>
<td >
<td style="border: solid 1px black;" colspan=7 class="td_field">
SSR[6:0]
</td>
<td >
......@@ -9624,19 +9900,19 @@ VAL[7:0]
</table>
<ul>
<li><b>
VAL
</b>[<i>read-only</i>]: Channel 2 current ACD value
<br>Current ADC raw value. The format is binary two's complement.
SSR
</b>[<i>read/write</i>]: Solid state relays control for channel 2
<br>Controls input voltage range, termination and DC offset error calibration<br>0x23: 100mV range<br>0x11: 1V range<br>0x45: 10V range<br>0x00: Open input<br>0x42: 100mV range calibration<br>0x40: 1V range calibration<br>0x44: 10V range calibration<br>Bit3 is indepandant of the others and enables the 50ohms termination.
</ul>
<a name="CH2_GAIN"></a>
<h3><a name="sect_3_25">3.25. Channel 2 gain calibration register</a></h3>
<a name="CH2_STA"></a>
<h3><a name="sect_3_25">3.25. Channel 2 status register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_100ms_csr_ch2_gain
fmc_adc_100ms_csr_ch2_sta
</td>
</tr>
<tr>
......@@ -9644,7 +9920,7 @@ fmc_adc_100ms_csr_ch2_gain
<b>HW address: </b>
</td>
<td class="td_code">
0x42
0x41
</td>
</tr>
<tr>
......@@ -9652,7 +9928,7 @@ fmc_adc_100ms_csr_ch2_gain
<b>C prefix: </b>
</td>
<td class="td_code">
CH2_GAIN
CH2_STA
</td>
</tr>
<tr>
......@@ -9660,7 +9936,7 @@ CH2_GAIN
<b>C offset: </b>
</td>
<td class="td_code">
0x108
0x104
</td>
</tr>
</table>
......@@ -9883,18 +10159,18 @@ VAL[7:0]
<ul>
<li><b>
VAL
</b>[<i>read/write</i>]: Gain calibration for channel 2
<br>Gain applied to all data coming from the ADC.<br>Fixed point format:<br>Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
</b>[<i>read-only</i>]: Channel 2 current ACD value
<br>Current ADC raw value. The format is binary two's complement.
</ul>
<a name="CH2_OFFSET"></a>
<h3><a name="sect_3_26">3.26. Channel 2 offset calibration register</a></h3>
<a name="CH2_GAIN"></a>
<h3><a name="sect_3_26">3.26. Channel 2 gain calibration register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_100ms_csr_ch2_offset
fmc_adc_100ms_csr_ch2_gain
</td>
</tr>
<tr>
......@@ -9902,7 +10178,7 @@ fmc_adc_100ms_csr_ch2_offset
<b>HW address: </b>
</td>
<td class="td_code">
0x43
0x42
</td>
</tr>
<tr>
......@@ -9910,7 +10186,7 @@ fmc_adc_100ms_csr_ch2_offset
<b>C prefix: </b>
</td>
<td class="td_code">
CH2_OFFSET
CH2_GAIN
</td>
</tr>
<tr>
......@@ -9918,7 +10194,7 @@ CH2_OFFSET
<b>C offset: </b>
</td>
<td class="td_code">
0x10c
0x108
</td>
</tr>
</table>
......@@ -10141,11 +10417,269 @@ VAL[7:0]
<ul>
<li><b>
VAL
</b>[<i>read/write</i>]: Offset calibration for channel 2
<br>Offset applied to all data coming from the ADC. The format is binary two's complement.
</b>[<i>read/write</i>]: Gain calibration for channel 2
<br>Gain applied to all data coming from the ADC.<br>Fixed point format:<br>Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
</ul>
<a name="CH2_SAT"></a>
<h3><a name="sect_3_27">3.27. Channel 2 saturation register</a></h3>
<a name="CH2_OFFSET"></a>
<h3><a name="sect_3_27">3.27. Channel 2 offset calibration register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_100ms_csr_ch2_offset
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x43
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
CH2_OFFSET
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x10c
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
VAL[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
VAL[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
VAL
</b>[<i>read/write</i>]: Offset calibration for channel 2
<br>Offset applied to all data coming from the ADC. The format is binary two's complement.
</ul>
<a name="CH2_SAT"></a>
<h3><a name="sect_3_28">3.28. Channel 2 saturation register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -10403,7 +10937,7 @@ VAL
<br>Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
</ul>
<a name="CH2_TRIG_THRES"></a>
<h3><a name="sect_3_28">3.28. Channel 2 trigger threshold configuration register</a></h3>
<h3><a name="sect_3_29">3.29. Channel 2 trigger threshold configuration register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -10664,8 +11198,266 @@ HYST
</b>[<i>read/write</i>]: Internal trigger threshold hysteresis
<br>Configures the internal trigger threshold hysteresis (two's complement).
</ul>
<a name="CH2_TRIG_DLY"></a>
<h3><a name="sect_3_30">3.30. Channel 2 trigger delay</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_100ms_csr_ch2_trig_dly
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x46
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
CH2_TRIG_DLY
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x118
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH2_TRIG_DLY[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH2_TRIG_DLY[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH2_TRIG_DLY[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH2_TRIG_DLY[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
CH2_TRIG_DLY
</b>[<i>read/write</i>]: Channel 2 trigger delay value
<br>Delay to apply on the trigger in sampling clock period.<br>The default clock frequency is 100MHz (period = 10ns).
</ul>
<a name="CH3_CTL"></a>
<h3><a name="sect_3_29">3.29. Channel 3 control register</a></h3>
<h3><a name="sect_3_31">3.31. Channel 3 control register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -10923,7 +11715,7 @@ SSR
<br>Controls input voltage range, termination and DC offset error calibration<br>0x23: 100mV range<br>0x11: 1V range<br>0x45: 10V range<br>0x00: Open input<br>0x42: 100mV range calibration<br>0x40: 1V range calibration<br>0x44: 10V range calibration<br>Bit3 is indepandant of the others and enables the 50ohms termination.
</ul>
<a name="CH3_STA"></a>
<h3><a name="sect_3_30">3.30. Channel 3 status register</a></h3>
<h3><a name="sect_3_32">3.32. Channel 3 status register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -11181,7 +11973,7 @@ VAL
<br>Current ADC raw value. The format is binary two's complement.
</ul>
<a name="CH3_GAIN"></a>
<h3><a name="sect_3_31">3.31. Channel 3 gain calibration register</a></h3>
<h3><a name="sect_3_33">3.33. Channel 3 gain calibration register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -11439,7 +12231,7 @@ VAL
<br>Gain applied to all data coming from the ADC.<br>Fixed point format:<br>Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
</ul>
<a name="CH3_OFFSET"></a>
<h3><a name="sect_3_32">3.32. Channel 3 offset calibration register</a></h3>
<h3><a name="sect_3_34">3.34. Channel 3 offset calibration register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -11697,7 +12489,7 @@ VAL
<br>Offset applied to all data coming from the ADC. The format is binary two's complement.
</ul>
<a name="CH3_SAT"></a>
<h3><a name="sect_3_33">3.33. Channel 3 saturation register</a></h3>
<h3><a name="sect_3_35">3.35. Channel 3 saturation register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -11955,7 +12747,7 @@ VAL
<br>Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
</ul>
<a name="CH3_TRIG_THRES"></a>
<h3><a name="sect_3_34">3.34. Channel 3 trigger threshold configuration register</a></h3>
<h3><a name="sect_3_36">3.36. Channel 3 trigger threshold configuration register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -12127,7 +12919,269 @@ HYST[7:0]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
VAL[15:8]
VAL[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
VAL[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
VAL
</b>[<i>read/write</i>]: Threshold for internal trigger
<br>Treated as binary two's complement and compared to raw ADC data.
<li><b>
HYST
</b>[<i>read/write</i>]: Internal trigger threshold hysteresis
<br>Configures the internal trigger threshold hysteresis (two's complement).
</ul>
<a name="CH3_TRIG_DLY"></a>
<h3><a name="sect_3_37">3.37. Channel 3 trigger delay</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_100ms_csr_ch3_trig_dly
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x66
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
CH3_TRIG_DLY
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x198
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH3_TRIG_DLY[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH3_TRIG_DLY[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH3_TRIG_DLY[15:8]
</td>
<td >
......@@ -12181,7 +13235,7 @@ VAL[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
VAL[7:0]
CH3_TRIG_DLY[7:0]
</td>
<td >
......@@ -12208,16 +13262,12 @@ VAL[7:0]
</table>
<ul>
<li><b>
VAL
</b>[<i>read/write</i>]: Threshold for internal trigger
<br>Treated as binary two's complement and compared to raw ADC data.
<li><b>
HYST
</b>[<i>read/write</i>]: Internal trigger threshold hysteresis
<br>Configures the internal trigger threshold hysteresis (two's complement).
CH3_TRIG_DLY
</b>[<i>read/write</i>]: Channel 3 trigger delay value
<br>Delay to apply on the trigger in sampling clock period.<br>The default clock frequency is 100MHz (period = 10ns).
</ul>
<a name="CH4_CTL"></a>
<h3><a name="sect_3_35">3.35. Channel 4 control register</a></h3>
<h3><a name="sect_3_38">3.38. Channel 4 control register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -12475,7 +13525,7 @@ SSR
<br>Controls input voltage range, termination and DC offset error calibration<br>0x23: 100mV range<br>0x11: 1V range<br>0x45: 10V range<br>0x00: Open input<br>0x42: 100mV range calibration<br>0x40: 1V range calibration<br>0x44: 10V range calibration<br>Bit3 is indepandant of the others and enables the 50ohms termination.
</ul>
<a name="CH4_STA"></a>
<h3><a name="sect_3_36">3.36. Channel 4 status register</a></h3>
<h3><a name="sect_3_39">3.39. Channel 4 status register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -12733,7 +13783,7 @@ VAL
<br>Current ADC raw value. The format is binary two's complement.
</ul>
<a name="CH4_GAIN"></a>
<h3><a name="sect_3_37">3.37. Channel 4 gain calibration register</a></h3>
<h3><a name="sect_3_40">3.40. Channel 4 gain calibration register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -12991,7 +14041,7 @@ VAL
<br>Gain applied to all data coming from the ADC.<br>Fixed point format:<br>Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
</ul>
<a name="CH4_OFFSET"></a>
<h3><a name="sect_3_38">3.38. Channel 4 offset calibration register</a></h3>
<h3><a name="sect_3_41">3.41. Channel 4 offset calibration register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -13249,7 +14299,7 @@ VAL
<br>Offset applied to all data coming from the ADC. The format is binary two's complement.
</ul>
<a name="CH4_SAT"></a>
<h3><a name="sect_3_39">3.39. Channel 4 saturation register</a></h3>
<h3><a name="sect_3_42">3.42. Channel 4 saturation register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -13507,7 +14557,7 @@ VAL
<br>Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
</ul>
<a name="CH4_TRIG_THRES"></a>
<h3><a name="sect_3_40">3.40. Channel 4 trigger threshold configuration register</a></h3>
<h3><a name="sect_3_43">3.43. Channel 4 trigger threshold configuration register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
......@@ -13768,6 +14818,264 @@ HYST
</b>[<i>read/write</i>]: Internal trigger threshold hysteresis
<br>Configures the internal trigger threshold hysteresis (two's complement).
</ul>
<a name="CH4_TRIG_DLY"></a>
<h3><a name="sect_3_44">3.44. Channel 4 trigger delay</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_adc_100ms_csr_ch4_trig_dly
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x86
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
CH4_TRIG_DLY
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x218
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH4_TRIG_DLY[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH4_TRIG_DLY[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH4_TRIG_DLY[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
CH4_TRIG_DLY[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
CH4_TRIG_DLY
</b>[<i>read/write</i>]: Channel 4 trigger delay value
<br>Delay to apply on the trigger in sampling clock period.<br>The default clock frequency is 100MHz (period = 10ns).
</ul>
......
hdl/adc/wb_gen/fmc_adc_100Ms_csr.wb
View file @ b7fbece5
......@@ -368,11 +368,11 @@ peripheral {
};
reg {
name = "Trigger delay";
prefix = "trig_dly";
name = "External trigger delay";
prefix = "ext_trig_dly";
field {
name = "Trigger delay value";
name = "External trigger delay value";
description = "Delay to apply on the trigger in sampling clock period.\nThe default clock frequency is 100MHz (period = 10ns).";
type = SLV;
size = 32;
......@@ -707,6 +707,20 @@ peripheral {
};
};
reg {
name = "Channel 1 trigger delay";
prefix = "ch1_trig_dly";
field {
name = "Channel 1 trigger delay value";
description = "Delay to apply on the trigger in sampling clock period.\nThe default clock frequency is 100MHz (period = 10ns).";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 2 control register";
prefix = "ch2_ctl";
......@@ -867,6 +881,20 @@ peripheral {
};
};
reg {
name = "Channel 2 trigger delay";
prefix = "ch2_trig_dly";
field {
name = "Channel 2 trigger delay value";
description = "Delay to apply on the trigger in sampling clock period.\nThe default clock frequency is 100MHz (period = 10ns).";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 3 control register";
prefix = "ch3_ctl";
......@@ -1027,6 +1055,20 @@ peripheral {
};
};
reg {
name = "Channel 3 trigger delay";
prefix = "ch3_trig_dly";
field {
name = "Channel 3 trigger delay value";
description = "Delay to apply on the trigger in sampling clock period.\nThe default clock frequency is 100MHz (period = 10ns).";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 4 control register";
prefix = "ch4_ctl";
......@@ -1187,4 +1229,18 @@ peripheral {
};
};
reg {
name = "Channel 4 trigger delay";
prefix = "ch4_trig_dly";
field {
name = "Channel 4 trigger delay value";
description = "Delay to apply on the trigger in sampling clock period.\nThe default clock frequency is 100MHz (period = 10ns).";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
hdl/spec/testbench/include/fmc_adc_100Ms_csr.v
View file @ b7fbece5
......@@ -63,7 +63,7 @@
`define FMC_ADC_100MS_CSR_TRIG_POL_CH3 32'h00000400
`define FMC_ADC_100MS_CSR_TRIG_POL_CH4_OFFSET 11
`define FMC_ADC_100MS_CSR_TRIG_POL_CH4 32'h00000800
`define ADDR_FMC_ADC_100MS_CSR_TRIG_DLY 10'h14
`define ADDR_FMC_ADC_100MS_CSR_EXT_TRIG_DLY 10'h14
`define ADDR_FMC_ADC_100MS_CSR_SW_TRIG 10'h18
`define ADDR_FMC_ADC_100MS_CSR_SHOTS 10'h1c
`define FMC_ADC_100MS_CSR_SHOTS_NB_OFFSET 0
......@@ -100,6 +100,7 @@
`define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_VAL 32'h0000ffff
`define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_HYST_OFFSET 16
`define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_HYST 32'hffff0000
`define ADDR_FMC_ADC_100MS_CSR_CH1_TRIG_DLY 10'h98
`define ADDR_FMC_ADC_100MS_CSR_CH2_CTL 10'h100
`define FMC_ADC_100MS_CSR_CH2_CTL_SSR_OFFSET 0
`define FMC_ADC_100MS_CSR_CH2_CTL_SSR 32'h0000007f
......@@ -120,6 +121,7 @@
`define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_VAL 32'h0000ffff
`define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_HYST_OFFSET 16
`define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_HYST 32'hffff0000
`define ADDR_FMC_ADC_100MS_CSR_CH2_TRIG_DLY 10'h118
`define ADDR_FMC_ADC_100MS_CSR_CH3_CTL 10'h180
`define FMC_ADC_100MS_CSR_CH3_CTL_SSR_OFFSET 0
`define FMC_ADC_100MS_CSR_CH3_CTL_SSR 32'h0000007f
......@@ -140,6 +142,7 @@
`define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_VAL 32'h0000ffff
`define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_HYST_OFFSET 16
`define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_HYST 32'hffff0000
`define ADDR_FMC_ADC_100MS_CSR_CH3_TRIG_DLY 10'h198
`define ADDR_FMC_ADC_100MS_CSR_CH4_CTL 10'h200
`define FMC_ADC_100MS_CSR_CH4_CTL_SSR_OFFSET 0
`define FMC_ADC_100MS_CSR_CH4_CTL_SSR 32'h0000007f
......@@ -160,3 +163,4 @@
`define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_VAL 32'h0000ffff
`define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_HYST_OFFSET 16
`define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_HYST 32'hffff0000
`define ADDR_FMC_ADC_100MS_CSR_CH4_TRIG_DLY 10'h218
hdl/spec/testbench/top/main.sv
View file @ b7fbece5
......@@ -273,6 +273,8 @@ module main;
val = (1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_TIME_OFFSET) |
(1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_EXT_OFFSET);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_EN, val);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_EXT_TRIG_DLY, 3);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SHOTS, 'h0000002);
......
hdl/spec/testbench/top/wave.do
View file @ b7fbece5
......@@ -32,7 +32,6 @@ add wave -noupdate -group l2p_dma /main/DUT/cmp_gn4124_core/cmp_l2p_dma_master/l
add wave -noupdate -group l2p_dma /main/DUT/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_ack_i
add wave -noupdate -group l2p_dma /main/DUT/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_stall_i
add wave -noupdate -group l2p_dma /main/DUT/cmp_gn4124_core/cmp_l2p_dma_master/p2l_dma_cyc_i
add wave -noupdate -group l2p_dma /main/DUT/cmp_gn4124_core/cmp_l2p_dma_master/fifo_rst_n
add wave -noupdate -group l2p_dma /main/DUT/cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_rd
add wave -noupdate -group l2p_dma /main/DUT/cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_wr
add wave -noupdate -group l2p_dma /main/DUT/cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_empty
......@@ -291,14 +290,19 @@ add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/ext_trig_n
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/int_trig_data
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/int_trig_thres
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/int_ch_trig
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/int_trig
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/int_trig_d
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/ext_trig_en
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/int_trig_en
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sw_trig_en
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/time_trig_en
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/ext_trig
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/ext_trig_d
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/ext_trig_fixed_delay
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sw_trig
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sw_trig_fixed_delay
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/time_trig
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/time_trig_fixed_delay
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_fifo_empty
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_fifo_full
......@@ -307,9 +311,10 @@ add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_fifo_din
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_fifo_dout
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_storage
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_delay
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_delay_cnt
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_d
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/ext_trig_delay
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/ext_trig_delay_cnt
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/int_trig_delay
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/int_trig_delay_cnt
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_align
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/undersample_factor
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/undersample_cnt
......
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