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FMC ADC 100M 14b 4cha - Gateware
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FMC ADC 100M 14b 4cha - Gateware
Commits
bb7a29f7
Commit
bb7a29f7
authored
Jan 17, 2020
by
Dimitris Lampridis
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[sim] sync simulations with latest design changes
parent
a5839b29
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4 changed files
with
3 additions
and
11 deletions
+3
-11
main.sv
hdl/testbench/fmc_adc_mezzanine/main.sv
+0
-8
run.do
hdl/testbench/fmc_adc_mezzanine/run.do
+1
-1
run.do
hdl/testbench/svec_ref_design/run.do
+1
-1
run_ci.do
hdl/testbench/svec_ref_design/run_ci.do
+1
-1
No files found.
hdl/testbench/fmc_adc_mezzanine/main.sv
View file @
bb7a29f7
...
...
@@ -92,8 +92,6 @@ module main;
.
si570_scl_b
()
,
.
si570_sda_b
()
,
.
mezz_one_wire_b
()
,
.
sys_scl_b
()
,
.
sys_sda_b
()
,
.
wr_tm_link_up_i
()
,
.
wr_tm_time_valid_i
()
,
.
wr_tm_tai_i
()
,
...
...
@@ -180,12 +178,6 @@ module main;
#
1u
s
;
// Check SDB
expected
=
'h5344422d
;
acc
.
read
(
`SDB_ADDR
,
val
)
;
if
(
val
!=
expected
)
$
fatal
(
1
,
"Unable to detect SDB header at offset 0x%8x."
,
`SDB_ADDR
)
;
// Check status after reset
expected
=
'h19
;
acc
.
read
(
`CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_STA
,
val
)
;
...
...
hdl/testbench/fmc_adc_mezzanine/run.do
View file @
bb7a29f7
vsim -quiet -L unisim work.main
vsim -quiet -L unisim work.main
-voptargs=+acc
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
...
...
hdl/testbench/svec_ref_design/run.do
View file @
bb7a29f7
vsim -quiet -t 10fs -L unisim work.main -
novopt
vsim -quiet -t 10fs -L unisim work.main -
voptargs=+acc -suppress 143,1270,8617,8683,8684,8822
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
...
...
hdl/testbench/svec_ref_design/run_ci.do
View file @
bb7a29f7
vsim -quiet -t 10fs -L unisim work.main
vsim -quiet -t 10fs -L unisim work.main
-suppress 1270,8617,8683,8684,8822
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
...
...
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