Skip to content

F
FMC ADC 100M 14b 4cha - Gateware
Commit ca9e3875 authored by Dimitris Lampridis's avatar Dimitris Lampridis
Browse files
Options

hdl: fixed identation and updated headers on all modified files, prior to new release

parent 1f69cf8c
Show whitespace changes
Inline Side-by-side
Showing with 273 additions and 265 deletions
hdl/adc/rtl/fmc_adc_100Ms_core.vhd
View file @ ca9e3875
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- FMC ADC 100Ms/s core
-- http://www.ohwr.org/projects/fmc-adc-100m14b4cha
--------------------------------------------------------------------------------
--
-- unit name: fmc_adc_100Ms_core (fmc_adc_100Ms_core.vhd)
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
-- Theodor Stana (t.stana@cern.ch)
--
-- date: 28-02-2011
--
-- description: FMC ADC 100Ms/s core.
--
-- dependencies:
--
-- references:
-- [1] Xilinx UG175. FIFO Generator v6.2, July 23, 2010
--
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Title : FMC ADC 100Ms/s core
-- Project : FMC ADC 100M 14B 4CHA gateware
-- URL : http://www.ohwr.org/projects/fmc-adc-100m14b4cha-gw
-------------------------------------------------------------------------------
-- File : fmc_adc_100Ms_core.vhd
-- Author(s) : Matthieu Cattin <matthieu.cattin@cern.ch>
-- Theodor Stana <t.stana@cern.ch>
-- Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-02-24
-- Last update: 2016-04-19
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: FMC ADC 100Ms/s core.
-------------------------------------------------------------------------------
-- Copyright (c) 2011-2016 CERN (BE-CO-HT)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
......@@ -30,11 +27,16 @@
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see git log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2016-04-20 4.1 Dimitrios Lampridis
-- 2014-04-25 4.0 Matthieu Cattin
-- 2014-01-16 3.0 Matthieu Cattin
-- 2013-07-29 2.0 Matthieu Cattin
-- 2013-03-28 1.1 Matthieu Cattin
-- 2013-03-11 1.0 Matthieu Cattin
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
......@@ -222,7 +224,7 @@ architecture rtl of fmc_adc_100Ms_core is
g_CLK_FREQUENCY : natural := 40; --! clk_i frequency (in MHz)
g_OUTPUT_POLARITY : std_logic := '1'; --! pulse_o polarity
--! (1=negative, 0=positive)
g_OUTPUT_RETRIG : boolean := false; --! Retriggerable output monostable
g_OUTPUT_RETRIG : boolean := FALSE; --! Retriggerable output monostable
g_OUTPUT_LENGTH : natural := 1 --! pulse_o lenght (in clk_i ticks)
);
port (
......@@ -252,7 +254,7 @@ architecture rtl of fmc_adc_100Ms_core is
--! ('0'=negative, 1=positive)
g_OUTPUT_POLARITY : std_logic := '1'; --! pulse_o polarity
--! ('0'=negative, 1=positive)
g_OUTPUT_RETRIG : boolean := false; --! Retriggerable output monostable
g_OUTPUT_RETRIG : boolean := FALSE; --! Retriggerable output monostable
g_OUTPUT_LENGTH : natural := 1 --! pulse_o lenght (in clk_i ticks)
);
port (
......@@ -465,7 +467,7 @@ begin
generic map(
g_INPUT_POLARITY => '1',
g_OUTPUT_POLARITY => '1',
g_OUTPUT_RETRIG => true,
g_OUTPUT_RETRIG => TRUE,
g_OUTPUT_LENGTH => 12500000
)
port map(
......@@ -481,7 +483,7 @@ begin
generic map(
g_INPUT_POLARITY => '1',
g_OUTPUT_POLARITY => '1',
g_OUTPUT_RETRIG => true,
g_OUTPUT_RETRIG => TRUE,
g_OUTPUT_LENGTH => 12500000
)
port map(
......@@ -505,7 +507,7 @@ begin
------------------------------------------------------------------------------
cmp_dco_buf : IBUFDS
generic map (
DIFF_TERM => true, -- Differential termination
DIFF_TERM => TRUE, -- Differential termination
IOSTANDARD => "LVDS_25")
port map (
I => adc_dco_p_i,
......@@ -516,9 +518,9 @@ begin
cmp_dco_bufio : BUFIO2
generic map (
DIVIDE => 1,
DIVIDE_BYPASS => true,
I_INVERT => false,
USE_DOUBLER => false)
DIVIDE_BYPASS => TRUE,
I_INVERT => FALSE,
USE_DOUBLER => FALSE)
port map (
I => dco_clk_buf,
IOCLK => open,
......@@ -573,7 +575,7 @@ begin
cmp_fb_clk_bufio : BUFIO2FB
generic map (
DIVIDE_BYPASS => true)
DIVIDE_BYPASS => TRUE)
port map (
I => clk_fb_buf,
O => clk_fb
......@@ -582,7 +584,7 @@ begin
-- Sampinling clock frequency meter
cmp_fs_freq : gc_frequency_meter
generic map(
g_with_internal_timebase => true,
g_with_internal_timebase => TRUE,
g_clk_sys_freq => 125000000,
g_counter_bits => 32
)
......@@ -703,7 +705,7 @@ begin
bitslip_sreg <= bitslip_sreg(0) & bitslip_sreg(bitslip_sreg'length-1 downto 1);
-- Generate bitslip and synced signal
if(bitslip_sreg(bitslip_sreg'left) = '1') then
if(bitslip_sreg(bitslip_sreg'LEFT) = '1') then
if(serdes_out_fr /= "00001111") then -- use fr_n pattern (fr_p and fr_n are swapped on the adc mezzanine)
serdes_auto_bitslip <= '1';
serdes_synced <= '0';
......@@ -828,7 +830,7 @@ begin
g_MIN_PULSE_WIDTH => 1, -- clk_i ticks
g_CLK_FREQUENCY => 100, -- MHz
g_OUTPUT_POLARITY => '0', -- positive pulse
g_OUTPUT_RETRIG => false,
g_OUTPUT_RETRIG => FALSE,
g_OUTPUT_LENGTH => 1 -- clk_i tick
)
port map(
......@@ -978,17 +980,17 @@ begin
generic map (
g_data_width => 65,
g_size => 16,
g_show_ahead => false,
g_with_rd_empty => true,
g_with_rd_full => false,
g_with_rd_almost_empty => false,
g_with_rd_almost_full => false,
g_with_rd_count => false,
g_with_wr_empty => false,
g_with_wr_full => true,
g_with_wr_almost_empty => false,
g_with_wr_almost_full => false,
g_with_wr_count => false,
g_show_ahead => FALSE,
g_with_rd_empty => TRUE,
g_with_rd_full => FALSE,
g_with_rd_almost_empty => FALSE,
g_with_rd_almost_full => FALSE,
g_with_rd_count => FALSE,
g_with_wr_empty => FALSE,
g_with_wr_full => TRUE,
g_with_wr_almost_empty => FALSE,
g_with_wr_almost_full => FALSE,
g_with_wr_count => FALSE,
g_almost_empty_threshold => 0,
g_almost_full_threshold => 0
)
......@@ -1014,7 +1016,7 @@ begin
-- One clock cycle delay for the FIFO's VALID signal. Since the General Cores
-- package does not offer the possibility to use the FWFT feature of the FIFOs,
-- we simulate the valid flag here according to Figure 4-7 in ref. [1].
-- we simulate the valid flag here according to Figure 4-7 in Xilinx UG175.
p_sync_fifo_valid : process (sys_clk_i) is
begin
if rising_edge(sys_clk_i) then
......@@ -1036,7 +1038,7 @@ begin
if fs_rst_n = '0' then
data_calibr_out_d <= (others => (others => '0'));
elsif rising_edge(fs_clk) then
data_calibr_out_d <= data_calibr_out_d(data_calibr_out_d'left-1 downto 0) & data_calibr_out;
data_calibr_out_d <= data_calibr_out_d(data_calibr_out_d'LEFT-1 downto 0) & data_calibr_out;
end if;
end process p_data_delay;
......@@ -1183,7 +1185,7 @@ begin
-- TODO: because of a -yet to be fully understood- bug, acquisition produces
-- corrupted samples when number_of_samples is exactly equal to multi_shot ram
-- size. So for now, number_of_samples should be less than multi_shot ram size.
p_acq_cfg_ok: process (sys_clk_i)
p_acq_cfg_ok : process (sys_clk_i)
begin
if rising_edge(sys_clk_i) then
if sys_rst_n_i = '0' then
......@@ -1398,9 +1400,9 @@ begin
(
g_data_width => 64,
g_size => g_multishot_ram_size,
g_with_byte_enable => false,
g_with_byte_enable => FALSE,
g_addr_conflict_resolution => "read_first",
g_dual_clock => false
g_dual_clock => FALSE
-- default values for the rest of the generics are okay
)
port map
......@@ -1425,9 +1427,9 @@ begin
(
g_data_width => 64,
g_size => g_multishot_ram_size,
g_with_byte_enable => false,
g_with_byte_enable => FALSE,
g_addr_conflict_resolution => "read_first",
g_dual_clock => false
g_dual_clock => FALSE
-- default values for the rest of the generics are okay
)
port map
......@@ -1479,12 +1481,12 @@ begin
generic map (
g_data_width => 65,
g_size => 256,
g_show_ahead => false,
g_with_empty => true,
g_with_full => true,
g_with_almost_empty => false,
g_with_almost_full => false,
g_with_count => false,
g_show_ahead => FALSE,
g_with_empty => TRUE,
g_with_full => TRUE,
g_with_almost_empty => FALSE,
g_with_almost_full => FALSE,
g_with_count => FALSE,
g_almost_empty_threshold => 0,
g_almost_full_threshold => 0
)
......
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
View file @ ca9e3875
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Top level entity for Simple PCIe FMC Carrier
-- http://www.ohwr.org/projects/spec
--------------------------------------------------------------------------------
--
-- unit name: spec_top_fmc_adc_100Ms (spec_top_fmc_adc_100Ms.vhd)
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 24-02-2011
--
-- version: see sdb_meta_pkg.vhd
--
-- description: Top entity of FMC ADC 100Ms/s design for SPEC board.
--
-- dependencies:
--
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Title : FMC ADC 100Ms/s SPEC top-level
-- Project : FMC ADC 100M 14B 4CHA gateware
-- URL : http://www.ohwr.org/projects/fmc-adc-100m14b4cha-gw
-------------------------------------------------------------------------------
-- File : spec_top_fmc_adc_100Ms.vhd
-- Author(s) : Matthieu Cattin <matthieu.cattin@cern.ch>
-- : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-02-24
-- Last update: 2016-04-19
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Top entity of FMC ADC 100Ms/s design for Simple PCIe FMC
-- Carrier (SPEC). See also: http://www.ohwr.org/projects/spec
-------------------------------------------------------------------------------
-- Copyright (c) 2011-2016 CERN (BE-CO-HT)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
......@@ -28,11 +27,16 @@
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see git log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2016-04-20 4.1 Dimitrios Lampridis
-- 2014-04-25 4.0 Matthieu Cattin
-- 2014-01-16 3.0 Matthieu Cattin
-- 2013-07-29 2.0 Matthieu Cattin
-- 2013-03-28 1.1 Matthieu Cattin
-- 2013-03-11 1.0 Matthieu Cattin
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
......@@ -522,8 +526,8 @@ begin
------------------------------------------------------------------------------
cmp_l_clk_buf : IBUFDS
generic map (
DIFF_TERM => false, -- Differential Termination
IBUF_LOW_PWR => true, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
DIFF_TERM => FALSE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => l_clk, -- Buffer output
......@@ -653,8 +657,8 @@ begin
generic map (
g_num_masters => c_NUM_WB_SLAVES,
g_num_slaves => c_NUM_WB_MASTERS,
g_registered => true,
g_wraparound => true,
g_registered => TRUE,
g_wraparound => TRUE,
g_layout => c_INTERCONNECT_LAYOUT,
g_sdb_addr => c_SDB_ADDRESS)
port map (
......
hdl/svec/rtl/svec_top_fmc_adc_100Ms.vhd
View file @ ca9e3875
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Top level entity for Simple VME FMC Carrier
-- http://www.ohwr.org/projects/svec
--------------------------------------------------------------------------------
--
-- unit name: svec_top_fmc_adc_100Ms (svec_top_fmc_adc_100Ms.vhd)
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 04-07-2013
--
-- version: see sdb_meta_pkg.vhd
--
-- description: Top entity of FMC ADC 100Ms/s design for SVEC board.
--
-- dependencies:
--
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Title : FMC ADC 100Ms/s SVEC top-level
-- Project : FMC ADC 100M 14B 4CHA gateware
-- URL : http://www.ohwr.org/projects/fmc-adc-100m14b4cha-gw
-------------------------------------------------------------------------------
-- File : svec_top_fmc_adc_100Ms.vhd
-- Author(s) : Matthieu Cattin <matthieu.cattin@cern.ch>
-- : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2013-07-04
-- Last update: 2016-04-19
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Top entity of FMC ADC 100Ms/s design for Simple VME FMC
-- Carrier (SVEC). See also: http://www.ohwr.org/projects/svec
-------------------------------------------------------------------------------
-- Copyright (c) 2013-2016 CERN (BE-CO-HT)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
......@@ -28,11 +27,14 @@
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see git log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2016-04-20 4.1 Dimitrios Lampridis
-- 2014-04-25 4.0 Matthieu Cattin
-- 2014-01-16 3.0 Matthieu Cattin
-- 2013-07-29 1.0 Matthieu Cattin
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
......@@ -775,8 +777,8 @@ begin
generic map (
g_num_masters => c_NUM_WB_SLAVES,
g_num_slaves => c_NUM_WB_MASTERS,
g_registered => true,
g_wraparound => true,
g_registered => TRUE,
g_wraparound => TRUE,
g_layout => c_INTERCONNECT_LAYOUT,
g_sdb_addr => c_SDB_ADDRESS)
port map (
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment