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FMC ADC 100M 14b 4cha - Gateware
Commit d31b0d43 authored by mcattin's avatar mcattin
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Fix timing issues in spi by adding a FF on the din path. 

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@50 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
parent 53345459
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Showing with 9 additions and 21 deletions
hdl/spec/ise_project/spec_fmc_adc_100Ms.gise
View file @ d31b0d43
......@@ -137,13 +137,11 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1300788409" xil_pn:in_ck="-6698355625770614420" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8197382171204319838" xil_pn:start_ts="1300788183">
<transform xil_pn:end_ts="1300809331" xil_pn:in_ck="-6698355625770614420" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8197382171204319838" xil_pn:start_ts="1300809106">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.lso"/>
......@@ -161,24 +159,20 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1300794486" xil_pn:in_ck="6806541686375937701" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7643830140109020653" xil_pn:start_ts="1300794455">
<transform xil_pn:end_ts="1300809359" xil_pn:in_ck="6806541686375937701" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7643830140109020653" xil_pn:start_ts="1300809331">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.bld"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.ngd"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1300794864" xil_pn:in_ck="8313289856678850416" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-525288356180264082" xil_pn:start_ts="1300794486">
<transform xil_pn:end_ts="1300809738" xil_pn:in_ck="8313289856678850416" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-525288356180264082" xil_pn:start_ts="1300809359">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.pcf"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_map.map"/>
......@@ -189,11 +183,10 @@
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_summary.xml"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1300795175" xil_pn:in_ck="-1808195220703275450" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="5879947102106257248" xil_pn:start_ts="1300794864">
<transform xil_pn:end_ts="1300809947" xil_pn:in_ck="-1808195220703275450" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="5879947102106257248" xil_pn:start_ts="1300809738">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.ncd"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.pad"/>
......@@ -205,11 +198,10 @@
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_pad.txt"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1300795240" xil_pn:in_ck="1401670161614903244" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="1554780821134721645" xil_pn:start_ts="1300795175">
<transform xil_pn:end_ts="1300810013" xil_pn:in_ck="1401670161614903244" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="1554780821134721645" xil_pn:start_ts="1300809947">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.bgn"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.bin"/>
......@@ -223,15 +215,13 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
</transform>
<transform xil_pn:end_ts="1300795175" xil_pn:in_ck="8313289856678850284" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="4435602129065547965" xil_pn:start_ts="1300795130">
<transform xil_pn:end_ts="1300809947" xil_pn:in_ck="8313289856678850284" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="4435602129065547965" xil_pn:start_ts="1300809905">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.twr"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.twx"/>
......
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
View file @ d31b0d43
......@@ -570,9 +570,7 @@ architecture rtl of spec_top_fmc_adc_100Ms is
signal ddr3_calib_done : std_logic;
-- SPI
signal spi_sck_t : std_logic_vector(2 downto 0);
signal spi_din_t : std_logic_vector(2 downto 0);
signal spi_dout_t : std_logic_vector(2 downto 0);
signal spi_din_t : std_logic_vector(3 downto 0);
signal spi_ss_t : std_logic_vector(7 downto 0);
......@@ -866,7 +864,7 @@ begin
ss_pad_o => spi_ss_t,
sclk_pad_o => spi_sck_o,
mosi_pad_o => spi_dout_o,
miso_pad_i => spi_din_t(2)
miso_pad_i => spi_din_t(spi_din_t'left)
);
-- 32-bit word to byte address
......@@ -886,7 +884,7 @@ begin
if sys_rst_n = '0' then
spi_din_t <= (others => '0');
else
spi_din_t <= spi_din_t(1 downto 0) & spi_din_i;
spi_din_t <= spi_din_t(spi_din_t'left-1 downto 0) & spi_din_i;
end if;
end if;
end process p_fmc_spi;
......
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