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FMC ADC 100M 14b 4cha - Gateware
Commit d5592fa4 authored by mcattin's avatar mcattin
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Bug fix in serdes data reordering, add manual bitslip 

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@44 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
parent 0b5d6966
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Showing with 285 additions and 196 deletions
hdl/spec/ip_cores/adc_serdes.vhd
View file @ d5592fa4
......@@ -232,12 +232,12 @@ begin
in_slices: for slice_count in 0 to num_serial_bits-1 generate begin
-- This places the first data in time on the right
DATA_IN_TO_DEVICE(slice_count*sys_w+sys_w-1 downto slice_count*sys_w) <=
iserdes_q(num_serial_bits-slice_count-1);
--DATA_IN_TO_DEVICE(slice_count*sys_w+sys_w-1 downto slice_count*sys_w) <=
-- iserdes_q(num_serial_bits-slice_count-1);
-- To place the first data in time on the left, use the
-- following code, instead
-- DATA_IN_TO_DEVICE(slice_count*sys_w+sys_w-1 downto sys_w) <=
-- iserdes_q(slice_count);
DATA_IN_TO_DEVICE(slice_count*sys_w+sys_w-1 downto slice_count*sys_w) <=
iserdes_q(slice_count);
end generate in_slices;
......
hdl/spec/ise_project/iseconfig/spec_top.xreport
View file @ d5592fa4
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2011-03-09T11:16:52</DateModified>
<ModuleName>spec_top</ModuleName>
<SummaryTimeStamp>2011-03-09T11:15:37</SummaryTimeStamp>
<DateModified>2011-03-16T07:57:36</DateModified>
<ModuleName>spec_top_fmc_adc_100Ms</ModuleName>
<SummaryTimeStamp>2011-03-09T11:19:20</SummaryTimeStamp>
<SavedFilePath>/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/ise_project/iseconfig/spec_top.xreport</SavedFilePath>
<ImplementationReportsDirectory>/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/ise_project/</ImplementationReportsDirectory>
<DateInitialized>2011-02-24T10:24:34</DateInitialized>
<DateInitialized>2011-03-10T15:11:50</DateInitialized>
<EnableMessageFiltering>false</EnableMessageFiltering>
</header>
<body>
<viewgroup label="Design Overview" >
<view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="spec_top_summary.html" label="Summary" >
<view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="spec_top_fmc_adc_100Ms_summary.html" label="Summary" >
<toc-item title="Design Overview" target="Design Overview" />
<toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
<toc-item title="Performance Summary" target="Performance Summary" />
<toc-item title="Failing Constraints" target="Failing Constraints" />
<toc-item title="Detailed Reports" target="Detailed Reports" />
</view>
<view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="spec_top_envsettings.html" label="System Settings" />
<view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="spec_top_map.xrpt" showConstraints="0" label="IOB Properties" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="spec_top_map.xrpt" label="Control Set Information" />
<view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="spec_top_map.xrpt" label="Module Level Utilization" />
<view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="spec_top.ptwx" showConstraints="0" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
<view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="spec_top_par.xrpt" showConstraints="0" label="Pinout Report" />
<view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="spec_top_par.xrpt" label="Clock Report" />
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="spec_top.twx" label="Static Timing" />
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="spec_top_html/fit/report.htm" label="CPLD Fitter Report" />
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="spec_top_html/tim/report.htm" label="CPLD Timing Report" />
<view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="spec_top_fmc_adc_100Ms_envsettings.html" label="System Settings" />
<view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="spec_top_fmc_adc_100Ms_map.xrpt" showConstraints="0" label="IOB Properties" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="spec_top_fmc_adc_100Ms_map.xrpt" label="Control Set Information" />
<view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="spec_top_fmc_adc_100Ms_map.xrpt" label="Module Level Utilization" />
<view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="spec_top_fmc_adc_100Ms.ptwx" showConstraints="0" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
<view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="spec_top_fmc_adc_100Ms_par.xrpt" showConstraints="0" label="Pinout Report" />
<view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="spec_top_fmc_adc_100Ms_par.xrpt" label="Clock Report" />
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="spec_top_fmc_adc_100Ms.twx" label="Static Timing" />
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="spec_top_fmc_adc_100Ms_html/fit/report.htm" label="CPLD Fitter Report" />
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="spec_top_fmc_adc_100Ms_html/tim/report.htm" label="CPLD Timing Report" />
</viewgroup>
<viewgroup label="XPS Errors and Warnings" >
<view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
......@@ -40,7 +40,7 @@
<view inputState="PreSynthesized" program="libgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="libgen.log" label="Libgen Log File" />
<view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
<view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
<view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="spec_top.log" label="System Log File" />
<view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="spec_top_fmc_adc_100Ms.log" label="System Log File" />
</viewgroup>
<viewgroup label="Errors and Warnings" >
<view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
......@@ -56,7 +56,7 @@
<view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
</viewgroup>
<viewgroup label="Detailed Reports" >
<view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="spec_top.syr" label="Synthesis Report" >
<view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="spec_top_fmc_adc_100Ms.syr" label="Synthesis Report" >
<toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
<toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " />
<toc-item title="HDL Compilation" target=" HDL Compilation " />
......@@ -81,15 +81,15 @@
<toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
<toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
</view>
<view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="spec_top.srr" label="Synplify Report" />
<view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="spec_top.prec_log" label="Precision Report" />
<view inputState="Synthesized" program="ngdbuild" type="Report" file="spec_top.bld" label="Translation Report" >
<view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="spec_top_fmc_adc_100Ms.srr" label="Synplify Report" />
<view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="spec_top_fmc_adc_100Ms.prec_log" label="Precision Report" />
<view inputState="Synthesized" program="ngdbuild" type="Report" file="spec_top_fmc_adc_100Ms.bld" label="Translation Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Command Line" target="Command Line:" />
<toc-item title="Partition Status" target="Partition Implementation Status" />
<toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
</view>
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="spec_top_map.mrp" label="Map Report" >
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="spec_top_fmc_adc_100Ms_map.mrp" label="Map Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
<toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
......@@ -105,7 +105,7 @@
<toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
<toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="spec_top.par" label="Place and Route Report" >
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="spec_top_fmc_adc_100Ms.par" label="Place and Route Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Device Utilization" target="Device Utilization Summary:" />
<toc-item title="Router Information" target="Starting Router" />
......@@ -114,7 +114,7 @@
<toc-item title="Timing Results" target="Timing Score:" />
<toc-item title="Final Summary" target="Peak Memory Usage:" />
</view>
<view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="spec_top.twr" label="Post-PAR Static Timing Report" >
<view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="spec_top_fmc_adc_100Ms.twr" label="Post-PAR Static Timing Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
......@@ -125,22 +125,22 @@
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
</view>
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="spec_top.rpt" label="CPLD Fitter Report (Text)" >
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="spec_top_fmc_adc_100Ms.rpt" label="CPLD Fitter Report (Text)" >
<toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
<toc-item title="Resources Summary" target="** Mapped Resource Summary **" />
<toc-item title="Pin Resources" target="** Pin Resources **" />
<toc-item title="Global Resources" target="** Global Control Resources **" />
</view>
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="spec_top.tim" label="CPLD Timing Report (Text)" >
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="spec_top_fmc_adc_100Ms.tim" label="CPLD Timing Report (Text)" >
<toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
<toc-item title="Performance Summary" target="Performance Summary:" />
</view>
<view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="spec_top.pwr" label="Power Report" >
<view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="spec_top_fmc_adc_100Ms.pwr" label="Power Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Power summary" target="Power summary" />
<toc-item title="Thermal summary" target="Thermal summary" />
</view>
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="spec_top.bgn" label="Bitgen Report" >
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="spec_top_fmc_adc_100Ms.bgn" label="Bitgen Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
<toc-item title="Final Summary" target="DRC detected" />
......@@ -148,20 +148,20 @@
</viewgroup>
<viewgroup label="Secondary Reports" >
<view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
<view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/spec_top_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
<view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/spec_top_fmc_adc_100Ms_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/spec_top_translate.nlf" label="Post-Translate Simulation Model Report" >
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/spec_top_fmc_adc_100Ms_translate.nlf" label="Post-Translate Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="spec_top_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="spec_top_map.map" label="Map Log File" >
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="spec_top_fmc_adc_100Ms_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="spec_top_fmc_adc_100Ms_map.map" label="Map Log File" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Design Information" target="Design Information" />
<toc-item title="Design Summary" target="Design Summary" />
</view>
<view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
<view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spec_top_preroute.twr" label="Post-Map Static Timing Report" >
<view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spec_top_fmc_adc_100Ms_preroute.twr" label="Post-Map Static Timing Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
......@@ -172,43 +172,43 @@
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
</view>
<view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/spec_top_map.nlf" label="Post-Map Simulation Model Report" />
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spec_top_map.psr" label="Physical Synthesis Report" >
<view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/spec_top_fmc_adc_100Ms_map.nlf" label="Post-Map Simulation Model Report" />
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spec_top_fmc_adc_100Ms_map.psr" label="Physical Synthesis Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="spec_top_pad.txt" label="Pad Report" >
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="spec_top_fmc_adc_100Ms_pad.txt" label="Pad Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="spec_top.unroutes" label="Unroutes Report" >
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="spec_top_fmc_adc_100Ms.unroutes" label="Unroutes Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spec_top_preroute.tsi" label="Post-Map Constraints Interaction Report" >
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spec_top_fmc_adc_100Ms_preroute.tsi" label="Post-Map Constraints Interaction Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spec_top.grf" label="Guide Results Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spec_top.dly" label="Asynchronous Delay Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spec_top.clk_rgn" label="Clock Region Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spec_top.tsi" label="Post-Place and Route Constraints Interaction Report" >
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spec_top_fmc_adc_100Ms.grf" label="Guide Results Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spec_top_fmc_adc_100Ms.dly" label="Asynchronous Delay Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spec_top_fmc_adc_100Ms.clk_rgn" label="Clock Region Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spec_top_fmc_adc_100Ms.tsi" label="Post-Place and Route Constraints Interaction Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="spec_top_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
<view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/spec_top_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="spec_top_sta.nlf" label="Primetime Netlist Report" >
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="spec_top_fmc_adc_100Ms_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
<view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/spec_top_fmc_adc_100Ms_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="spec_top_fmc_adc_100Ms_sta.nlf" label="Primetime Netlist Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="spec_top.ibs" label="IBIS Model" >
<view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="spec_top_fmc_adc_100Ms.ibs" label="IBIS Model" >
<toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
<toc-item title="Component" target="Component " />
</view>
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spec_top.lck" label="Back-annotate Pin Report" >
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spec_top_fmc_adc_100Ms.lck" label="Back-annotate Pin Report" >
<toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
<toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
</view>
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spec_top.lpc" label="Locked Pin Constraints" >
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spec_top_fmc_adc_100Ms.lpc" label="Locked Pin Constraints" >
<toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
<toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
</view>
<view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/spec_top_timesim.nlf" label="Post-Fit Simulation Model Report" />
<view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/spec_top_fmc_adc_100Ms_timesim.nlf" label="Post-Fit Simulation Model Report" />
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
</viewgroup>
......
hdl/spec/ise_project/spec_fmc_adc_100Ms.gise
View file @ d5592fa4
......@@ -43,35 +43,65 @@
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="spec_top.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="spec_top.ngd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="spec_top.ngr"/>
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="spec_top.pad"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="spec_top.par" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="spec_top.pcf" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="spec_top.prj"/>
<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="spec_top.ptwx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="spec_top.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="spec_top.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="spec_top.twr" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="spec_top.twx" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="spec_top.unroutes" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="spec_top.ut" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="spec_top.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="spec_top.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="spec_top_envsettings.html"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="spec_top_fmc_adc_100Ms.bgn" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_BIN" xil_pn:name="spec_top_fmc_adc_100Ms.bin"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="spec_top_fmc_adc_100Ms.bit" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="spec_top_fmc_adc_100Ms.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="spec_top_fmc_adc_100Ms.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="spec_top_fmc_adc_100Ms.drc" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="spec_top_fmc_adc_100Ms.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="spec_top_fmc_adc_100Ms.ncd" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="spec_top_fmc_adc_100Ms.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="spec_top_fmc_adc_100Ms.ngd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="spec_top_fmc_adc_100Ms.ngr"/>
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="spec_top_fmc_adc_100Ms.pad"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="spec_top_fmc_adc_100Ms.par" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="spec_top_fmc_adc_100Ms.pcf" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="spec_top_fmc_adc_100Ms.prj"/>
<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="spec_top_fmc_adc_100Ms.ptwx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="spec_top_fmc_adc_100Ms.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="spec_top_fmc_adc_100Ms.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="spec_top_fmc_adc_100Ms.twr" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="spec_top_fmc_adc_100Ms.twx" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="spec_top_fmc_adc_100Ms.unroutes" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="spec_top_fmc_adc_100Ms.ut" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="spec_top_fmc_adc_100Ms.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="spec_top_fmc_adc_100Ms.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="spec_top_fmc_adc_100Ms_envsettings.html"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="spec_top_fmc_adc_100Ms_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="spec_top_fmc_adc_100Ms_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="spec_top_fmc_adc_100Ms_map.mrp" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="spec_top_fmc_adc_100Ms_map.ncd" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="spec_top_fmc_adc_100Ms_map.ngm" xil_pn:subbranch="Map"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="spec_top_fmc_adc_100Ms_map.xrpt"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="spec_top_fmc_adc_100Ms_ngdbuild.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="spec_top_fmc_adc_100Ms_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="spec_top_fmc_adc_100Ms_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="spec_top_fmc_adc_100Ms_par.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="spec_top_fmc_adc_100Ms_summary.html"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="spec_top_fmc_adc_100Ms_summary.xml"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="spec_top_fmc_adc_100Ms_usage.xml"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="spec_top_fmc_adc_100Ms_xst.xrpt"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="spec_top_fpga_editor.log"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="spec_top_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="spec_top_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="spec_top_map.mrp" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="spec_top_map.ncd" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="spec_top_map.ngm" xil_pn:subbranch="Map"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="spec_top_map.xrpt"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="spec_top_ngdbuild.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="spec_top_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="spec_top_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="spec_top_par.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="spec_top_summary.html"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="spec_top_summary.xml"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="spec_top_usage.xml"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="spec_top_xst.xrpt"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
......@@ -83,11 +113,11 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1299483117" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-4655097310102199149" xil_pn:start_ts="1299483117">
<transform xil_pn:end_ts="1299776202" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-5336720412813903745" xil_pn:start_ts="1299776202">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1299483117" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="2099650482794156374" xil_pn:start_ts="1299483117">
<transform xil_pn:end_ts="1299776202" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-6573690209299584574" xil_pn:start_ts="1299776202">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
......@@ -95,7 +125,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1299483117" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="7611406935666307157" xil_pn:start_ts="1299483117">
<transform xil_pn:end_ts="1299776202" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-972982594196377663" xil_pn:start_ts="1299776202">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
......@@ -103,90 +133,90 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1299483117" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-7096291744251652000" xil_pn:start_ts="1299483117">
<transform xil_pn:end_ts="1299776202" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="3375361665759590988" xil_pn:start_ts="1299776202">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1299665078" xil_pn:in_ck="-6698355625770614420" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-4700144962104088910" xil_pn:start_ts="1299664867">
<transform xil_pn:end_ts="1300213822" xil_pn:in_ck="-6698355625770614420" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8197382171204319838" xil_pn:start_ts="1300213598">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="spec_top.lso"/>
<outfile xil_pn:name="spec_top.ngc"/>
<outfile xil_pn:name="spec_top.ngr"/>
<outfile xil_pn:name="spec_top.prj"/>
<outfile xil_pn:name="spec_top.stx"/>
<outfile xil_pn:name="spec_top.syr"/>
<outfile xil_pn:name="spec_top.xst"/>
<outfile xil_pn:name="spec_top_xst.xrpt"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.lso"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.ngc"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.ngr"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.prj"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.stx"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.syr"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.xst"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_xst.xrpt"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1299665078" xil_pn:in_ck="2162529744943951648" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3143274269413541142" xil_pn:start_ts="1299665078">
<transform xil_pn:end_ts="1299776415" xil_pn:in_ck="2162529744943951648" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-4337831395208791850" xil_pn:start_ts="1299776415">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1299665105" xil_pn:in_ck="-5205591137091154823" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-8659698654136953279" xil_pn:start_ts="1299665078">
<transform xil_pn:end_ts="1300213850" xil_pn:in_ck="6806541686375937701" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7643830140109020653" xil_pn:start_ts="1300213822">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<outfile xil_pn:name="spec_top.bld"/>
<outfile xil_pn:name="spec_top.ngd"/>
<outfile xil_pn:name="spec_top_ngdbuild.xrpt"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.bld"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.ngd"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1299665495" xil_pn:in_ck="-4758618940946871356" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-525288356180264082" xil_pn:start_ts="1299665105">
<transform xil_pn:end_ts="1300214231" xil_pn:in_ck="8313289856678850416" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-525288356180264082" xil_pn:start_ts="1300213850">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="spec_top.pcf"/>
<outfile xil_pn:name="spec_top_map.map"/>
<outfile xil_pn:name="spec_top_map.mrp"/>
<outfile xil_pn:name="spec_top_map.ncd"/>
<outfile xil_pn:name="spec_top_map.ngm"/>
<outfile xil_pn:name="spec_top_map.xrpt"/>
<outfile xil_pn:name="spec_top_summary.xml"/>
<outfile xil_pn:name="spec_top_usage.xml"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.pcf"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_map.map"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_map.mrp"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_map.ncd"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_map.ngm"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_map.xrpt"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_summary.xml"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1299665735" xil_pn:in_ck="-7505570899544269603" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="5879947102106257248" xil_pn:start_ts="1299665495">
<transform xil_pn:end_ts="1300214481" xil_pn:in_ck="-1808195220703275450" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="5879947102106257248" xil_pn:start_ts="1300214231">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="spec_top.ncd"/>
<outfile xil_pn:name="spec_top.pad"/>
<outfile xil_pn:name="spec_top.par"/>
<outfile xil_pn:name="spec_top.ptwx"/>
<outfile xil_pn:name="spec_top.unroutes"/>
<outfile xil_pn:name="spec_top.xpi"/>
<outfile xil_pn:name="spec_top_pad.csv"/>
<outfile xil_pn:name="spec_top_pad.txt"/>
<outfile xil_pn:name="spec_top_par.xrpt"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.ncd"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.pad"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.par"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.ptwx"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.unroutes"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.xpi"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_pad.csv"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_pad.txt"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1299665960" xil_pn:in_ck="5988710092847000608" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="1554780821134721645" xil_pn:start_ts="1299665892">
<transform xil_pn:end_ts="1300214546" xil_pn:in_ck="1401670161614903244" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="1554780821134721645" xil_pn:start_ts="1300214481">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="spec_top.bgn"/>
<outfile xil_pn:name="spec_top.bin"/>
<outfile xil_pn:name="spec_top.bit"/>
<outfile xil_pn:name="spec_top.drc"/>
<outfile xil_pn:name="spec_top.ut"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.bgn"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.bin"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.bit"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.drc"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.ut"/>
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1299665735" xil_pn:in_ck="-4758618940946871488" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="4435602129065547965" xil_pn:start_ts="1299665694">
<transform xil_pn:end_ts="1300214481" xil_pn:in_ck="8313289856678850284" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="4435602129065547965" xil_pn:start_ts="1300214439">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="spec_top.twr"/>
<outfile xil_pn:name="spec_top.twx"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.twr"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.twx"/>
</transform>
</transforms>
......
hdl/spec/ise_project/spec_fmc_adc_100Ms.xise
View file @ d5592fa4
......@@ -213,6 +213,7 @@
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Name" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
......@@ -227,7 +228,9 @@
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Data Flow window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF ModelSim" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx45t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
......@@ -278,10 +281,12 @@
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Verbose Library Compilation Messages" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map" xil_pn:value="Off" xil_pn:valueState="default"/>
......@@ -289,11 +294,12 @@
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore Pre-Compiled Library Warning Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|spec_top|rtl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|spec_top_fmc_adc_100Ms|rtl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../rtl/spec_top_fmc_adc_100Ms.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/spec_top" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/spec_top_fmc_adc_100Ms" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -312,6 +318,11 @@
<property xil_pn:name="Last Applied Goal" xil_pn:value="Timing Performance" xil_pn:valueState="non-default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Performance with IOB Packing;/opt/Xilinx/12.2/ISE_DS/ISE/spartan6/data/spartan6_performance_with_iobpacking.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="List window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Behavioral Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Map Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Par Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Translate Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
......@@ -319,6 +330,8 @@
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Map UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Par UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
......@@ -348,10 +361,13 @@
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VCOM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VLOG Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VSIM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="spec_top" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="spec_top_fmc_adc_100Ms" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Yes" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
......@@ -365,14 +381,15 @@
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default" xil_pn:x_locked="true"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="Normal" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="spec_top_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="spec_top_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="spec_top_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="spec_top_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="spec_top_fmc_adc_100Ms_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="spec_top_fmc_adc_100Ms_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="spec_top_fmc_adc_100Ms_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="spec_top_fmc_adc_100Ms_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Process window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Advanced Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -390,7 +407,7 @@
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="spec_top" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="spec_top_fmc_adc_100Ms" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
......@@ -412,7 +429,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/spec_top_fmc_adc_100Ms" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.spec_top_fmc_adc_100Ms" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -422,22 +440,27 @@
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Signal window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Resolution" xil_pn:value="Default (1 ps)" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="1000ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="Modelsim-SE VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.spec_top_fmc_adc_100Ms" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Modelsim-SE VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -445,7 +468,13 @@
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use Automatic Do File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Configuration Name" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -459,6 +488,7 @@
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Explicit Declarations Only" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -469,11 +499,14 @@
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Syntax" xil_pn:value="93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Variables window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Wave window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
......
hdl/spec/ise_project/spec_top_summary.html
View file @ d5592fa4
......@@ -522,5 +522,5 @@ System Settings</A>
</TABLE>
<br><center><b>Date Generated:</b> 03/09/2011 - 11:19:20</center>
<br><center><b>Date Generated:</b> 03/10/2011 - 15:11:49</center>
</BODY></HTML>
\ No newline at end of file
hdl/spec/rtl/carrier_csr.vhd
View file @ d5592fa4
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Mon Feb 28 16:09:47 2011
-- Created : Thu Mar 10 14:51:39 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
......
hdl/spec/rtl/fmc_adc_100Ms_core.vhd
View file @ d5592fa4
......@@ -132,6 +132,7 @@ architecture rtl of fmc_adc_100Ms_core is
fmc_adc_core_ctl_fsm_cmd_wr_o : out std_logic;
fmc_adc_core_ctl_fmc_clk_oe_o : out std_logic;
fmc_adc_core_ctl_offset_dac_clr_n_o : out std_logic;
fmc_adc_core_ctl_man_bitslip_o : out std_logic;
fmc_adc_core_sta_fsm_i : in std_logic_vector(2 downto 0);
fmc_adc_core_sta_serdes_pll_i : in std_logic;
fmc_adc_core_sta_serdes_synced_i : in std_logic;
......@@ -265,6 +266,8 @@ architecture rtl of fmc_adc_100Ms_core is
signal serdes_out_raw : std_logic_vector(71 downto 0);
signal serdes_out_data : std_logic_vector(63 downto 0);
signal serdes_out_fr : std_logic_vector(7 downto 0);
signal serdes_auto_bitslip : std_logic;
signal serdes_man_bitslip : std_logic;
signal serdes_bitslip : std_logic;
signal serdes_synced : std_logic;
signal bitslip_sreg : std_logic_vector(7 downto 0);
......@@ -460,16 +463,19 @@ begin
& adc_outa_n_i(1) & adc_outb_n_i(1)
& adc_outa_n_i(0) & adc_outb_n_i(0);
-- serdes outputs re-ordering
-- out_raw(7:0) = CH1D12 CH1D10 CH1D8 CH1D6 CH1D4 CH1D2 CH1D0 0 = CH1_B
-- out_raw(15:8) = CH1D13 CH1D11 CH1D9 CH1D7 CH1D5 CH1D3 CH1D1 0 = CH1_A
-- out_raw(23:16) = CH2D12 CH2D10 CH2D8 CH2D6 CH2D4 CH2D2 CH2D0 0 = CH2_B
-- out_raw(31:24) = CH2D13 CH2D11 CH2D9 CH2D7 CH2D5 CH2D3 CH2D1 0 = CH2_A
-- out_raw(39:32) = CH3D12 CH3D10 CH3D8 CH3D6 CH3D4 CH3D2 CH3D0 0 = CH3_B
-- out_raw(47:40) = CH3D13 CH3D11 CH3D9 CH3D7 CH3D5 CH3D3 CH3D1 0 = CH3_A
-- out_raw(55:48) = CH4D12 CH4D10 CH4D8 CH4D6 CH4D4 CH4D2 CH4D0 0 = CH4_B
-- out_raw(63:56) = CH4D13 CH4D11 CH4D9 CH4D7 CH4D5 CH4D3 CH4D1 0 = CH4_A
-- out_raw(71:64) = FR7 FR6 FR5 FR4 FR3 FR2 FR1 FR0 = FR
-- serdes outputs re-ordering (time slices -> channel)
-- out_raw :(71:63)(62:54)(53:45)(44:36)(35:27)(26:18)(17:9)(8:0)
-- | | | | | | | |
-- V V V V V V V V
-- CH1D12 CH1D10 CH1D8 CH1D6 CH1D4 CH1D2 CH1D0 0 = CH1_B
-- CH1D13 CH1D11 CH1D9 CH1D7 CH1D5 CH1D3 CH1D1 0 = CH1_A
-- CH2D12 CH2D10 CH2D8 CH2D6 CH2D4 CH2D2 CH2D0 0 = CH2_B
-- CH2D13 CH2D11 CH2D9 CH2D7 CH2D5 CH2D3 CH2D1 0 = CH2_A
-- CH3D12 CH3D10 CH3D8 CH3D6 CH3D4 CH3D2 CH3D0 0 = CH3_B
-- CH3D13 CH3D11 CH3D9 CH3D7 CH3D5 CH3D3 CH3D1 0 = CH3_A
-- CH4D12 CH4D10 CH4D8 CH4D6 CH4D4 CH4D2 CH4D0 0 = CH4_B
-- CH4D13 CH4D11 CH4D9 CH4D7 CH4D5 CH4D3 CH4D1 0 = CH4_A
-- FR7 FR6 FR5 FR4 FR3 FR2 FR1 FR0 = FR
--
-- out_data(15:0) = CH1
-- out_data(31:16) = CH2
......@@ -477,24 +483,24 @@ begin
-- out_data(63:48) = CH4
-- Note: The two LSBs of each channel are always '0' => 14-bit ADC
gen_serdes_dout_reorder : for I in 0 to 7 generate
serdes_out_data(0*16 + 2*i) <= serdes_out_raw(i + 0*8); -- CH1 even bits
serdes_out_data(0*16 + 2*i+1) <= serdes_out_raw(i + 1*8); -- CH1 odd bits
serdes_out_data(1*16 + 2*i) <= serdes_out_raw(i + 2*8); -- CH2 even bits
serdes_out_data(1*16 + 2*i+1) <= serdes_out_raw(i + 3*8); -- CH2 odd bits
serdes_out_data(2*16 + 2*i) <= serdes_out_raw(i + 4*8); -- CH3 even bits
serdes_out_data(2*16 + 2*i+1) <= serdes_out_raw(i + 5*8); -- CH3 odd bits
serdes_out_data(3*16 + 2*i) <= serdes_out_raw(i + 6*8); -- CH4 even bits
serdes_out_data(3*16 + 2*i+1) <= serdes_out_raw(i + 7*8); -- CH4 odd bits
serdes_out_fr(i) <= serdes_out_raw(i + 8*8); -- FR
serdes_out_data(0*16 + 2*i) <= serdes_out_raw(0 + i*9); -- CH1 even bits
serdes_out_data(0*16 + 2*i+1) <= serdes_out_raw(1 + i*9); -- CH1 odd bits
serdes_out_data(1*16 + 2*i) <= serdes_out_raw(2 + i*9); -- CH2 even bits
serdes_out_data(1*16 + 2*i+1) <= serdes_out_raw(3 + i*9); -- CH2 odd bits
serdes_out_data(2*16 + 2*i) <= serdes_out_raw(4 + i*9); -- CH3 even bits
serdes_out_data(2*16 + 2*i+1) <= serdes_out_raw(5 + i*9); -- CH3 odd bits
serdes_out_data(3*16 + 2*i) <= serdes_out_raw(6 + i*9); -- CH4 even bits
serdes_out_data(3*16 + 2*i+1) <= serdes_out_raw(7 + i*9); -- CH4 odd bits
serdes_out_fr(i) <= serdes_out_raw(8 + i*9); -- FR
end generate gen_serdes_dout_reorder;
-- serdes bitslip generation
p_bitslip : process (fs_clk, sys_rst_n_i)
p_auto_bitslip : process (fs_clk, sys_rst_n_i)
begin
if sys_rst_n_i = '0' then
bitslip_sreg <= std_logic_vector(to_unsigned(1, bitslip_sreg'length));
serdes_bitslip <= '0';
serdes_auto_bitslip <= '0';
serdes_synced <= '0';
elsif rising_edge(fs_clk) then
......@@ -504,19 +510,21 @@ begin
-- Generate bitslip and synced signal
if(bitslip_sreg(bitslip_sreg'left) = '1') then
if(serdes_out_fr /= "11110000") then
serdes_bitslip <= '1';
serdes_auto_bitslip <= '1';
serdes_synced <= '0';
else
serdes_bitslip <= '0';
serdes_auto_bitslip <= '0';
serdes_synced <= '1';
end if;
else
serdes_bitslip <= '0';
serdes_auto_bitslip <= '0';
end if;
end if;
end process;
serdes_bitslip <= serdes_auto_bitslip or serdes_man_bitslip;
------------------------------------------------------------------------------
-- ADC core control and status registers (CSR)
------------------------------------------------------------------------------
......@@ -537,6 +545,7 @@ begin
fmc_adc_core_ctl_fsm_cmd_wr_o => fsm_cmd_wr,
fmc_adc_core_ctl_fmc_clk_oe_o => gpio_si570_oe_o,
fmc_adc_core_ctl_offset_dac_clr_n_o => gpio_dac_clr_n_o,
fmc_adc_core_ctl_man_bitslip_o => serdes_man_bitslip,
fmc_adc_core_sta_fsm_i => "000",
fmc_adc_core_sta_serdes_pll_i => locked_out,
fmc_adc_core_sta_serdes_synced_i => serdes_synced,
......@@ -562,13 +571,13 @@ begin
fmc_adc_core_post_samples_o => post_trig_value,
fmc_adc_core_samp_cnt_i => X"00000000",
fmc_adc_core_ch1_ssr_o => gpio_ssr_ch1_o,
fmc_adc_core_ch1_val_i => X"0000",
fmc_adc_core_ch1_val_i => sync_fifo_dout(15 downto 0),
fmc_adc_core_ch2_ssr_o => gpio_ssr_ch2_o,
fmc_adc_core_ch2_val_i => X"0000",
fmc_adc_core_ch2_val_i => sync_fifo_dout(31 downto 16),
fmc_adc_core_ch3_ssr_o => gpio_ssr_ch3_o,
fmc_adc_core_ch3_val_i => X"0000",
fmc_adc_core_ch3_val_i => sync_fifo_dout(47 downto 32),
fmc_adc_core_ch4_ssr_o => gpio_ssr_ch4_o,
fmc_adc_core_ch4_val_i => X"0000"
fmc_adc_core_ch4_val_i => sync_fifo_dout(63 downto 48)
);
------------------------------------------------------------------------------
......
hdl/spec/rtl/fmc_adc_100Ms_csr.vhd
View file @ d5592fa4
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/fmc_adc_100Ms_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Created : Fri Mar 4 14:20:32 2011
-- Created : Wed Mar 16 11:36:21 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -34,6 +34,8 @@ entity fmc_adc_100Ms_csr is
fmc_adc_core_ctl_fmc_clk_oe_o : out std_logic;
-- Port for BIT field: 'Offset DACs clear (active low)' in reg: 'Control register'
fmc_adc_core_ctl_offset_dac_clr_n_o : out std_logic;
-- Port for BIT field: 'Manual serdes bitslip' in reg: 'Control register'
fmc_adc_core_ctl_man_bitslip_o : out std_logic;
-- Port for std_logic_vector field: 'State machine status' in reg: 'Status register'
fmc_adc_core_sta_fsm_i : in std_logic_vector(2 downto 0);
-- Port for BIT field: 'SerDes PLL status' in reg: 'Status register'
......@@ -104,6 +106,7 @@ architecture syn of fmc_adc_100Ms_csr is
signal fmc_adc_core_ctl_fmc_clk_oe_int : std_logic ;
signal fmc_adc_core_ctl_offset_dac_clr_n_int : std_logic ;
signal fmc_adc_core_ctl_man_bitslip_int : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_sel_int : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_sel_sync0 : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_sel_sync1 : std_logic ;
......@@ -180,6 +183,7 @@ begin
fmc_adc_core_ctl_fsm_cmd_wr_o <= '0';
fmc_adc_core_ctl_fmc_clk_oe_int <= '0';
fmc_adc_core_ctl_offset_dac_clr_n_int <= '0';
fmc_adc_core_ctl_man_bitslip_int <= '0';
fmc_adc_core_trig_cfg_hw_trig_sel_int <= '0';
fmc_adc_core_trig_cfg_ext_trig_pol_int <= '0';
fmc_adc_core_trig_cfg_hw_trig_en_int <= '0';
......@@ -231,12 +235,13 @@ begin
fmc_adc_core_ctl_fsm_cmd_wr_o <= '1';
fmc_adc_core_ctl_fmc_clk_oe_int <= wrdata_reg(2);
fmc_adc_core_ctl_offset_dac_clr_n_int <= wrdata_reg(3);
fmc_adc_core_ctl_man_bitslip_int <= wrdata_reg(4);
else
rddata_reg(2) <= fmc_adc_core_ctl_fmc_clk_oe_int;
rddata_reg(3) <= fmc_adc_core_ctl_offset_dac_clr_n_int;
rddata_reg(4) <= fmc_adc_core_ctl_man_bitslip_int;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
......@@ -734,6 +739,8 @@ begin
fmc_adc_core_ctl_fmc_clk_oe_o <= fmc_adc_core_ctl_fmc_clk_oe_int;
-- Offset DACs clear (active low)
fmc_adc_core_ctl_offset_dac_clr_n_o <= fmc_adc_core_ctl_offset_dac_clr_n_int;
-- Manual serdes bitslip
fmc_adc_core_ctl_man_bitslip_o <= fmc_adc_core_ctl_man_bitslip_int;
-- State machine status
-- SerDes PLL status
-- SerDes synchronization status
......
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
View file @ d5592fa4
......@@ -31,7 +31,7 @@ library UNISIM;
use UNISIM.vcomponents.all;
entity spec_top is
entity spec_top_fmc_adc_100Ms is
generic(
g_SIMULATION : string := "FALSE";
g_CALIB_SOFT_IP : string := "TRUE");
......@@ -130,10 +130,10 @@ entity spec_top is
prsnt_m2c_n_i : in std_logic -- Mezzanine present (active low)
);
end spec_top;
end spec_top_fmc_adc_100Ms;
architecture rtl of spec_top is
architecture rtl of spec_top_fmc_adc_100Ms is
------------------------------------------------------------------------------
-- Components declaration
......@@ -574,6 +574,7 @@ architecture rtl of spec_top is
signal spi_sck_t : std_logic_vector(2 downto 0);
signal spi_din_t : std_logic_vector(2 downto 0);
signal spi_dout_t : std_logic_vector(2 downto 0);
signal spi_ss_t : std_logic_vector(7 downto 0);
begin
......@@ -751,15 +752,16 @@ begin
------------------------------------------------------------------------------
-- CSR wishbone bus slaves
-- 0 -> Carrier SPI master
-- 1 -> Carrier I2C master
-- 2 -> Carrier CSR
-- 3 -> UTC core
-- 4 -> Interrupt controller
-- 5 -> Mezzanine system managment I2C master
-- 6 -> Mezzanine SPI master
-- 7 -> Mezzanine I2C master
-- 8 -> Mezzanine ADC core
-- (0x00000 -> DMA configuration)
-- 0x10000 -> Carrier SPI master
-- 0x20000 -> Carrier I2C master
-- 0x30000 -> Carrier CSR
-- 0x40000 -> UTC core
-- 0x50000 -> Interrupt controller
-- 0x60000 -> Mezzanine system managment I2C master
-- 0x70000 -> Mezzanine SPI master
-- 0x80000 -> Mezzanine I2C master
-- 0x90000 -> Mezzanine ADC core
------------------------------------------------------------------------------
------------------------------------------------------------------------------
......@@ -861,14 +863,7 @@ begin
wb_ack_o => wb_ack_fmc_spi,
wb_err_o => open,
wb_int_o => open,
ss_pad_o(0) => spi_cs_adc_n_o,
ss_pad_o(1) => spi_cs_dac1_n_o,
ss_pad_o(2) => spi_cs_dac2_n_o,
ss_pad_o(3) => spi_cs_dac3_n_o,
ss_pad_o(4) => spi_cs_dac4_n_o,
ss_pad_o(5) => open,
ss_pad_o(6) => open,
ss_pad_o(7) => open,
ss_pad_o => spi_ss_t,
sclk_pad_o => spi_sck_o,
mosi_pad_o => spi_dout_o,
miso_pad_i => spi_din_t(2)
......@@ -877,8 +872,15 @@ begin
-- 32-bit word to byte address
wb_adr_fmc_spi <= wb_adr(2 downto 0) & "00";
-- Assign slave select lines
spi_cs_adc_n_o <= spi_ss_t(0);
spi_cs_dac1_n_o <= spi_ss_t(1);
spi_cs_dac2_n_o <= spi_ss_t(2);
spi_cs_dac3_n_o <= spi_ss_t(3);
spi_cs_dac4_n_o <= spi_ss_t(4);
-- Add some FF after the input pin to solve timing problem
p_fmc_spi: process (sys_clk_125)
p_fmc_spi : process (sys_clk_125)
begin
if rising_edge(sys_clk_125) then
if sys_rst_n = '0' then
......@@ -899,7 +901,7 @@ begin
ARST_LVL => '0')
port map (
wb_clk_i => sys_clk_125,
wb_rst_i => sys_rst_n,
wb_rst_i => sys_rst,
arst_i => '1',
wb_adr_i => wb_adr_fmc_i2c(2 downto 0),
wb_dat_i => wb_dat_o(7 downto 0),
......
hdl/spec/wb_gen/Makefile
View file @ d5592fa4
......@@ -2,7 +2,7 @@ WBGEN2=../../../../wbgen2/wishbone-gen/wbgen2
RTL=../rtl/
carrier_csr:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -C $@.h $@.wb
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -D $@.htm $@.wb
fmc_adc_100Ms_csr:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -C $@.h $@.wb
\ No newline at end of file
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -D $@.htm $@.wb
\ No newline at end of file
hdl/spec/wb_gen/fmc_adc_100Ms_csr.wb
View file @ d5592fa4
......@@ -34,6 +34,14 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Manual serdes bitslip";
prefix = "man_bitslip";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
......
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