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FMC ADC 100M 14b 4cha - Gateware
Commit e948330f authored by mcattin's avatar mcattin
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One multiple irq bit per irq source instead of a unique flag. 

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@88 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
parent 413ce60d
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Showing with 138 additions and 182 deletions
hdl/spec/rtl/irq_controller.vhd
View file @ e948330f
...@@ -64,23 +64,23 @@ architecture rtl of irq_controller is ...@@ -64,23 +64,23 @@ architecture rtl of irq_controller is
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
component irq_controller_regs component irq_controller_regs
port ( port (
rst_n_i : in std_logic; rst_n_i : in std_logic;
wb_clk_i : in std_logic; wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(1 downto 0); wb_addr_i : in std_logic_vector(1 downto 0);
wb_data_i : in std_logic_vector(31 downto 0); wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0); wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic; wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0); wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic; wb_stb_i : in std_logic;
wb_we_i : in std_logic; wb_we_i : in std_logic;
wb_ack_o : out std_logic; wb_ack_o : out std_logic;
irq_ctrl_status_mult_irq_o : out std_logic; irq_ctrl_multi_irq_o : out std_logic_vector(31 downto 0);
irq_ctrl_status_mult_irq_i : in std_logic; irq_ctrl_multi_irq_i : in std_logic_vector(31 downto 0);
irq_ctrl_status_mult_irq_load_o : out std_logic; irq_ctrl_multi_irq_load_o : out std_logic;
irq_ctrl_src_o : out std_logic_vector(31 downto 0); irq_ctrl_src_o : out std_logic_vector(31 downto 0);
irq_ctrl_src_i : in std_logic_vector(31 downto 0); irq_ctrl_src_i : in std_logic_vector(31 downto 0);
irq_ctrl_src_load_o : out std_logic; irq_ctrl_src_load_o : out std_logic;
irq_ctrl_en_mask_o : out std_logic_vector(31 downto 0) irq_ctrl_en_mask_o : out std_logic_vector(31 downto 0)
); );
end component irq_controller_regs; end component irq_controller_regs;
...@@ -94,10 +94,8 @@ architecture rtl of irq_controller is ...@@ -94,10 +94,8 @@ architecture rtl of irq_controller is
signal irq_src_rst : std_logic_vector(31 downto 0); signal irq_src_rst : std_logic_vector(31 downto 0);
signal irq_src_rst_en : std_logic; signal irq_src_rst_en : std_logic;
signal multi_irq : std_logic_vector(31 downto 0); signal multi_irq : std_logic_vector(31 downto 0);
signal multi_irq_or : std_logic_vector(32 downto 0); signal multi_irq_rst : std_logic_vector(31 downto 0);
signal multi_irq_rst : std_logic;
signal multi_irq_rst_en : std_logic; signal multi_irq_rst_en : std_logic;
signal multi_irq_flag : std_logic;
signal irq_p_or : std_logic_vector(32 downto 0); signal irq_p_or : std_logic_vector(32 downto 0);
...@@ -108,23 +106,23 @@ begin ...@@ -108,23 +106,23 @@ begin
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
cmp_irq_controller_regs : irq_controller_regs cmp_irq_controller_regs : irq_controller_regs
port map( port map(
rst_n_i => rst_n_i, rst_n_i => rst_n_i,
wb_clk_i => clk_i, wb_clk_i => clk_i,
wb_addr_i => wb_adr_i, wb_addr_i => wb_adr_i,
wb_data_i => wb_dat_i, wb_data_i => wb_dat_i,
wb_data_o => wb_dat_o, wb_data_o => wb_dat_o,
wb_cyc_i => wb_cyc_i, wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i, wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i, wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i, wb_we_i => wb_we_i,
wb_ack_o => wb_ack_o, wb_ack_o => wb_ack_o,
irq_ctrl_status_mult_irq_o => multi_irq_rst, irq_ctrl_multi_irq_o => multi_irq_rst,
irq_ctrl_status_mult_irq_load_o => multi_irq_rst_en, irq_ctrl_multi_irq_load_o => multi_irq_rst_en,
irq_ctrl_status_mult_irq_i => multi_irq_flag, irq_ctrl_multi_irq_i => multi_irq,
irq_ctrl_src_o => irq_src_rst, irq_ctrl_src_o => irq_src_rst,
irq_ctrl_src_i => irq_pending, irq_ctrl_src_i => irq_pending,
irq_ctrl_src_load_o => irq_src_rst_en, irq_ctrl_src_load_o => irq_src_rst_en,
irq_ctrl_en_mask_o => irq_en_mask irq_ctrl_en_mask_o => irq_en_mask
); );
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
...@@ -159,25 +157,19 @@ begin ...@@ -159,25 +157,19 @@ begin
multi_irq(I) <= '0'; multi_irq(I) <= '0';
elsif irq_src_p_i(I) = '1' and irq_pending(I) = '1' then elsif irq_src_p_i(I) = '1' and irq_pending(I) = '1' then
multi_irq(I) <= '1'; multi_irq(I) <= '1';
elsif multi_irq_rst_en = '1' and multi_irq_rst = '1' then elsif multi_irq_rst_en = '1' and multi_irq_rst(I) = '1' then
multi_irq(I) <= '0'; multi_irq(I) <= '0';
end if; end if;
end loop; -- I end loop; -- I
end if; end if;
end process p_multi_irq_detect; end process p_multi_irq_detect;
multi_irq_or(0) <= '0';
l_multi_irq_flag : for I in 0 to multi_irq'length-2 generate
multi_irq_or(I+1) <= multi_irq_or(I) or multi_irq(I);
end generate l_multi_irq_flag;
multi_irq_flag <= multi_irq_or(32);
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Generate IRQ output pulse -- Generate IRQ output pulse
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
irq_p_or(0) <= '0'; irq_p_or(0) <= '0';
l_irq_out_pulse: for I in 0 to irq_p_or'length-2 generate l_irq_out_pulse : for I in 0 to irq_src_p_i'length-1 generate
irq_p_or(I+1) <= irq_p_or(I) or irq_src_p_i(I); irq_p_or(I+1) <= irq_p_or(I) or (irq_src_p_i(I) and irq_en_mask(I));
end generate l_irq_out_pulse; end generate l_irq_out_pulse;
p_irq_out_pulse : process (clk_i) p_irq_out_pulse : process (clk_i)
......
hdl/spec/rtl/irq_controller_regs.vhd
View file @ e948330f
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : ../rtl/irq_controller_regs.vhd -- File : ../rtl/irq_controller_regs.vhd
-- Author : auto-generated by wbgen2 from irq_controller_regs.wb -- Author : auto-generated by wbgen2 from irq_controller_regs.wb
-- Created : Fri Nov 18 16:47:40 2011 -- Created : Mon Nov 21 18:08:05 2011
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE irq_controller_regs.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE irq_controller_regs.wb
...@@ -26,10 +26,10 @@ entity irq_controller_regs is ...@@ -26,10 +26,10 @@ entity irq_controller_regs is
wb_stb_i : in std_logic; wb_stb_i : in std_logic;
wb_we_i : in std_logic; wb_we_i : in std_logic;
wb_ack_o : out std_logic; wb_ack_o : out std_logic;
-- Ports for BIT field: 'Multiple interrupt' in reg: 'Interrupt controller status register' -- Port for std_logic_vector field: 'Multiple interrupt' in reg: 'Multiple interrupt register'
irq_ctrl_status_mult_irq_o : out std_logic; irq_ctrl_multi_irq_o : out std_logic_vector(31 downto 0);
irq_ctrl_status_mult_irq_i : in std_logic; irq_ctrl_multi_irq_i : in std_logic_vector(31 downto 0);
irq_ctrl_status_mult_irq_load_o : out std_logic; irq_ctrl_multi_irq_load_o : out std_logic;
-- Port for std_logic_vector field: 'Interrupt sources' in reg: 'Interrupt sources register ' -- Port for std_logic_vector field: 'Interrupt sources' in reg: 'Interrupt sources register '
irq_ctrl_src_o : out std_logic_vector(31 downto 0); irq_ctrl_src_o : out std_logic_vector(31 downto 0);
irq_ctrl_src_i : in std_logic_vector(31 downto 0); irq_ctrl_src_i : in std_logic_vector(31 downto 0);
...@@ -71,7 +71,7 @@ begin ...@@ -71,7 +71,7 @@ begin
ack_sreg <= "0000000000"; ack_sreg <= "0000000000";
ack_in_progress <= '0'; ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000"; rddata_reg <= "00000000000000000000000000000000";
irq_ctrl_status_mult_irq_load_o <= '0'; irq_ctrl_multi_irq_load_o <= '0';
irq_ctrl_src_load_o <= '0'; irq_ctrl_src_load_o <= '0';
irq_ctrl_en_mask_int <= "00000000000000000000000000000000"; irq_ctrl_en_mask_int <= "00000000000000000000000000000000";
elsif rising_edge(bus_clock_int) then elsif rising_edge(bus_clock_int) then
...@@ -80,11 +80,11 @@ begin ...@@ -80,11 +80,11 @@ begin
ack_sreg(9) <= '0'; ack_sreg(9) <= '0';
if (ack_in_progress = '1') then if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then if (ack_sreg(0) = '1') then
irq_ctrl_status_mult_irq_load_o <= '0'; irq_ctrl_multi_irq_load_o <= '0';
irq_ctrl_src_load_o <= '0'; irq_ctrl_src_load_o <= '0';
ack_in_progress <= '0'; ack_in_progress <= '0';
else else
irq_ctrl_status_mult_irq_load_o <= '0'; irq_ctrl_multi_irq_load_o <= '0';
irq_ctrl_src_load_o <= '0'; irq_ctrl_src_load_o <= '0';
end if; end if;
else else
...@@ -92,40 +92,9 @@ begin ...@@ -92,40 +92,9 @@ begin
case rwaddr_reg(1 downto 0) is case rwaddr_reg(1 downto 0) is
when "00" => when "00" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
irq_ctrl_status_mult_irq_load_o <= '1'; irq_ctrl_multi_irq_load_o <= '1';
else else
rddata_reg(0) <= irq_ctrl_status_mult_irq_i; rddata_reg(31 downto 0) <= irq_ctrl_multi_irq_i;
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if; end if;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
...@@ -159,7 +128,7 @@ begin ...@@ -159,7 +128,7 @@ begin
-- Drive the data output bus -- Drive the data output bus
wb_data_o <= rddata_reg; wb_data_o <= rddata_reg;
-- Multiple interrupt -- Multiple interrupt
irq_ctrl_status_mult_irq_o <= wrdata_reg(0); irq_ctrl_multi_irq_o <= wrdata_reg(31 downto 0);
-- Interrupt sources -- Interrupt sources
irq_ctrl_src_o <= wrdata_reg(31 downto 0); irq_ctrl_src_o <= wrdata_reg(31 downto 0);
-- Interrupt enable mask -- Interrupt enable mask
......
hdl/spec/wb_gen/irq_controller_regs.h
View file @ e948330f
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
* File : irq_controller_regs.h * File : irq_controller_regs.h
* Author : auto-generated by wbgen2 from irq_controller_regs.wb * Author : auto-generated by wbgen2 from irq_controller_regs.wb
* Created : Fri Nov 18 16:47:40 2011 * Created : Mon Nov 21 18:08:05 2011
* Standard : ANSI C * Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE irq_controller_regs.wb THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE irq_controller_regs.wb
...@@ -31,18 +31,15 @@ ...@@ -31,18 +31,15 @@
#endif #endif
/* definitions for register: Interrupt controller status register */ /* definitions for register: Multiple interrupt register */
/* definitions for field: Multiple interrupt in reg: Interrupt controller status register */
#define IRQ_CTRL_STATUS_MULT_IRQ WBGEN2_GEN_MASK(0, 1)
/* definitions for register: Interrupt sources register */ /* definitions for register: Interrupt sources register */
/* definitions for register: Interrupt enable mask register */ /* definitions for register: Interrupt enable mask register */
PACKED struct IRQ_CTRL_WB { PACKED struct IRQ_CTRL_WB {
/* [0x0]: REG Interrupt controller status register */ /* [0x0]: REG Multiple interrupt register */
uint32_t STATUS; uint32_t MULTI_IRQ;
/* [0x4]: REG Interrupt sources register */ /* [0x4]: REG Interrupt sources register */
uint32_t SRC; uint32_t SRC;
/* [0x8]: REG Interrupt enable mask register */ /* [0x8]: REG Interrupt enable mask register */
......
hdl/spec/wb_gen/irq_controller_regs.htm
View file @ e948330f
...@@ -34,7 +34,7 @@ ...@@ -34,7 +34,7 @@
<span style="margin-left: 0px; ">1. <A href="#sect_1_0">Memory map summary</a></span><br/> <span style="margin-left: 0px; ">1. <A href="#sect_1_0">Memory map summary</a></span><br/>
<span style="margin-left: 0px; ">2. <A href="#sect_2_0">HDL symbol</a></span><br/> <span style="margin-left: 0px; ">2. <A href="#sect_2_0">HDL symbol</a></span><br/>
<span style="margin-left: 0px; ">3. <A href="#sect_3_0">Register description</a></span><br/> <span style="margin-left: 0px; ">3. <A href="#sect_3_0">Register description</a></span><br/>
<span style="margin-left: 20px; ">3.1. <A href="#sect_3_1">Interrupt controller status register</a></span><br/> <span style="margin-left: 20px; ">3.1. <A href="#sect_3_1">Multiple interrupt register</a></span><br/>
<span style="margin-left: 20px; ">3.2. <A href="#sect_3_2">Interrupt sources register </a></span><br/> <span style="margin-left: 20px; ">3.2. <A href="#sect_3_2">Interrupt sources register </a></span><br/>
<span style="margin-left: 20px; ">3.3. <A href="#sect_3_3">Interrupt enable mask register</a></span><br/> <span style="margin-left: 20px; ">3.3. <A href="#sect_3_3">Interrupt enable mask register</a></span><br/>
<h3><a name="sect_1_0">1. Memory map summary</a></h3> <h3><a name="sect_1_0">1. Memory map summary</a></h3>
...@@ -64,13 +64,13 @@ C prefix ...@@ -64,13 +64,13 @@ C prefix
REG REG
</td> </td>
<td > <td >
<A href="#STATUS">Interrupt controller status register</a> <A href="#MULTI_IRQ">Multiple interrupt register</a>
</td> </td>
<td class="td_code"> <td class="td_code">
irq_ctrl_status irq_ctrl_multi_irq
</td> </td>
<td class="td_code"> <td class="td_code">
STATUS MULTI_IRQ
</td> </td>
</tr> </tr>
<tr class="tr_even"> <tr class="tr_even">
...@@ -122,7 +122,7 @@ rst_n_i ...@@ -122,7 +122,7 @@ rst_n_i
</td> </td>
<td class="td_pblock_right"> <td class="td_pblock_right">
<b>Interrupt controller status register:</b> <b>Multiple interrupt register:</b>
</td> </td>
<td class="td_arrow_right"> <td class="td_arrow_right">
...@@ -139,10 +139,10 @@ wb_clk_i ...@@ -139,10 +139,10 @@ wb_clk_i
</td> </td>
<td class="td_pblock_right"> <td class="td_pblock_right">
irq_ctrl_status_mult_irq_o irq_ctrl_multi_irq_o[31:0]
</td> </td>
<td class="td_arrow_right"> <td class="td_arrow_right">
&rarr; &rArr;
</td> </td>
</tr> </tr>
<tr> <tr>
...@@ -156,10 +156,10 @@ wb_addr_i[1:0] ...@@ -156,10 +156,10 @@ wb_addr_i[1:0]
</td> </td>
<td class="td_pblock_right"> <td class="td_pblock_right">
irq_ctrl_status_mult_irq_i irq_ctrl_multi_irq_i[31:0]
</td> </td>
<td class="td_arrow_right"> <td class="td_arrow_right">
&larr; &lArr;
</td> </td>
</tr> </tr>
<tr> <tr>
...@@ -173,7 +173,7 @@ wb_data_i[31:0] ...@@ -173,7 +173,7 @@ wb_data_i[31:0]
</td> </td>
<td class="td_pblock_right"> <td class="td_pblock_right">
irq_ctrl_status_mult_irq_load_o irq_ctrl_multi_irq_load_o
</td> </td>
<td class="td_arrow_right"> <td class="td_arrow_right">
&rarr; &rarr;
...@@ -318,15 +318,15 @@ irq_ctrl_en_mask_o[31:0] ...@@ -318,15 +318,15 @@ irq_ctrl_en_mask_o[31:0]
</table> </table>
<h3><a name="sect_3_0">3. Register description</a></h3> <h3><a name="sect_3_0">3. Register description</a></h3>
<a name="STATUS"></a> <a name="MULTI_IRQ"></a>
<h3><a name="sect_3_1">3.1. Interrupt controller status register</a></h3> <h3><a name="sect_3_1">3.1. Multiple interrupt register</a></h3>
<table cellpadding=0 cellspacing=0 border=0> <table cellpadding=0 cellspacing=0 border=0>
<tr> <tr>
<td > <td >
<b>HW prefix: </b> <b>HW prefix: </b>
</td> </td>
<td class="td_code"> <td class="td_code">
irq_ctrl_status irq_ctrl_multi_irq
</td> </td>
</tr> </tr>
<tr> <tr>
...@@ -342,7 +342,7 @@ irq_ctrl_status ...@@ -342,7 +342,7 @@ irq_ctrl_status
<b>C prefix: </b> <b>C prefix: </b>
</td> </td>
<td class="td_code"> <td class="td_code">
STATUS MULTI_IRQ
</td> </td>
</tr> </tr>
<tr> <tr>
...@@ -355,7 +355,7 @@ STATUS ...@@ -355,7 +355,7 @@ STATUS
</tr> </tr>
</table> </table>
<p> <p>
Multiple interrupts occurs before irq source is read.<br>Write '1' to clear a bit.
</p> </p>
<table cellpadding=0 cellspacing=0 border=0> <table cellpadding=0 cellspacing=0 border=0>
<tr> <tr>
...@@ -385,29 +385,29 @@ STATUS ...@@ -385,29 +385,29 @@ STATUS
</td> </td>
</tr> </tr>
<tr> <tr>
<td class="td_unused"> <td style="border: solid 1px black;" colspan=8 class="td_field">
- MULTI_IRQ[31:24]
</td> </td>
<td class="td_unused"> <td >
-
</td> </td>
<td class="td_unused"> <td >
-
</td> </td>
<td class="td_unused"> <td >
-
</td> </td>
<td class="td_unused"> <td >
-
</td> </td>
<td class="td_unused"> <td >
-
</td> </td>
<td class="td_unused"> <td >
-
</td> </td>
<td class="td_unused"> <td >
-
</td> </td>
</tr> </tr>
</table> </table>
...@@ -439,29 +439,29 @@ STATUS ...@@ -439,29 +439,29 @@ STATUS
</td> </td>
</tr> </tr>
<tr> <tr>
<td class="td_unused"> <td style="border: solid 1px black;" colspan=8 class="td_field">
- MULTI_IRQ[23:16]
</td> </td>
<td class="td_unused"> <td >
-
</td> </td>
<td class="td_unused"> <td >
-
</td> </td>
<td class="td_unused"> <td >
-
</td> </td>
<td class="td_unused"> <td >
-
</td> </td>
<td class="td_unused"> <td >
-
</td> </td>
<td class="td_unused"> <td >
-
</td> </td>
<td class="td_unused"> <td >
-
</td> </td>
</tr> </tr>
</table> </table>
...@@ -493,29 +493,29 @@ STATUS ...@@ -493,29 +493,29 @@ STATUS
</td> </td>
</tr> </tr>
<tr> <tr>
<td class="td_unused"> <td style="border: solid 1px black;" colspan=8 class="td_field">
- MULTI_IRQ[15:8]
</td> </td>
<td class="td_unused"> <td >
-
</td> </td>
<td class="td_unused"> <td >
-
</td> </td>
<td class="td_unused"> <td >
-
</td> </td>
<td class="td_unused"> <td >
-
</td> </td>
<td class="td_unused"> <td >
-
</td> </td>
<td class="td_unused"> <td >
-
</td> </td>
<td class="td_unused"> <td >
-
</td> </td>
</tr> </tr>
</table> </table>
...@@ -547,37 +547,36 @@ STATUS ...@@ -547,37 +547,36 @@ STATUS
</td> </td>
</tr> </tr>
<tr> <tr>
<td class="td_unused"> <td style="border: solid 1px black;" colspan=8 class="td_field">
- MULTI_IRQ[7:0]
</td> </td>
<td class="td_unused"> <td >
-
</td> </td>
<td class="td_unused"> <td >
-
</td> </td>
<td class="td_unused"> <td >
-
</td> </td>
<td class="td_unused"> <td >
-
</td> </td>
<td class="td_unused"> <td >
-
</td> </td>
<td class="td_unused"> <td >
-
</td> </td>
<td style="border: solid 1px black;" colspan=1 class="td_field"> <td >
MULT_IRQ
</td> </td>
</tr> </tr>
</table> </table>
<ul> <ul>
<li><b> <li><b>
MULT_IRQ MULTI_IRQ
</b>[<i>read/write</i>]: Multiple interrupt </b>[<i>read/write</i>]: Multiple interrupt
<br>Multiple interrupts occurs before irq source is read.
</ul> </ul>
<a name="SRC"></a> <a name="SRC"></a>
<h3><a name="sect_3_2">3.2. Interrupt sources register </a></h3> <h3><a name="sect_3_2">3.2. Interrupt sources register </a></h3>
......
hdl/spec/wb_gen/irq_controller_regs.wb
View file @ e948330f
...@@ -6,15 +6,14 @@ peripheral { ...@@ -6,15 +6,14 @@ peripheral {
prefix = "irq_ctrl"; prefix = "irq_ctrl";
reg { reg {
name = "Interrupt controller status register"; name = "Multiple interrupt register";
description = ""; description = "Multiple interrupts occurs before irq source is read.\nWrite '1' to clear a bit.";
prefix = "status"; prefix = "multi_irq";
field { field {
name = "Multiple interrupt"; name = "Multiple interrupt";
description = "Multiple interrupts occurs before irq source is read."; type = SLV;
prefix = "mult_irq"; size = 32;
type = BIT;
load = LOAD_EXT; load = LOAD_EXT;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_WRITE; access_dev = READ_WRITE;
......
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