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FMC ADC 100M 14b 4cha - Gateware
Commit ea1ddd6e authored by mcattin's avatar mcattin
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ddr ctrl wb address in 32-bit words (instead of byte), adc data sync on fr_n… 

ddr ctrl wb address in 32-bit words (instead of byte), adc data sync on fr_n (due to inverted signal on adc fmc pcb).

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@47 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
parent ec0dc339
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Showing with 23 additions and 17 deletions
hdl/spec/ise_project/iseconfig/spec_top.xreport
View file @ ea1ddd6e
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2011-03-16T19:14:15</DateModified>
<DateModified>2011-03-21T12:53:12</DateModified>
<ModuleName>spec_top_fmc_adc_100Ms</ModuleName>
<SummaryTimeStamp>2011-03-09T11:19:20</SummaryTimeStamp>
<SavedFilePath>/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/ise_project/iseconfig/spec_top.xreport</SavedFilePath>
......
hdl/spec/ise_project/spec_fmc_adc_100Ms.gise
View file @ ea1ddd6e
......@@ -137,7 +137,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1300298475" xil_pn:in_ck="-6698355625770614420" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8197382171204319838" xil_pn:start_ts="1300298258">
<transform xil_pn:end_ts="1300706177" xil_pn:in_ck="-6698355625770614420" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8197382171204319838" xil_pn:start_ts="1300705954">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -155,11 +155,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1299776415" xil_pn:in_ck="2162529744943951648" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-4337831395208791850" xil_pn:start_ts="1299776415">
<transform xil_pn:end_ts="1300698519" xil_pn:in_ck="2162529744943951648" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-4337831395208791850" xil_pn:start_ts="1300698519">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1300298500" xil_pn:in_ck="6806541686375937701" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7643830140109020653" xil_pn:start_ts="1300298475">
<transform xil_pn:end_ts="1300706204" xil_pn:in_ck="6806541686375937701" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7643830140109020653" xil_pn:start_ts="1300706177">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -169,7 +169,7 @@
<outfile xil_pn:name="spec_top_fmc_adc_100Ms.ngd"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1300298873" xil_pn:in_ck="8313289856678850416" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-525288356180264082" xil_pn:start_ts="1300298500">
<transform xil_pn:end_ts="1300706615" xil_pn:in_ck="8313289856678850416" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-525288356180264082" xil_pn:start_ts="1300706204">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -183,7 +183,7 @@
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_summary.xml"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1300299119" xil_pn:in_ck="-1808195220703275450" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="5879947102106257248" xil_pn:start_ts="1300298873">
<transform xil_pn:end_ts="1300706876" xil_pn:in_ck="-1808195220703275450" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="5879947102106257248" xil_pn:start_ts="1300706615">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -198,7 +198,7 @@
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_pad.txt"/>
<outfile xil_pn:name="spec_top_fmc_adc_100Ms_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1300299190" xil_pn:in_ck="1401670161614903244" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="1554780821134721645" xil_pn:start_ts="1300299119">
<transform xil_pn:end_ts="1300706942" xil_pn:in_ck="1401670161614903244" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="1554780821134721645" xil_pn:start_ts="1300706876">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -211,7 +211,14 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1300299119" xil_pn:in_ck="8313289856678850284" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="4435602129065547965" xil_pn:start_ts="1300299079">
<transform xil_pn:end_ts="1300690913" xil_pn:in_ck="1401670161614890390" xil_pn:name="TRAN_impactProgrammingTool" xil_pn:prop_ck="2682241697568822907" xil_pn:start_ts="1300690912">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputRemoved"/>
</transform>
<transform xil_pn:end_ts="1300706876" xil_pn:in_ck="8313289856678850284" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="4435602129065547965" xil_pn:start_ts="1300706835">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/spec/rtl/fmc_adc_100Ms_core.vhd
View file @ ea1ddd6e
......@@ -509,7 +509,7 @@ begin
-- Generate bitslip and synced signal
if(bitslip_sreg(bitslip_sreg'left) = '1') then
if(serdes_out_fr /= "11110000") then
if(serdes_out_fr /= "00001111") then -- use fr_n pattern (fr_p and fr_n are swapped on the adc mezzanine)
serdes_auto_bitslip <= '1';
serdes_synced <= '0';
else
......
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
View file @ ea1ddd6e
......@@ -1028,7 +1028,7 @@ begin
wb0_cyc_i => wb_ddr_cyc,
wb0_stb_i => wb_ddr_stb,
wb0_we_i => wb_ddr_we,
wb0_addr_i => wb_ddr_adr(29 downto 0),
wb0_addr_i => wb_ddr_adr(27 downto 0),
wb0_data_i => wb_ddr_dat_o,
wb0_data_o => wb_ddr_dat_i,
wb0_ack_o => wb_ddr_ack,
......@@ -1039,15 +1039,12 @@ begin
wb1_cyc_i => wb_dma_cyc,
wb1_stb_i => wb_dma_stb,
wb1_we_i => wb_dma_we,
wb1_addr_i => wb_dma_adr_ddr,
wb1_addr_i => wb_dma_adr(27 downto 0),
wb1_data_i => wb_dma_dat_o,
wb1_data_o => wb_dma_dat_i,
wb1_ack_o => wb_dma_ack,
wb1_stall_o => wb_dma_stall);
-- 32-bit word to byte address
wb_dma_adr_ddr <= wb_dma_adr(27 downto 0) & "00";
------------------------------------------------------------------------------
-- Assign unused outputs
------------------------------------------------------------------------------
......
hdl/spec/spec_top_fmc_adc_100Ms.ucf
View file @ ea1ddd6e
......@@ -208,10 +208,12 @@ NET "adc_dco_n_i" IOSTANDARD = "LVDS_25";
NET "adc_dco_p_i" LOC = Y11; # LA00_P
NET "adc_dco_p_i" IOSTANDARD = "LVDS_25";
NET "adc_fr_p_i" LOC = AA12; # LA01_N
NET "adc_fr_p_i" IOSTANDARD = "LVDS_25";
NET "adc_fr_n_i" LOC = AB12; # LA01_P
# fr_p and fr_n are swapped compared to the FMC ADC schematics
# this is to be coherent in the hdl design
NET "adc_fr_n_i" LOC = AB12; # LA01_N
NET "adc_fr_n_i" IOSTANDARD = "LVDS_25";
NET "adc_fr_p_i" LOC = AA12; # LA01_P
NET "adc_fr_p_i" IOSTANDARD = "LVDS_25";
NET "adc_outa_n_i[0]" LOC = AB4; # LA14_N
NET "adc_outa_n_i[0]" IOSTANDARD = "LVDS_25";
......
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