FMC ADC 100M 14b 4cha - Gateware Release 2.0 for SPEC
Gateware
For use on SPEC carrier: spec-fmc-adc-v2.0.bin
Memory map
Documentation
The documentation for release 2.0 is being updated.
Meanwhile please refer to the release 1.1
documentation
Sources
All components correspond to the revisions with Tag "spec-fmc-adc-v2.0" in the repositories enumerated below.
Release date
- 29 July 2013
Release notes
1.0*
- Implements SDB (Self Describing Bus) to enumerate the devices that have been synthetized in the current design.
- Does not implement White Rabbit connectivity.
- Only available on SPEC FMC carrier.
1.1*
- Fix bug in interrupt controller:
Was setting the interrupt source bits regardless of the interrupt mask.
Now a source bit is set only if the corresponding mask bit is set. - Fix bug in ddr controller (ddr3-sp6-core repo):
In some conditions, the ddr controller wasn't writing the last word to memory.
This was preventing acq_end interrupt generation.
2.0*
- Fix bug in pre/post_trig_done signals generation.
- Update wbgen wishbone interfaces (port name change).
- Change utc core name into timetag core.
- Takes the adc data for trigger threshold after offset/gain correction block.
- Move mezzanine related wb cores to a separate module.
- Rename top level fmc slot ports to be compatible with the svec (2 fmc slots).
- Change spec mapping to fit the svec mapping.
- Change serdes pll feedback.
- Add a software reset register to reset the mezzanine related cores.
- [ddr core] Fix wishbone interface to ignore stb if cyc is '0'.
Matthieu Cattin - July 2013