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FMC ADC 100M 14b 4cha - Testing
Commit 05d76879 authored by Matthieu Cattin's avatar Matthieu Cattin
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eic, vic: Add eic and vic register maps, add vic class.

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test/fmcadc100m14b4cha/python/dma_eic_regs.py 0 → 100644
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#! /usr/bin/env python
# coding: utf8
# Copyright CERN, 2012
# Author: Matthieu Cattin (CERN)
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
# Last modifications: 8/5/2012
# GN4124 DMA enhanced interrupt controller registers
DMA_EIC_REGS=['DMA EIC registers', {
'IDR':[0x00, 'Interrupt disable', {
'DMA_END':[0, 'End of DMA transfer', 0x1],
'DMA_ERR':[1, 'Error in DMA transfer', 0x1],
'RESERVED':[2, 'Reserved', 0x3FFFFFFF]}],
'IER':[0x04, 'Interrupt enable', {
'DMA_END':[0, 'End of DMA transfer', 0x1],
'DMA_ERR':[1, 'Error in DMA transfer', 0x1],
'RESERVED':[2, 'Reserved', 0x3FFFFFFF]}],
'IMR':[0x08, 'Interrupt enable mask', {
'DMA_END':[0, 'End of DMA transfer', 0x1],
'DMA_ERR':[1, 'Error in DMA transfer', 0x1],
'RESERVED':[2, 'Reserved', 0x3FFFFFFF]}],
'ISR':[0x0C, 'Interrupt status', {
'DMA_END':[0, 'End of DMA transfer', 0x1],
'DMA_ERR':[1, 'Error in DMA transfer', 0x1],
'RESERVED':[2, 'Reserved', 0x3FFFFFFF]}]
}]
test/fmcadc100m14b4cha/python/fmc_adc_eic_regs.py 0 → 100644
View file @ 05d76879
#! /usr/bin/env python
# coding: utf8
# Copyright CERN, 2012
# Author: Matthieu Cattin (CERN)
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
# Last modifications: 8/5/2012
# fmc-adc enhanced interrupt controller (eic) registers
FMC_ADC_EIC_REGS=['FMC-ADC EIC registers', {
'IDR':[0x00, 'Interrupt disbale', {
'TRIG':[0, 'Acquisition triggered', 0x1],
'ACQ_END':[1, 'Acquisition finished', 0x1],
'RESERVED':[2, 'Reserved', 0x3FFFFFFF]}],
'IER':[0x04, 'Interrupt enable', {
'TRIG':[0, 'Acquisition triggered', 0x1],
'ACQ_END':[1, 'Acquisition finished', 0x1],
'RESERVED':[2, 'Reserved', 0x3FFFFFFF]}],
'IMR':[0x08, 'Interrupt enable mask', {
'TRIG':[0, 'Acquisition triggered', 0x1],
'ACQ_END':[1, 'Acquisition finished', 0x1],
'RESERVED':[2, 'Reserved', 0x3FFFFFFF]}],
'ISR':[0x0C, 'Interrupt status', {
'TRIG':[0, 'Acquisition triggered', 0x1],
'ACQ_END':[1, 'Acquisition finished', 0x1],
'RESERVED':[2, 'Reserved', 0x3FFFFFFF]}]
}]
test/fmcadc100m14b4cha/python/vic.py 0 → 100644
View file @ 05d76879
#! /usr/bin/env python
# coding: utf8
# Copyright CERN, 2012
# Author: Matthieu Cattin (CERN)
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
# Last modifications: 8/5/2012
# Import standard modules
import sys
import time
import random
import math
# Import specific modules
#import rr
from csr import *
# Import register maps
from vic_regs import *
# Class to access VIC (Vectored Interrupt Controller)
class VicOperationError(Exception):
def __init__(self, msg):
self.msg = msg
def __str__(self):
return ("VIC: %s" %(self.msg))
class CVic:
# Interrupt vector table start address offset
IVT_ADDR = 0x80
#======================================================================
# Class initialisation
def __init__(self, bus, base_address):
self.bus = bus
self.base_address = base_address
# Objects declaration
self.vic = CCSR(self.bus, self.base_address, VIC_REGS)
def print_regs(self):
self.vic.print_reg_map()
def print_ivt(self):
print "\nInterrupt vector table:"
print "------+-------------------------------------------"
print " vect | address"
print "------+-------------------------------------------"
for i in range(32):
val = self.bus.iread(0, self.base_address + self.IVT_ADDR + (i*4), 4)
print " %02d | 0x%08X" % (i, val)
def enable_module(self):
self.vic.set_field('CTL', 'EN', 1)
def disable_module(self):
self.vic.set_field('CTL', 'EN', 0)
def set_polarity(self, pol):
self.vic.set_field('CTL', 'POL', pol)
def enable_emu_edge(self, length=1000):
self.vic.set_field('CTL', 'EMU_EDGE', 1)
self.vic.set_field('CTL', 'EMU_LEN', length)
def disable_emu_edge(self):
self.vic.set_field('CTL', 'EMU_EDGE', 0)
def enable_int(self, int_number):
self.vic.set_reg('IER', 1 << int_number)
def disbale_int(self, int_number):
self.vic.set_reg('IDR', 1 << int_number)
def get_raw_int_status(self):
return self.vic.get_reg('RISR')
def get_int_enable_mask(self):
return self.vic.get_reg('IMR')
def get_int_vector_addr(self):
return self.vic.get_reg('VAR')
def sw_int(self, int_number):
self.vic.set_reg('SWIR', 1 << int_number)
def int_ack(self):
self.vic.set_reg('EOIR', 0x0)
def get_vector_addr(self, vect):
return self.bus.iread(0, self.base_address + self.IVT_ADDR + (vect*4), 4)
# TODO -> set vector table with custom vector addresses
test/fmcadc100m14b4cha/python/vic_regs.py 0 → 100644
View file @ 05d76879
#! /usr/bin/env python
# coding: utf8
# Copyright CERN, 2012
# Author: Matthieu Cattin (CERN)
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
# Last modifications: 8/5/2012
# Vectored interrupt controller registers
VIC_REGS=['VIC registers', {
'CTL':[0x00, 'VIC control', {
'EN':[0, 'Enable VIC', 0x1],
'POL':[1, 'Output polaritity (0=low, 1=high)', 0x1],
'EMU_EDGE':[2, 'Emulate edge sensitive output', 0x1],
'EMU_LEN':[3, 'Emulated edge pulse length timer', 0xFFFF],
'RESERVED':[19, 'Reserved', 0xFFF]}],
'RISR':[0x04, 'Raw interrupt status', {}],
'IER':[0x08, 'Interrupt enable', {}],
'IDR':[0x0C, 'Interrupt disable', {}],
'IMR':[0x10, 'Interrupt enable mask', {}],
'VAR':[0x14, 'Vector address', {}],
'SWIR':[0x18, 'Software interrupt', {}],
'EOIR':[0x1C, 'End of interrupt acknowledge', {}]
}]
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