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FMC ADC 100M 14b 4cha - Testing
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FMC ADC 100M 14b 4cha - Testing
Commits
4c03d466
Commit
4c03d466
authored
Jul 19, 2013
by
Matthieu Cattin
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fmc_adc: Fix returned data order.
Was returning two channels per row.
parent
7f67d59f
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-1
fmc_adc.py
test/fmcadc100m14b4cha/python/fmc_adc.py
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test/fmcadc100m14b4cha/python/fmc_adc.py
View file @
4c03d466
...
...
@@ -891,14 +891,18 @@ class CFmcAdc100m:
# carrier_addr and length are in 32-bit word
def
get_data
(
self
,
carrier_addr
,
length
):
ret
=
[]
data
=
[]
cc
=
self
.
bus
.
iwrite
(
0
,
self
.
DDR_ADR_ADDR
,
4
,
carrier_addr
)
#print('[get_data] write: addr=0x%.8X cc=%d'%(self.DDR_ADR_ADDR, cc))
for
i
in
range
(
length
):
#adr_cnt_b = self.bus.iread(0, self.DDR_ADR_ADDR, 4)
ret
.
append
(
self
.
bus
.
iread
(
0
,
self
.
DDR_DAT_ADDR
,
4
))
data
.
append
(
self
.
bus
.
iread
(
0
,
self
.
DDR_DAT_ADDR
,
4
))
#print('[get_data] read: addr=0x%.9X i=%d'%(self.DDR_DAT_ADDR, i))
#adr_cnt = self.bus.iread(0, self.DDR_ADR_ADDR, 4)
#print('[get_data] address counter: before=0x%.8X after=0x%.8X'%(adr_cnt_b, adr_cnt))
for
i
in
range
(
length
/
4
):
ret
.
append
(
data
[
i
]
&
0xFFFF
)
ret
.
append
(
data
[
i
]
>>
16
)
return
ret
# Write data to DDR
...
...
Write
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