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FMC ADC 100M 14b 4cha - Testing
Commit 7f67d59f authored by Matthieu Cattin's avatar Matthieu Cattin
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fmc_adc: Add debug features to svec get/put data methods.

parent 6c18bc6c
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test/fmcadc100m14b4cha/python/fmc_adc.py
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......@@ -891,9 +891,15 @@ class CFmcAdc100m:
# carrier_addr and length are in 32-bit word
def get_data(self, carrier_addr, length):
ret = []
self.bus.iwrite(0, self.DDR_ADR_ADDR, 4, carrier_addr)
cc = self.bus.iwrite(0, self.DDR_ADR_ADDR, 4, carrier_addr)
#print('[get_data] write: addr=0x%.8X cc=%d'%(self.DDR_ADR_ADDR, cc))
for i in range(length):
#adr_cnt_b = self.bus.iread(0, self.DDR_ADR_ADDR, 4)
ret.append(self.bus.iread(0, self.DDR_DAT_ADDR, 4))
#print('[get_data] read: addr=0x%.9X i=%d'%(self.DDR_DAT_ADDR, i))
#adr_cnt = self.bus.iread(0, self.DDR_ADR_ADDR, 4)
#print('[get_data] address counter: before=0x%.8X after=0x%.8X'%(adr_cnt_b, adr_cnt))
return ret
# Write data to DDR
# carrier_addr is in 32-bit word
......@@ -901,7 +907,11 @@ class CFmcAdc100m:
def put_data(self, carrier_addr, data):
self.bus.iwrite(0, self.DDR_ADR_ADDR, 4, carrier_addr)
for i in range(len(data)):
#adr_cnt_b = self.bus.iread(0, self.DDR_ADR_ADDR, 4)
self.bus.iwrite(0, self.DDR_DAT_ADDR, 4, data[i])
#print('[put_data] write: addr=0x%.9X i=%d data=0x%.8X'%(self.DDR_DAT_ADDR, i, data[i]))
#adr_cnt = self.bus.iread(0, self.DDR_ADR_ADDR, 4)
#print('[put_data] address counter: before=0x%.8X after=0x%.8X'%(adr_cnt_b, adr_cnt))
# Clear DDR
def clear_ddr(self):
......
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