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FMC ADC 100M 14b 4cha - Testing
Commit 9173c900 authored by Matthieu Cattin's avatar Matthieu Cattin
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Add sdb class with basic functionality. Add acquisition config Ok bit in fmc-adc core regs.

parent abba8cbd
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Showing with 18 additions and 8 deletions
test/fmcadc100m14b4cha/python/fmc_adc.py
View file @ 9173c900
......@@ -58,6 +58,8 @@ class FmcAdc100mOperationError(Exception):
class CFmcAdc100m:
#------------------------------------
# offsets from mezzanine base address
FMC_EIC_ADDR = 0x0
UTC_CORE_ADDR = 0x100
......@@ -65,6 +67,8 @@ class CFmcAdc100m:
DDR_DAT_ADDR = 0x1000
DDR_ADR_ADDR = 0x200
#------------------------------------
# offsets from mezzanine + adc core base address
FMC_SYS_I2C_ADDR = 0x1000
EEPROM_ADDR = 0x50
......
test/fmcadc100m14b4cha/python/fmc_adc_spec.py
View file @ 9173c900
......@@ -15,6 +15,7 @@ import math
# Import specific modules
#import rr
from sdb import *
from csr import *
from onewire import *
from gn4124 import *
......@@ -37,6 +38,7 @@ class FmcAdc100mSpecOperationError(Exception):
class CFmcAdc100mSpec:
# Wishbone core base addresses
SDB_ADDR = 0x0
GNUM_DMA_CSR_ADDR = 0x1000
ONEWIRE_ADDR = 0x1100
CSR_ADDR = 0x1200
......@@ -46,13 +48,6 @@ class CFmcAdc100mSpec:
# Onewire core port
DS18B20_PORT = 0
# UTC core
# tag = [wb_addr_offset, meta, second, coarse, fine]
tag_trig = [0x8, 0, 0, 0, 0]
tag_start = [0x18, 0, 0, 0, 0]
tag_stop = [0x28, 0, 0, 0, 0]
tag_end = [0x38, 0, 0, 0, 0]
# Gennum interface
DMA_LENGTH = 4096 # DMA length in bytes
......@@ -64,6 +59,8 @@ class CFmcAdc100mSpec:
self.bus = bus
# Objects declaration
self.sdb_csr = CCSR(self.bus, self.SDB_ADDR)
self.sdb = CSDB(self.sdb_csr)
self.dma_csr = CCSR(self.bus, self.GNUM_DMA_CSR_ADDR)
self.gnum = CGN4124(self.bus, self.dma_csr)
self.onewire = COpenCoresOneWire(self.bus, self.ONEWIRE_ADDR, 624, 124)
......@@ -105,6 +102,14 @@ class CFmcAdc100mSpec:
raise FmcAdc100mSpecOperationError("Mezzanine not present or PRSNT_M2C_L line faulty.")
#======================================================================
# SDB records
# Dump SDB records
def sdb_dump(self):
self.sdb.dump()
#======================================================================
# Control and status registers (CSR)
......
test/fmcadc100m14b4cha/python/fmcadc100m_csr.py
View file @ 9173c900
......@@ -23,7 +23,8 @@ FMCADC100M_CSR=['FMC ADC 100MS/s core registers',{
'FSM':[0, 'State machine status', 0x7],
'SERDES_PLL':[3, 'Serdes PLL locked', 0x1],
'SERDES_SYNCED':[4, 'Serdes synchronised', 0x1],
'RESERVED':[5, 'Reserved', 0x7FFFFFF]}],
'ACQ_CFG':[5, 'Acquisition configuration OK', 0x1],
'RESERVED':[6, 'Reserved', 0x3FFFFFF]}],
'TRIG_CFG':[0x08, 'Trigger configuration', {
'HW_TRIG_SEL':[0, 'Hardware trigger selection', 0x1],
'HW_TRIG_POL':[1, 'Hardware trigger polarity', 0x1],
......
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