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FMC ADC 100M 14b 4cha - Testing
Commit dea99e37 authored by Matthieu Cattin's avatar Matthieu Cattin
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Move register map declaration in separate files. 

This is in prevision of those files beeing automatically generated by wbgen2.
parent e9fb39c4
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test/fmcadc100m14b4cha/python/carrier_csr.py 0 → 100644
View file @ dea99e37
#! /usr/bin/env python
# coding: utf8
# Copyright CERN, 2012
# Author: Matthieu Cattin (CERN)
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
# Last modifications: 8/5/2012
# Control and status registers of the SPEC board
CARRIER_CSR={
'CARRIER':[0x00, 'Carrier', {
'PCB_REV':[0, 'PCB revision', 0xF],
'TYPE':[16, 'Carrier type', 0xFFFF]}],
'BITSTREAM_TYPE':[0x04, 'Bitstream type', {
'BITSTREAM_TYPE':[0, 'Bitstream type', 0xFFFFFFFF]}],
'BITSTREAM_DATE':[0x08, 'Bitstream date', {
'BITSTREAM_DATE':[0, 'Bitstream date', 0xFFFFFFFF]}],
'STAT':[0x0C, 'Status', {
'FMC_PRES':[0, 'FMC presence (active low)', 0x1],
'P2L_PLL_LCK':[1, 'P2L PLL locked', 0x1],
'SYS_PLL_LCK':[2, 'System PLL locked', 0x1],
'DDR3_CAL_DONE':[3, 'DDR3 calibration done', 0x1]}],
'CTRL':[0x10, 'Control', {
'LED_GREEN':[0, 'Green LED', 0x1],
'LED_RED':[1, 'Red LED', 0x1],
'DAC_CLR_N':[2, 'VCXO DAC clear (active low)', 0x1]}]
}
test/fmcadc100m14b4cha/python/fmc_adc_spec.py
View file @ dea99e37
......@@ -5,7 +5,7 @@
# Author: Matthieu Cattin (CERN)
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
# Last modifications: 7/5/2012
# Last modifications: 8/5/2012
# Import standard modules
import sys
......@@ -20,6 +20,11 @@ from onewire import *
from gn4124 import *
from ds18b20 import *
# Import register maps
from carrier_csr import *
from utc_core_regs import *
from irq_controller_regs import *
# Class to access fmcadc100m14b4cha SPEC specific Wishbone cores
class FmcAdc100mSpecOperationError(Exception):
......@@ -40,67 +45,6 @@ class CFmcAdc100mSpec:
# Onewire core port
DS18B20_PORT = 0
# Control and status registers of the SPEC board
CSR={
'CARRIER':[0x00, 'Carrier', {
'PCB_REV':[0, 'PCB revision', 0xF],
'TYPE':[16, 'Carrier type', 0xFFFF]}],
'BITSTREAM_TYPE':[0x04, 'Bitstream type', {
'BITSTREAM_TYPE':[0, 'Bitstream type', 0xFFFFFFFF]}],
'BITSTREAM_DATE':[0x08, 'Bitstream date', {
'BITSTREAM_DATE':[0, 'Bitstream date', 0xFFFFFFFF]}],
'STAT':[0x0C, 'Status', {
'FMC_PRES':[0, 'FMC presence (active low)', 0x1],
'P2L_PLL_LCK':[1, 'P2L PLL locked', 0x1],
'SYS_PLL_LCK':[2, 'System PLL locked', 0x1],
'DDR3_CAL_DONE':[3, 'DDR3 calibration done', 0x1]}],
'CTRL':[0x10, 'Control', {
'LED_GREEN':[0, 'Green LED', 0x1],
'LED_RED':[1, 'Red LED', 0x1],
'DAC_CLR_N':[2, 'VCXO DAC clear (active low)', 0x1]}]
}
# UTC core registers
UTC_CORE={
'SECONDS':[0x00, 'UTC seconds', {}],
'COARSE':[0x04, 'UTC coarse time (8ns resolution)', {}],
'TRIG_TAG_META':[0x08, 'Trigger time-tag metadata', {}],
'TRIG_TAG_SECONDS':[0x0C, 'Trigger time-tag UTC seconds', {}],
'TRIG_TAG_COARSE':[0x10, 'Trigger time-tag UTC coarse time', {}],
'TRIG_TAG_FINE':[0x14, 'Trigger time-tag fine time', {}],
'ACQ_START_TAG_META':[0x18, 'Acquisition start time-tag metadata', {}],
'ACQ_START_TAG_SECONDS':[0x1C, 'Acquisition start time-tag UTC seconds', {}],
'ACQ_START_TAG_COARSE':[0x20, 'Acquisition start time-tag UTC coarse time', {}],
'ACQ_START_TAG_FINE':[0x24, 'Acquisition start time-tag fine time', {}],
'ACQ_STOP_TAG_META':[0x28, 'Acquisition stop time-tag metadata', {}],
'ACQ_STOP_TAG_SECONDS':[0x2C, 'Acquisition stop time-tag UTC seconds', {}],
'ACQ_STOP_TAG_COARSE':[0x30, 'Acquisition stop time-tag UTC coarse time', {}],
'ACQ_STOP_TAG_FINE':[0x34, 'Acquisition stop time-tag fine time', {}],
'ACQ_END_TAG_META':[0x38, 'Acquisition end time-tag metadata', {}],
'ACQ_END_TAG_SECONDS':[0x3C, 'Acquisition end time-tag UTC seconds', {}],
'ACQ_END_TAG_COARSE':[0x40, 'Acquisition end time-tag UTC coarse time', {}],
'ACQ_END_TAG_FINE':[0x44, 'Acquisition end time-tag fine time', {}]
}
# IRQ controller core registers
IRQ_CORE={
'MULTI_IRQ':[0x00, 'Multiple interrupt', {
'DMA_END':[0, 'End of DMA transfer', 0x1],
'DMA_ERR':[1, 'Error in DMA transfer', 0x1],
'ACQ_TRG':[2, 'Acquisition triggered', 0x1],
'ACQ_END':[3, 'Acquisition finished', 0x1]}],
'SRC':[0x04, 'Interrupt sources', {
'DMA_END':[0, 'End of DMA transfer', 0x1],
'DMA_ERR':[1, 'Error in DMA transfer', 0x1],
'ACQ_TRG':[2, 'Acquisition triggered', 0x1],
'ACQ_END':[3, 'Acquisition finished', 0x1]}],
'EN_MASK':[0x08, 'Interrupt enable mask', {
'DMA_END':[0, 'End of DMA transfer', 0x1],
'DMA_ERR':[1, 'Error in DMA transfer', 0x1],
'ACQ_TRG':[2, 'Acquisition triggered', 0x1],
'ACQ_END':[3, 'Acquisition finished', 0x1]}]
}
# UTC core
UTC_CORE_SECONDS = 0x0
UTC_CORE_COARSE = 0x4
......@@ -198,56 +142,56 @@ class CFmcAdc100mSpec:
print ''
print 'Carrier control and status registers:'
print '-------------------------------------'
self.print_reg_map(self.csr, self.CSR)
self.print_reg_map(self.csr, CARRIER_CSR)
# Get carrier type
def get_carrier_type(self):
return self.get_field(self.csr, self.CSR, 'CARRIER', 'TYPE')
return self.get_field(self.csr, CARRIER_CSR, 'CARRIER', 'TYPE')
# Get PCB revision
def get_pcb_rev(self):
return self.get_field(self.csr, self.CSR, 'CARRIER', 'PCB_REV')
return self.get_field(self.csr, CARRIER_CSR, 'CARRIER', 'PCB_REV')
# Get Bitstream type
def get_bitstream_type(self):
return self.get_reg(self.csr, self.CSR, 'BITSTREAM_TYPE')
return self.get_reg(self.csr, CARRIER_CSR, 'BITSTREAM_TYPE')
# Get Bitstream date
def get_bitstream_date(self):
return self.get_reg(self.csr, self.CSR, 'BITSTREAM_DATE')
return self.get_reg(self.csr, CARRIER_CSR, 'BITSTREAM_DATE')
# Get status register value
def get_status(self):
return self.get_reg(self.csr, self.CSR, 'STAT')
return self.get_reg(self.csr, CARRIER_CSR, 'STAT')
# Get control register value
def get_control(self):
return self.get_reg(self.csr, self.CSR, 'CTRL')
return self.get_reg(self.csr, CARRIER_CSR, 'CTRL')
# Get FMC presence state
# 1 = mezzanine present, 0 = no nezzanine
def get_fmc_presence(self):
return not self.get_field(self.csr, self.CSR, 'STAT', 'FMC_PRES')
return not self.get_field(self.csr, CARRIER_CSR, 'STAT', 'FMC_PRES')
# Get Gennum core P2L PLL lock state
def get_p2l_pll_lock(self):
return self.get_field(self.csr, self.CSR, 'STAT', 'P2L_PLL_LCK')
return self.get_field(self.csr, CARRIER_CSR, 'STAT', 'P2L_PLL_LCK')
# Get system clock PLL lock state
def get_sys_pll_lock(self):
return self.get_field(self.csr, self.CSR, 'STAT', 'SYS_PLL_LCK')
return self.get_field(self.csr, CARRIER_CSR, 'STAT', 'SYS_PLL_LCK')
# Get DDR3 controller calibration done state
def get_ddr3_cal_done(self):
return self.get_field(self.csr, self.CSR, 'STAT', 'DDR3_CAL_DONE')
return self.get_field(self.csr, CARRIER_CSR, 'STAT', 'DDR3_CAL_DONE')
# Set front panel green LED ON(1) or OFF(0)
def set_green_led(self, value):
return self.set_field(self.csr, self.CSR, 'CTRL', 'LED_GREEN', value)
return self.set_field(self.csr, CARRIER_CSR, 'CTRL', 'LED_GREEN', value)
# Set front panel red LED ON(1) or OFF(0)
def set_red_led(self, value):
return self.set_field(self.csr, self.CSR, 'CTRL', 'LED_RED', value)
return self.set_field(self.csr, CARRIER_CSR, 'CTRL', 'LED_RED', value)
#======================================================================
......
test/fmcadc100m14b4cha/python/irq_controller_regs.py 0 → 100644
View file @ dea99e37
#! /usr/bin/env python
# coding: utf8
# Copyright CERN, 2012
# Author: Matthieu Cattin (CERN)
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
# Last modifications: 8/5/2012
# IRQ controller core registers
IRQ_CONTROLLER_REGS={
'MULTI_IRQ':[0x00, 'Multiple interrupt', {
'DMA_END':[0, 'End of DMA transfer', 0x1],
'DMA_ERR':[1, 'Error in DMA transfer', 0x1],
'ACQ_TRG':[2, 'Acquisition triggered', 0x1],
'ACQ_END':[3, 'Acquisition finished', 0x1]}],
'SRC':[0x04, 'Interrupt sources', {
'DMA_END':[0, 'End of DMA transfer', 0x1],
'DMA_ERR':[1, 'Error in DMA transfer', 0x1],
'ACQ_TRG':[2, 'Acquisition triggered', 0x1],
'ACQ_END':[3, 'Acquisition finished', 0x1]}],
'EN_MASK':[0x08, 'Interrupt enable mask', {
'DMA_END':[0, 'End of DMA transfer', 0x1],
'DMA_ERR':[1, 'Error in DMA transfer', 0x1],
'ACQ_TRG':[2, 'Acquisition triggered', 0x1],
'ACQ_END':[3, 'Acquisition finished', 0x1]}]
}
test/fmcadc100m14b4cha/python/utc_core_regs.py 0 → 100644
View file @ dea99e37
#! /usr/bin/env python
# coding: utf8
# Copyright CERN, 2012
# Author: Matthieu Cattin (CERN)
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
# Last modifications: 8/5/2012
# UTC core registers
UTC_CORE_REGS={
'SECONDS':[0x00, 'UTC seconds', {}],
'COARSE':[0x04, 'UTC coarse time (8ns resolution)', {}],
'TRIG_TAG_META':[0x08, 'Trigger time-tag metadata', {}],
'TRIG_TAG_SECONDS':[0x0C, 'Trigger time-tag UTC seconds', {}],
'TRIG_TAG_COARSE':[0x10, 'Trigger time-tag UTC coarse time', {}],
'TRIG_TAG_FINE':[0x14, 'Trigger time-tag fine time', {}],
'ACQ_START_TAG_META':[0x18, 'Acquisition start time-tag metadata', {}],
'ACQ_START_TAG_SECONDS':[0x1C, 'Acquisition start time-tag UTC seconds', {}],
'ACQ_START_TAG_COARSE':[0x20, 'Acquisition start time-tag UTC coarse time', {}],
'ACQ_START_TAG_FINE':[0x24, 'Acquisition start time-tag fine time', {}],
'ACQ_STOP_TAG_META':[0x28, 'Acquisition stop time-tag metadata', {}],
'ACQ_STOP_TAG_SECONDS':[0x2C, 'Acquisition stop time-tag UTC seconds', {}],
'ACQ_STOP_TAG_COARSE':[0x30, 'Acquisition stop time-tag UTC coarse time', {}],
'ACQ_STOP_TAG_FINE':[0x34, 'Acquisition stop time-tag fine time', {}],
'ACQ_END_TAG_META':[0x38, 'Acquisition end time-tag metadata', {}],
'ACQ_END_TAG_SECONDS':[0x3C, 'Acquisition end time-tag UTC seconds', {}],
'ACQ_END_TAG_COARSE':[0x40, 'Acquisition end time-tag UTC coarse time', {}],
'ACQ_END_TAG_FINE':[0x44, 'Acquisition end time-tag fine time', {}]
}
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