board is equipped with an on-board crystal oscillator from Silicon Labs.
The Si570 crystal oscillator IC
can be programmed via the I2C interface to provide frequencies in the
range 10MHz - 1.4GHz. This crystal oscillator drives the clock pins of
the ADC chip on-board the mezzanine cards. When using multiple ADC
mezzanine cards in a large experimental facility, it may be necessary to
make sure the measurements they provide are synchronized. This
synchronization can be provided via White
This page contans the specifications and implementation details of the
mechanism used to synchronize multiple ADC mezzanine cards with a
In order to synchronize two or more ADC mezzanine cards with sub-ns
accuracy, the clock synchronization mechanism (CSM) should be perform as
It is assumed that the ADC FMCs are equipped with an Si570
pre-calibrated from factory to output a 100MHz frequency. Since the
WR core offers a clock that is stable to within /-2 ppm, and the
output frequency of the Si570 can be changed to within/-3500 ppm
simply by changing the values of the RFREQ registers (see
it is enough to only change one or more of the RFREQ registers
whenever the Si570 clock and the White Rabbit clocks are out of
Upon initialization (FPGA device reset), the CSM will read the RFREQ
register of the Si570. This process is performed only once, upon
device reset, and considering the previous specification, changes in
frequency will from that moment on be made by adjusting the value of
A dedicated I2C controller will be implemented in hardware to handle
reading from and writing to the Si570.
The CSM will be accessible externally via the Wishbone bus, offering
control and status registers (CSRs) accessible to the user. The
Wishbone bus in use is the auxiliary WR Wishbone bus. Therefore one
will need to read/write through the WR core to access the device.
In order to comply with the previous specification, the CSM will
implement a simple Wishbone slave interface.
A debug mode will be implemented, offering the user direct access to
the Si570's registers via the I2C interface. When in debug mode, the
Si570 registers will be controlled exclusively via the Wishbone
interface. When not in debug mode, the Si570 registers will be
controlled exclusively by the CSM.
Since the WR core is capable of disciplining various external clocks
via its internal software PLL, the clock from the Si570 will be
input to the WR core and uses timing data from the WR core to adjust
the RFREQ registers of the Si570.
If WR is in sync with an uplink node or is the System Timing Master
(thus providing the synchronization based on the high-precision
reference clock), the CSM is enabled and tracks the Si570 clock
against the WR clock continuously.
If WR is not in synchronization with the uplink node, the CSM should
When the CSM is disabled or if the WR core is out of sync, the Si570
clock is left free-running, keeping the settings last written before
the CSM was
Block diagram of the design
All registers shall be byte-sized registers (8 bits wide). An address
map and details about the registers are given below.