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FMC DEL 1ns 4cha
Commit dffa0b56 authored by Greg's avatar Greg Committed by Tomasz Wlostowski
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Sch/PCB: Added directory with PLL loop ADIsim project file, changed clk… 

Sch/PCB: Added directory with PLL loop ADIsim project file, changed clk assignments at the PLL output, added extra notes, changed termination resistors

git-svn-id: http://svn.ohwr.org/fmc-delay-1ns-8cha@11 1bcb1fca-75bf-43fa-9ae8-4d3013b6ad5d
parent 7258e40d
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Showing with 16 additions and 1 deletion
trunk/circuit_board/fmc-delay-1ns-8cha/Schematics/FMC_Delay_1ns_4Cha.PrjPcb
View file @ dffa0b56
......@@ -176,6 +176,21 @@ ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None
DItemRevisionGUID=
[Document11]
DocumentPath=FMC_Delay_1ns_4Cha.OutJob
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None
DItemRevisionGUID=
[Generic_SmartPDF]
AutoOpenFile=-1
AutoOpenOutJob=-1
......@@ -196,7 +211,7 @@ SCH_ShowNoErc=-1
SCH_ShowParameter=-1
SCH_ShowProbes=-1
SCH_ShowBlankets=-1
OutputFileName=FMC_Delay_1ns_4Cha.PrjPcb=E:\DESIGNS\FMC_Delay_1ns_4CH\PCB\FMC_Delay_4CH_PCB_0.8\FMC_Delay_1ns_4Cha.pdf
OutputFileName=FMC_Delay_1ns_4Cha.PrjPcb=E:\DESIGNS\FMC_Delay_1ns_4CH\PCB\FMC Delay 1ns 8cha\trunk\circuit_board\fmc-delay-1ns-8cha\Schematics\FMC_Delay_1ns_4Cha.pdf
SCH_ExpandLogicalToPhysical=-1
SCH_VariantName=[No Variations]
SCH_ExpandComponentDesignators=-1
......
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