Sch/PCB: Changed clock connection to the output flip-flops, changed resistors to resistor arrays, added 2 layers to improve signal integrity and differential pair routing, changed footprints and schematic symbols to the CERN ones.

git-svn-id: http://svn.ohwr.org/fmc-delay-1ns-8cha@15 1bcb1fca-75bf-43fa-9ae8-4d3013b6ad5d

git-svn-id: http://svn.ohwr.org/fmc-delay-1ns-8cha@14 1bcb1fca-75bf-43fa-9ae8-4d3013b6ad5d

git-svn-id: http://svn.ohwr.org/fmc-delay-1ns-8cha@13 1bcb1fca-75bf-43fa-9ae8-4d3013b6ad5d

Sch/PCB: Added directory with PLL loop ADIsim project file, changed clk assignments at the PLL output, added extra notes, changed termination resistors

git-svn-id: http://svn.ohwr.org/fmc-delay-1ns-8cha@11 1bcb1fca-75bf-43fa-9ae8-4d3013b6ad5d

git-svn-id: http://svn.ohwr.org/fmc-delay-1ns-8cha@10 1bcb1fca-75bf-43fa-9ae8-4d3013b6ad5d

git-svn-id: http://svn.ohwr.org/fmc-delay-1ns-8cha@9 1bcb1fca-75bf-43fa-9ae8-4d3013b6ad5d

git-svn-id: http://svn.ohwr.org/fmc-delay-1ns-8cha@8 1bcb1fca-75bf-43fa-9ae8-4d3013b6ad5d