FMC Delay 1ns 8cha
Functional system specifications
- 1 ns resolution or better.
- Accuracy: /- (500 ps timebase accuracy).
- Timebase accuracy: +/- 4ppm.
- Implementation details: timebase from a local TCXO on FMC card and needs calibration. The 4ppm accuracy is the one of the on-board TCXO. Much better accuracy will be reached when used on a White Rabbit enabled FMC carrier.
- 500 ns - 120 s range or better.
- 1 input, selectable between front panel and FMC connector. This input is shared by all output channels.
- Input electrical standard will be TTL (not LVTTL), with optional 50 Ohm termination. The default power-up state is high impedance. A LED will signal termination status.
- External input needs to be protected against +15V pulses with a pulse width of at least 10us @ 50Hz (with protection diodes if possible).
- Need to withstand a continuous short-circuit on all the outputs at the same time.
- Output standard: 50 Ohm TTL drivers (with 2V/ns or faster rising edges). At power-up the default output state is low, with no glitches.
- SMC connectors for input and outputs.
- 4 individually controllable outputs, with independent delay, width and enable/disable.
- Delay circuit reacts on input rising edge. Minimum input pulse width: 100 ns. Pulses shorter than 20ns should be ignored.
- Input pulses will be ignored until the longest programmed delay of the previous input pulse has expired.
- Output pulse width is programmable in steps of system clock ticks (~125 MHz) with a 16-bit register per output channel.
- Jitter will be measured by probing two output channels which have been programmed with the same delay. The sigma of the distribution of delay measurements between the rising edges of any two channels should not exceed 100 ps. This should hold for any programmed delay within the whole delay range.
- A circular buffer will contain time tags for at least the last 100 input and output pulses. These time tags will at first be rough UTC (counter initialized by SW) giving ~ms accuracy. Later, with a WR-enabled solution, they can be much more accurate.
Preliminary ideas for the technical specifications
- Baseline solution: TDC at the inputs followed by coarse count in the FPGA and fine delay chips at the outputs. To be considered for improving jitter: monolithic FFs in the FMC, before the fine delay chips. Continuous calibration of fine delay chips might be needed to compensate for Process-Voltage-Temperature (PVT) effects. The timebase is from a local TCXO on FMC card and needs calibration. The 4ppm accuracy will only be reached when used on a White Rabbit enabled FMC carrier.
Project Status
Date | Event |
22-04-2010 | Start working on project. |
30-04-2010 | First meeting with N. Voumard to fine-tune functional specs. |
20-05-2010 | Second functional specs meeting with the ABT team. |
11-06-2010 | Order 4384595 made for design of the module. |
15-06-2010 | Final functional specification review meeting held. Resulted in minor modifications. |
30-06-2010 | Technical specification draft finished. |
17-08-2010 | First schematics review held. ReviewFineDelayFMC17082010 |
03-09-2010 | Schematics revised. Waiting for a new design review. |
10-11-2010 | Second schematics review held. ReviewFineDelayFMC10112010 |
12-11-2010 | Comments on review received. Re-commented on it. FMC10112010_improvements v5 |
25-11-2010 | Updated schematics and comments received. ReviewFineDelayFMC10112010-improvements |
25-11-2010 | Comments on updated schematics. ReviewFineDelayFMC25112010 |
30-11-2010 | Updated schematics and comments received. ReviewFineDelayFMC25112010-improvements |
13-12-2010 | First version of PCB layout expected by 17 December. |
14-01-2011 | Spec change for minimum delay: 500 ns. PCB layout almost finished, waiting for some symbols. |
18-01-2011 | PCB layout received. Review on 19-01-2011. |
18-01-2011 | Changelog for the PCB/schematics published: Changelog-19012010 |
Erik van der Bij - 18 January 2011