-
David Cussans authored
( trigger output two clock cycles of 40MHz, trigger number on reset line being clocked out at 160MHz) * Added reset circuitry to DUTInterface_AIDA_rtl.vhd * Added one extra register of clk4x ( 160MHz ) to aid with timing closure ( although Vivado not reporting negative slack - so have probably got timing contraints wrong :-o )
187ad97c
Name |
Last commit
|
Last update |
---|---|---|
.. | ||
Documentation | ||
bitFiles | ||
boards/enclustra_ax3_pm3/base_fw | ||
components | ||
legacy | ||
projects/TLU_v1e | ||
scripts | ||
.gitignore | ||
README.md |