Checking in changes to event formatter to get fine-grain timing information…

Checking in changes to event formatter to get fine-grain timing information aligned with trigger and hence written to FIFO correctly

Checking in changes to event formatter to get fine-grain timing information…
Checking in changes to event formatter to get fine-grain timing information aligned with trigger and hence written to FIFO correctly
0f25c0e1 · David Cussans · 4d22ae94 · 0f25c0e1 · 0f25c0e1
Commit 0f25c0e1 authored Nov 04, 2015 by David Cussans
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Showing with 7 additions and 17 deletions

eventFormatter_rtl.vhd firmware/hdl/common/eventFormatter_rtl.vhd +6 -16

ipbus_ver.vhd firmware/hdl/common/ipbus_ver.vhd +1 -1

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--- a/firmware/hdl/common/eventFormatter_rtl.vhd
+++ b/firmware/hdl/common/eventFormatter_rtl.vhd
@@ -103,10 +103,6 @@ END eventFormatter ;
 --
 ARCHITECTURE rtl OF eventFormatter IS

-  -- add to ports
-  -- trigger_i           : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    -- ! High when trigger active
-  -- signal inputs_triggered_i :    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    -- ! High when trigger active
-  -- signal logic_reset_i : std_logic := '0';  -- put into ports...
  
  constant c_NUM_INPUT_TYPES     : positive := 3+g_NUM_EDGE_INPUTS;               -- Number of different input types (trigger, shutter, edge(0), edge(1)...)
  
@@ -145,6 +141,7 @@ ARCHITECTURE rtl OF eventFormatter IS
 --  signal s_event_number : unsigned(g_IPBUS_WIDTH-1 downto 0) := (others => '0');  -- increment after each post-veto trigger.

  signal s_word0 , s_word1, s_word2 			: std_logic_vector(g_EVENT_DATA_WIDTH-1 downto 0) := (others => '0');  -- clocked to data output on logic_strobe , s_logic_strobe_d1 , etc.
+  signal s_word0_p1  : std_logic_vector(g_EVENT_DATA_WIDTH-1 downto 0) := (others => '0');  -- clocked to data output on logic_strobe , s_logic_strobe_d1 , etc.
  signal s_word0_d1 , s_word1_d1, s_word2_d1 : std_logic_vector(g_EVENT_DATA_WIDTH-1 downto 0) := (others => '0');  -- clocked to data output on logic_strobe , s_logic_strobe_d1 , etc.
  signal s_word0_d2 , s_word1_d2, s_word2_d2 : std_logic_vector(g_EVENT_DATA_WIDTH-1 downto 0) := (others => '0');  -- clocked to data output on logic_strobe , s_logic_strobe_d1 , etc.
  signal s_word0_d3 , s_word1_d3, s_word2_d3 : std_logic_vector(g_EVENT_DATA_WIDTH-1 downto 0) := (others => '0');  -- clocked to data output on logic_strobe , s_logic_strobe_d1 , etc.
@@ -301,7 +298,8 @@ BEGIN
    if rising_edge(clk_4x_logic_i) then

 		trigger_times_d1 <= trigger_times_i;
-		
+
+                s_word0 <= s_word0_p1;
 		s_word0_d1 <= s_word0;
 		s_word1_d1 <= s_word1;
 		s_word1_d2 <= s_word1_d1;
@@ -322,19 +320,11 @@ BEGIN
 -------------------------------------------------------------------------------
 -- Trigger event formater
 -------------------------------------------------------------------------------
- -- s_evttype <= "0000" when unsigned(trigger_inputs_fired_d1) = 0 and trigger_i = '1' else
--  s_evttype <= "0000" when unsigned(trigger_inputs_fired_i) = 0 and trigger_i = '1' else
--               "0001";
--   s_evttype <= "0000" when unsigned(trigger_inputs_fired_d1) = 0 else
--               "0001";
-     s_evttype <= "0000" when unsigned(trigger_inputs_fired_i) = 0 else "0001";
-
--  s_var     <= trigger_inputs_fired_d1 & std_logic_vector(to_unsigned(0,s_var'length-g_NUM_TRIG_INPUTS));
-  s_var <= trigger_inputs_fired_i & std_logic_vector(to_unsigned(0,s_var'length-g_NUM_TRIG_INPUTS));
+  s_evttype <= "0000" when unsigned(trigger_inputs_fired_i) = 0 else "0001";

+  s_var <= trigger_inputs_fired_i & std_logic_vector(to_unsigned(0,s_var'length-g_NUM_TRIG_INPUTS));

-  --s_word0 <= s_evttype(0) & s_var(0) & std_logic_vector(s_coarse_timestamp_d2);
-  s_word0 <= s_evttype & s_var & s_coarse_timestamp;
+  s_word0_p1 <= s_evttype & s_var & s_coarse_timestamp;
  
  s_word1 <= "000" & trigger_times_d1(0) & "000" & trigger_times_d1(1) &
             "000" & trigger_times_d1(2) & "000" & trigger_times_d1(3) &

--- a/firmware/hdl/common/ipbus_ver.vhd
+++ b/firmware/hdl/common/ipbus_ver.vhd
@@ -25,7 +25,7 @@ architecture rtl of ipbus_ver is

 begin

-  ipbus_out.ipb_rdata <= X"a620" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement).
+  ipbus_out.ipb_rdata <= X"a622" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement).
  ipbus_out.ipb_ack <= ipbus_in.ipb_strobe;
  ipbus_out.ipb_err <= '0';