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AIDA-2020 TLU
Commit 4d22ae94 authored by David Cussans's avatar David Cussans
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Bodging to get fine-grain time-stamp working with pulse shifts and delays

parent 81cbbeae
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Showing with 44 additions and 30 deletions
firmware/hdl/common/eventFormatter_rtl.vhd
View file @ 4d22ae94
......@@ -134,32 +134,14 @@ ARCHITECTURE rtl OF eventFormatter IS
-- 0111 spill on
-- 0110 spill off
-- signal s_var : t_var(3+g_NUM_EDGE_INPUTS-1 downto 0) :=(others=>(others=>'0')); -- 12b different in every input
signal s_var : std_logic_vector(g_COUNTER_WIDTH-1 downto 0) := (others => '0');
--signal s_FIFO_wr : std_logic_vector(3+g_NUM_EDGE_INPUTS-1 downto 0) := (others=>'0'); -- FIFO write signal
--signal s_FIFO_rd : std_logic_vector(3+g_NUM_EDGE_INPUTS-1 downto 0) := (others=>'0'); -- FIFO read signals
--signal s_FIFO_rd_d1 : std_logic_vector(3+g_NUM_EDGE_INPUTS-1 downto 0) := (others=>'0'); -- FIFO read signals delayed
--signal s_FIFO_rd_d2 : std_logic_vector(3+g_NUM_EDGE_INPUTS-1 downto 0) := (others=>'0'); -- FIFO read signals delayed
--constant c_FIFO_rd_mask : unsigned(3+g_NUM_EDGE_INPUTS-1 downto 0) := (0 =>'1',others=>'0'); --(3+g_NUM_EDGE_INPUTS-1 =>'1',others=>'0'); -- FIFO read mask
--signal s_FIFO_empty : std_logic_vector(3+g_NUM_EDGE_INPUTS-1 downto 0) := (others=>'0'); -- FIFO empty signals
--signal s_FIFO_full : std_logic_vector(3+g_NUM_EDGE_INPUTS-1 downto 0) := (others=>'0'); -- FIFO full signals
--signal s_FIFO_i : t_fifo_io(3+g_NUM_EDGE_INPUTS-1 downto 0) :=(others=>(others=>'0')); -- FIFO input data
--signal s_FIFO_o : t_fifo_io(3+g_NUM_EDGE_INPUTS-1 downto 0) :=(others=>(others=>'0')); -- FIFO output data
signal s_data_o : std_logic_vector(g_EVENT_DATA_WIDTH-1 DOWNTO 0); -- Multiplexed data from FIFOs
--signal s_data_o_mask : unsigned(3+g_NUM_EDGE_INPUTS-1 downto 0) := (g_NUM_TRIG_INPUTS+g_NUM_EDGE_INPUTS-1 =>'1',others=>'0'); -- Output data mask
constant c_COARSE_TIMESTAMP_WIDTH : positive := 48; -- ! Number of bits in 40MHz timestamp
constant c_COARSE_TIMESTAMP_L_WIDTH : positive := 32; -- ! Number of bits in 40MHz timestamp lower bits
constant c_COARSE_TIMESTAMP_H_WIDTH : positive := 16; -- ! Number of bits in 40MHz timestamp higher bits
-- signal s_coarse_timestamp_l, s_coarse_timestamp_l_d1, s_coarse_timestamp_l_d2, s_coarse_timestamp_l_d3 : unsigned(c_COARSE_TIMESTAMP_L_WIDTH-1 downto 0) := (others => '0'); -- 40MHz timestamp.
-- signal s_coarse_timestamp_h, s_coarse_timestamp_h_d1, s_coarse_timestamp_h_d2, s_coarse_timestamp_h_d3 : unsigned(c_COARSE_TIMESTAMP_H_WIDTH-1 downto 0) := (others => '0'); -- 40MHz timestamp.
signal s_coarse_timestamp : std_logic_vector(c_COARSE_TIMESTAMP_WIDTH-1 downto 0) := (others => '0'); -- 40MHz timestamp.
signal s_coarse_timestamp_ipbus : ipb_reg_v(1 downto 0) := ( others => (others => '0')); --! 40MHz timestamp on IPB clock domain.
signal s_timestamp_h_en : std_logic:='0';
-- signal s_event_number : unsigned(g_IPBUS_WIDTH-1 downto 0) := (others => '0'); -- increment after each post-veto trigger.
signal s_word0 , s_word1, s_word2 : std_logic_vector(g_EVENT_DATA_WIDTH-1 downto 0) := (others => '0'); -- clocked to data output on logic_strobe , s_logic_strobe_d1 , etc.
......@@ -181,6 +163,8 @@ ARCHITECTURE rtl OF eventFormatter IS
signal s_rst_fifo_d1 , s_rst_fifo_d2 , s_rst_fifo_clk4x : std_logic := '0';
signal s_buffer_full_d1 , s_buffer_full_d2 , s_buffer_full_clk4x : std_logic := '0';
signal s_trigger : std_logic := '0'; -- pulses on risng edge of triger in
signal s_captured_trigger_times : t_triggerTimeArray (g_NUM_TRIG_INPUTS-1 DOWNTO 0); --! Array of trigger times,captured when trigger
BEGIN
......
firmware/hdl/common/fmcTLU_pkg.vhd
View file @ 4d22ae94
......@@ -18,7 +18,7 @@ PACKAGE fmcTLU IS
constant c_EVENT_DATA_WIDTH : natural := 32;
constant c_DATA_WIDTH : natural := 32;
--subtype t_triggerTime is std_logic_vector(c_NUM_TIME_BITS-1 downto 0);
subtype t_triggerTime is std_logic_vector(c_NUM_TIME_BITS-1 downto 0);
--type t_triggerTimeArray is array(natural range <>) of t_triggerTime;
type t_triggerTimeArray is array(natural range <>) of std_logic_vector(c_NUM_TIME_BITS-1 downto 0) ;
......
firmware/hdl/common/stretchPulse_rtl.vhd
View file @ 4d22ae94
......@@ -17,6 +17,9 @@ LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
--! Definition of trigger time
USE work.fmcTLU.all;
entity stretchPulse is
generic (
......@@ -26,6 +29,9 @@ entity stretchPulse is
clk_i : in std_logic; --! Active high
pulse_i : in std_logic; --! Active high
pulse_o : out std_logic; --! delayed and stretched
triggerTime_i : in t_triggerTime; --! 5-bit time
triggerTime_o : out t_triggerTime; --! Delayed by same amount as pulse
pulseWidth_i : in std_logic_vector(g_PARAM_WIDTH-1 downto 0); --! Minimum pulse width ( in clock cycles )
pulseDelay_i : in std_logic_vector(g_PARAM_WIDTH-1 downto 0) --! Delay is pulseDelay_i +1 clock cycles
);
......@@ -38,6 +44,11 @@ architecture rtl of stretchPulse is
signal s_delaySR : std_logic_vector( (2**g_PARAM_WIDTH) -1 downto 0) := ( others => '0' ); -- --! Shift register to generate delay
signal s_stretchSR : std_logic_vector( (2**g_PARAM_WIDTH) -1 downto 0) := ( others => '0' ); -- --! Shift register to generate stretch
signal s_delayedPulse : std_logic := '0'; -- delayed pulse before stretch
signal s_triggerTimeSR : t_triggerTimeArray ( (2**g_PARAM_WIDTH)-1 downto 0) := ( others => ( others => '0')); -- array of trigger times
signal s_triggerTime_d1 : t_triggerTime := ( others => '0'); -- shim out by one more clock cycle...
signal s_stretchedTriggerTime : t_triggerTime := ( others => '0'); -- shim out by one more clock cycle...
begin -- architecture rtl
......@@ -47,6 +58,12 @@ begin -- architecture rtl
if rising_edge(clk_i) then
s_delaySR <= s_delaySR( (s_delaySR'left -1) downto 0 ) & pulse_i;
s_delayedPulse <= s_delaySR( to_integer(unsigned(pulseDelay_i)) );
-- delay the trigger time to match trigger delay
s_triggerTimeSR <= s_triggerTimeSR( (s_triggerTimeSR'left -1) downto 0 ) & triggerTime_i;
s_triggerTime_d1 <= s_triggerTimeSR( to_integer(unsigned(pulseDelay_i)) );
-- triggerTime_o <= s_triggerTime_d1 ;
end if;
end process p_delayPulse;
......@@ -61,6 +78,13 @@ begin -- architecture rtl
s_stretchSR <= s_stretchSR( (s_stretchSR'left -1) downto 0 ) & '0';
pulse_o <= s_stretchSR( to_integer(unsigned(pulseWidth_i)) );
end if;
if s_stretchSR( to_integer(unsigned(pulseWidth_i)) ) = '0' then
--s_stretchedTriggerTime <= s_triggerTimeSR( to_integer(unsigned(pulseDelay_i)) );
triggerTime_o <= s_triggerTime_d1;
end if;
--triggerTime_o <= s_stretchedTriggerTime ;
end if;
end process p_stretchPulse;
......
firmware/hdl/common/triggerLogic_rtl.vhd
View file @ 4d22ae94
......@@ -114,6 +114,7 @@ ARCHITECTURE rtl OF triggerLogic IS
signal s_external_veto_word : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');
signal s_loadTriggerPattern , s_loadTriggerPattern_p1 : std_logic := '0'; -- take high to load trigger pattern
signal s_delayedTriggerTimes, s_delayedTriggerTimes_d1, s_delayedTriggerTimes_d2 : t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); --! Array of std_logic_vectors
signal s_stretchedTriggers , s_stretchedTriggers_d1 , s_stretchedTriggers_d2 : std_logic_vector( trigger_i'range) := (others => '0'); -- --! Triggers after stretch and delay
BEGIN
......@@ -196,18 +197,19 @@ BEGIN
end process p_delayLoadPulse;
-- Stretch and delay pulses.
--D Put in delay for trigger times as well.
gen_stretchVals: for v_inputNumber in 0 to g_NUM_INPUTS-1 generate
cmp_stretchPulse: entity work.stretchPulse
generic map (
g_PARAM_WIDTH => c_PARAM_WIDTH)
port map (
clk_i => clk_4x_logic_i,
pulse_i => trigger_i(v_inputNumber),
pulse_o => s_stretchedTriggers(v_inputNumber),
pulsewidth_i => s_PulseStretchWord( (v_inputNumber*c_BYTE_WIDTH) + c_PARAM_WIDTH -1 downto v_inputNumber*c_BYTE_WIDTH ),
pulseDelay_i => s_PulseDelayWord( (v_inputNumber*c_BYTE_WIDTH) + c_PARAM_WIDTH -1 downto v_inputNumber*c_BYTE_WIDTH )
-- pulsewidth_i => s_PulseStretchWord( c_PARAM_WIDTH-1 downto 0 ),
-- pulseDelay_i => s_PulseDelayWord( c_PARAM_WIDTH-1 downto 0 )
clk_i => clk_4x_logic_i,
pulse_i => trigger_i(v_inputNumber),
pulse_o => s_stretchedTriggers(v_inputNumber),
triggerTime_i => trigger_times_i(v_inputNumber),
triggerTime_o => s_delayedTriggerTimes(v_inputNumber),
pulsewidth_i => s_PulseStretchWord( (v_inputNumber*c_BYTE_WIDTH) + c_PARAM_WIDTH -1 downto v_inputNumber*c_BYTE_WIDTH ),
pulseDelay_i => s_PulseDelayWord( (v_inputNumber*c_BYTE_WIDTH) + c_PARAM_WIDTH -1 downto v_inputNumber*c_BYTE_WIDTH )
);
end generate gen_stretchVals;
......@@ -249,9 +251,13 @@ BEGIN
-- same time as the pre/post veto trigger signals.
s_stretchedTriggers_d1 <= s_stretchedTriggers;
s_stretchedTriggers_d2 <= s_stretchedTriggers_d1;
s_delayedTriggerTimes_d1 <= s_delayedTriggerTimes;
s_delayedTriggerTimes_d2 <= s_delayedTriggerTimes_d1;
trigger_o <= s_stretchedTriggers_d2;
trigger_times_o <= trigger_times_i;
trigger_times_o <= s_delayedTriggerTimes_d2; -- trigger_times_i; -- put delayed version of trigger
-- times here
end if;
end process;
......
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