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AIDA-2020 TLU
Commit 81cbbeae authored by David Cussans's avatar David Cussans
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Checking in updated FIFO core definition

parent 9a0a1b3e
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firmware/chipscope/fmc_tlu_chipscope.cdc
View file @ 81cbbeae
#ChipScope Core Inserter Project File Version 3.0
#Wed Oct 28 14:11:18 CET 2015
#Thu Oct 29 13:14:34 CET 2015
Project.device.designInputFile=/afs/cern.ch/user/c/cussans/IPBus_stuff/fmc_tlu_test_modify_tpix3_nov14_aug15/workspace/top_extphy_cs.ngc
Project.device.designOutputFile=/afs/cern.ch/user/c/cussans/IPBus_stuff/fmc_tlu_test_modify_tpix3_nov14_aug15/workspace/top_extphy_cs.ngc
Project.device.deviceFamily=18
......@@ -7,25 +7,25 @@ Project.device.enableRPMs=true
Project.device.outputDirectory=/afs/cern.ch/user/c/cussans/IPBus_stuff/fmc_tlu_test_modify_tpix3_nov14_aug15/workspace/_ngo
Project.device.useSRL16=true
Project.filter.dimension=19
Project.filter<0>=*trig*
Project.filter<10>=*clk*
Project.filter<11>=clk*
Project.filter<12>=*veto*
Project.filter<13>=*busy*
Project.filter<14>=*external*
Project.filter<15>=*externali*
Project.filter<16>=*veto_i*
Project.filter<17>=*ignore*
Project.filter<18>=*ignore_busy*
Project.filter<1>=*fired*
Project.filter<2>=
Project.filter<3>=*CLK*4*
Project.filter<4>=i2/*STROBE*
Project.filter<5>=i2/*TRIG*
Project.filter<6>=*word*
Project.filter<7>=*type*
Project.filter<8>=*evt*
Project.filter<9>=*clk*4*
Project.filter<0>=*deser*
Project.filter<10>=*clk*4*
Project.filter<11>=*clk*
Project.filter<12>=clk*
Project.filter<13>=*veto*
Project.filter<14>=*busy*
Project.filter<15>=*external*
Project.filter<16>=*externali*
Project.filter<17>=*veto_i*
Project.filter<18>=*ignore*
Project.filter<1>=
Project.filter<2>=*trig*
Project.filter<3>=*fired*
Project.filter<4>=*CLK*4*
Project.filter<5>=i2/*STROBE*
Project.filter<6>=i2/*TRIG*
Project.filter<7>=*word*
Project.filter<8>=*type*
Project.filter<9>=*evt*
Project.icon.boundaryScanChain=1
Project.icon.enableExtTriggerIn=false
Project.icon.enableExtTriggerOut=false
......@@ -35,9 +35,9 @@ Project.unit.dimension=1
Project.unit<0>.clockChannel=clk_4x_logic
Project.unit<0>.clockEdge=Rising
Project.unit<0>.dataChannel<0>=I2/s_coarse_timestamp_h<0>
Project.unit<0>.dataChannel<10>=I2/trigger_inputs_fired_d1<1>
Project.unit<0>.dataChannel<11>=I2/trigger_inputs_fired_d1<2>
Project.unit<0>.dataChannel<12>=I2/trigger_inputs_fired_d1<3>
Project.unit<0>.dataChannel<10>=I3/trigger_o<2>
Project.unit<0>.dataChannel<11>=I3/trigger_o<1>
Project.unit<0>.dataChannel<12>=I3/trigger_o<0>
Project.unit<0>.dataChannel<1>=I2/s_coarse_timestamp_h<1>
Project.unit<0>.dataChannel<2>=I2/s_coarse_timestamp_h<2>
Project.unit<0>.dataChannel<3>=I2/s_coarse_timestamp_h<3>
......@@ -46,8 +46,8 @@ Project.unit<0>.dataChannel<5>=I2/s_event_strobe_d2
Project.unit<0>.dataChannel<6>=I2/s_event_strobe_d1
Project.unit<0>.dataChannel<7>=I2/data_strobe_o
Project.unit<0>.dataChannel<8>=I3/s_post_veto_trigger
Project.unit<0>.dataChannel<9>=I2/trigger_inputs_fired_d1<0>
Project.unit<0>.dataDepth=2048
Project.unit<0>.dataChannel<9>=I3/trigger_o<3>
Project.unit<0>.dataDepth=1024
Project.unit<0>.dataEqualsTrigger=true
Project.unit<0>.dataPortWidth=13
Project.unit<0>.enableGaps=false
......@@ -55,13 +55,13 @@ Project.unit<0>.enableStorageQualification=true
Project.unit<0>.enableTimestamps=false
Project.unit<0>.timestampDepth=0
Project.unit<0>.timestampWidth=0
Project.unit<0>.triggerChannel<0><0>=I2/s_coarse_timestamp_h<0>
Project.unit<0>.triggerChannel<0><0>=I1/trigger_input_loop[0].thresholdDeserializer/s_data_o<2>
Project.unit<0>.triggerChannel<0><10>=I3/trigger_o<2>
Project.unit<0>.triggerChannel<0><11>=I3/trigger_o<1>
Project.unit<0>.triggerChannel<0><12>=I3/trigger_o<0>
Project.unit<0>.triggerChannel<0><1>=I2/s_coarse_timestamp_h<1>
Project.unit<0>.triggerChannel<0><2>=I2/s_coarse_timestamp_h<2>
Project.unit<0>.triggerChannel<0><3>=I2/s_coarse_timestamp_h<3>
Project.unit<0>.triggerChannel<0><1>=I1/trigger_input_loop[0].thresholdDeserializer/s_data_o<0>
Project.unit<0>.triggerChannel<0><2>=I1/trigger_input_loop[0].thresholdDeserializer/s_data_o<3>
Project.unit<0>.triggerChannel<0><3>=I1/trigger_input_loop[0].thresholdDeserializer/s_data_o<1>
Project.unit<0>.triggerChannel<0><4>=I2/s_event_strobe_d3
Project.unit<0>.triggerChannel<0><5>=I2/s_event_strobe_d2
Project.unit<0>.triggerChannel<0><6>=I2/s_event_strobe_d1
......
firmware/ise/ipcore_dir/tlu_event_fifo.xco
View file @ 81cbbeae
##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Thu Aug 28 15:34:30 2014
# Date: Wed Oct 28 10:31:15 2015
#
##############################################################
#
......@@ -53,18 +53,18 @@ CSET clock_enable_type=Slave_Interface_Clock_Enable
CSET clock_type_axi=Common_Clock
CSET component_name=tlu_event_fifo
CSET data_count=false
CSET data_count_width=14
CSET data_count_width=13
CSET disable_timing_violations=false
CSET disable_timing_violations_axi=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=4
CSET empty_threshold_assert_value=2
CSET empty_threshold_assert_value_axis=1022
CSET empty_threshold_assert_value_rach=1022
CSET empty_threshold_assert_value_rdch=1022
CSET empty_threshold_assert_value_wach=1022
CSET empty_threshold_assert_value_wdch=1022
CSET empty_threshold_assert_value_wrch=1022
CSET empty_threshold_negate_value=5
CSET empty_threshold_negate_value=3
CSET enable_aruser=false
CSET enable_awuser=false
CSET enable_buser=false
......@@ -117,14 +117,14 @@ CSET fifo_implementation_wach=Common_Clock_Block_RAM
CSET fifo_implementation_wdch=Common_Clock_Block_RAM
CSET fifo_implementation_wrch=Common_Clock_Block_RAM
CSET full_flags_reset_value=1
CSET full_threshold_assert_value=16000
CSET full_threshold_assert_value=8181
CSET full_threshold_assert_value_axis=1023
CSET full_threshold_assert_value_rach=1023
CSET full_threshold_assert_value_rdch=1023
CSET full_threshold_assert_value_wach=1023
CSET full_threshold_assert_value_wdch=1023
CSET full_threshold_assert_value_wrch=1023
CSET full_threshold_negate_value=15999
CSET full_threshold_negate_value=8180
CSET id_width=4
CSET inject_dbit_error=false
CSET inject_dbit_error_axis=false
......@@ -141,7 +141,7 @@ CSET inject_sbit_error_wach=false
CSET inject_sbit_error_wdch=false
CSET inject_sbit_error_wrch=false
CSET input_data_width=64
CSET input_depth=16384
CSET input_depth=8192
CSET input_depth_axis=1024
CSET input_depth_rach=16
CSET input_depth_rdch=1024
......@@ -150,12 +150,12 @@ CSET input_depth_wdch=1024
CSET input_depth_wrch=16
CSET interface_type=Native
CSET output_data_width=32
CSET output_depth=32768
CSET output_depth=16384
CSET overflow_flag=false
CSET overflow_flag_axi=false
CSET overflow_sense=Active_High
CSET overflow_sense_axi=Active_High
CSET performance_options=First_Word_Fall_Through
CSET performance_options=Standard_FIFO
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_empty_type_axis=Empty
CSET programmable_empty_type_rach=Empty
......@@ -174,7 +174,7 @@ CSET rach_type=FIFO
CSET rdch_type=FIFO
CSET read_clock_frequency=1
CSET read_data_count=true
CSET read_data_count_width=16
CSET read_data_count_width=14
CSET register_slice_mode_axis=Fully_Registered
CSET register_slice_mode_rach=Fully_Registered
CSET register_slice_mode_rdch=Fully_Registered
......@@ -199,7 +199,7 @@ CSET underflow_sense_axi=Active_High
CSET use_clock_enable=false
CSET use_dout_reset=true
CSET use_embedded_registers=false
CSET use_extra_logic=true
CSET use_extra_logic=false
CSET valid_flag=false
CSET valid_sense=Active_High
CSET wach_type=FIFO
......@@ -208,12 +208,12 @@ CSET wrch_type=FIFO
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=true
CSET write_data_count_width=15
CSET write_data_count=false
CSET write_data_count_width=13
CSET wuser_width=1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2011-10-22T06:08:52Z
# END Extra information
GENERATE
# CRC: 9008abaa
# CRC: 110a0fe8
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