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AIDA-2020 TLU
Commit 9a0a1b3e authored by David Cussans's avatar David Cussans
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Changed order for add_files.tcl

parent e2316977
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Showing with 25 additions and 18 deletions
firmware/simulation/scripts/add_files.tcl
View file @ 9a0a1b3e
......@@ -7,6 +7,8 @@ vmap unimacro $xlib_vhdl/unimacro
vmap secureip $xlib_vlog/secureip
vmap xilinxcorelib $xlib_vhdl/xilinxcorelib
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/simulation_src/delay.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/simulation_src/dtype.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/ipbus_trans_decl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/ipbus_package.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_tx_mux.vhd
......@@ -65,34 +67,33 @@ project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/cloc
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/arrivalTimeLUT_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/external/opencores_i2c/i2c_master_top.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/slaves/hdl/ipbus_syncreg_v.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/slaves/hdl/ipbus_syncreg_v.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/slaves/hdl/ipbus_ctrlreg_v.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/synchronizeRegisters_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/stretchPulse_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/coincidenceLogic_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/single_pulse_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/triggerInputs_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/logic_clocks_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ethernet/sim/eth_mac_sim.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/sim/hdl/clock_sim.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/IPBusInterface_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/i2c_master_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/eventFormatter_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/eventBuffer_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/DUTInterfaces_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/DUTInterface_AIDA_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/DUTInterface_EUDET_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/single_pulse_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/coincidenceLogic_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/stretchPulse_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/synchronizeRegisters_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/DUTInterfaces_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/pulseClockDomainCrossing_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/T0_Shutter_Iface_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/test/clock_divider_s6.v
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/slaves/hdl/ipbus_syncreg_v.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/slaves/hdl/ipbus_ctrlreg_v.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ethernet/sim/eth_mac_sim.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/sim/hdl/clock_sim.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/simulation_src/pmtPulseGenerator_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/simulation_src/fmc-tlu_v0-1_test-bench.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/simulation_src/fmc-tlu_v0-1_eudet_test-bench.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/simulation_src/Dummy_DUT.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/simulation_src/delay.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/simulation_src/dtype.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/simulation_src/pmtPulseGenerator_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/T0_Shutter_Iface_rtl.vhd
project calculateorder
project close
......
firmware/simulation/scripts/setup.sh
View file @ 9a0a1b3e
#!/bin/sh
export MODELSIM_ROOT="/software/CAD/Mentor/2014_2015/HDS_2013.1b/questasim/"
# ... pclhcb50.cern.ch
export MODELSIM_ROOT="/opt/Mentor/questasim/"
#export MODELSIM_ROOT="/software/CAD/Mentor/2014_2015/HDS_2013.1b/questasim/"
#export MODELSIM_ROOT="/eda/mentor/2014-15/RHELx86/QUESTA-SV-AFV_10.4/questasim/"
export ISE_VHDL_MTI="/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/vhdl/questasim/10.4/lin64/"
export ISE_VLOG_MTI="/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/verilog/questasim/10.4/lin64/"
#export FW_WORKSPACE=../../../..
export XILINX=/opt/Xilinx/14.7/ISE_DS/ISE
export ISE_VHDL_MTI="$XILINX/vhdl/questasim/10.4/lin64/"
export ISE_VLOG_MTI="$XILINX/verilog/questasim/10.4/lin64/"
export FW_WORKSPACE=../../../..
vsim -c -do add_files.tcl
vsim -64 -c -do add_files.tcl
cp -r ${FW_WORKSPACE}/workspace/ipbus/firmware/ethernet/sim/modelsim_fli ./
cd modelsim_fli
./mac_fli_compile.sh
......
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