Commit e2316977 authored by David Cussans's avatar David Cussans

Changed number of registers in TriggerLogic to 16 - allows trigger hold-off word…

Changed number of registers in TriggerLogic to 16 - allows trigger hold-off word to be recorded and aux triggers. Also changed address map for PyChips and uHAL
parent c6751c4e
......@@ -25,7 +25,7 @@ architecture rtl of ipbus_ver is
begin
ipbus_out.ipb_rdata <= X"a618" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement).
ipbus_out.ipb_rdata <= X"a620" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement).
ipbus_out.ipb_ack <= ipbus_in.ipb_strobe;
ipbus_out.ipb_err <= '0';
......
......@@ -99,11 +99,13 @@ ARCHITECTURE rtl OF triggerLogic IS
signal s_PulseStretchWord : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0'); --! Length of trigger pulses
signal s_PulseDelayWord : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0'); --!number of cycles to delay trigger pulses.
signal s_TriggerHoldOffWord : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0'); --! minimum number of clock cycles between triggers
constant c_PARAM_WIDTH : positive := 5; -- length of pulse width and delay.
constant c_BYTE_WIDTH : positive := 8; -- trying to make code clearer...
constant c_N_CTRL : positive := 8;
constant c_N_STAT : positive := 8;
constant c_N_CTRL : positive := 16;
constant c_N_STAT : positive := 16;
signal s_controlRegStrobes : std_logic_vector(c_N_CTRL-1 downto 0) := ( others => '0') ; --!
--Bit strobes when control reg is loaded
signal s_status_to_ipbus, s_sync_status_to_ipbus : ipb_reg_v(c_N_STAT-1 downto 0);
......@@ -165,7 +167,11 @@ BEGIN
s_internal_veto <= s_veto_word(0);
s_PulseStretchWord <= s_sync_control_from_ipbus(6);
s_PulseDelayWord <= s_sync_control_from_ipbus(7);
s_TriggerHoldOffWord <= s_sync_control_from_ipbus(8);
s_external_veto_word(0) <= veto_i;
s_external_veto_word(g_IPBUS_WIDTH-1 downto 1) <= (others=>'0');
-- Map the status registers
s_status_to_ipbus(0) <= std_logic_vector(s_post_veto_trigger_counter);
s_status_to_ipbus(1) <= std_logic_vector(s_pre_veto_trigger_counter);
......@@ -173,11 +179,10 @@ BEGIN
s_status_to_ipbus(3) <= s_TriggerPattern;
s_status_to_ipbus(4) <= s_veto_word;
s_status_to_ipbus(5) <= s_external_veto_word;
s_external_veto_word(0) <= veto_i;
s_external_veto_word(g_IPBUS_WIDTH-1 downto 1) <= (others=>'0');
s_status_to_ipbus(6) <= s_PulseStretchWord;
s_status_to_ipbus(7) <= s_PulseDelayWord;
-- s_status_to_ipbus(6) <= std_logic_vector(s_aux_trigger_counter);-- Bodge
s_status_to_ipbus(8) <= s_TriggerHoldOffWord;
s_status_to_ipbus(9) <= std_logic_vector(s_aux_trigger_counter);-- Bodge
-- purpose: Delay pulse that loads trigger pattern by one cycle of IPBus clk.
-- type : combinational
......
......@@ -23,19 +23,24 @@ ThrCount2R 0x0000004b 0xffffffff 1 0
ThrCount3R 0x0000004c 0xffffffff 1 0
*
* trigger logic = 0x060 **Note the different read and write directions
PostVetoTriggersR 0x00000068 0xffffffff 1 0
PreVetoTriggersR 0x00000069 0xffffffff 1 0
InternalTriggerIntervalW 0x00000062 0xffffffff 1 1
InternalTriggerIntervalR 0x0000006A 0xffffffff 1 0
InternalTriggerIntervalW 0x00000062 0xffffffff 0 1
TriggerPatternW 0x00000063 0xffffffff 0 1
TriggerPatternR 0x0000006B 0xffffffff 1 0
TriggerVetoW 0x00000064 0xffffffff 0 1
TriggerVetoR 0x0000006C 0xffffffff 1 0
ExternalTriggerVetoR 0x0000006D 0xffffffff 1 0
PulseStretchW 0x00000066 0xffffffff 0 1
PulseStretchR 0x0000006E 0xffffffff 1 0
PulseDelayW 0x00000067 0xffffffff 0 1
PulseDelayR 0x0000006F 0xffffffff 1 0
TriggerHoldOffW 0x00000068 0xffffffff 0 1
PostVetoTriggersR 0x00000070 0xffffffff 1 0
PreVetoTriggersR 0x00000071 0xffffffff 1 0
InternalTriggerIntervalR 0x00000072 0xffffffff 1 0
TriggerPatternR 0x00000073 0xffffffff 1 0
TriggerVetoR 0x00000074 0xffffffff 1 0
ExternalTriggerVetoR 0x00000075 0xffffffff 1 0
PulseStretchR 0x00000076 0xffffffff 1 0
PulseDelayR 0x00000077 0xffffffff 1 0
TriggerHoldOffR 0x00000078 0xffffffff 1 0
AuxTriggerCountR 0x00000079 0xffffffff 1 0
*
* event buffer = 0x080
EventFifoData 0x00000080 0xffffffff 1 0
......
......@@ -21,18 +21,21 @@
</node>
<node id="triggerLogic" address="0x060" description="Trigger logic configuration">
<node id="PostVetoTriggersR" address="0x8" permission="r" description="" />
<node id="PreVetoTriggersR" address="0x9" permission="r" description="" />
<node id="PostVetoTriggersR" address="0x10" permission="r" description="" />
<node id="PreVetoTriggersR" address="0x11" permission="r" description="" />
<node id="InternalTriggerIntervalW" address="0x2" permission="w" description="" />
<node id="InternalTriggerIntervalR" address="0xa" permission="r" description="" />
<node id="InternalTriggerIntervalR" address="0x12" permission="r" description="" />
<node id="TriggerPatternW" address="0x3" permission="w" description="" />
<node id="TriggerPatternR" address="0xb" permission="r" description="" />
<node id="TriggerPatternR" address="0x13" permission="r" description="" />
<node id="TriggerVetoW" address="0x4" permission="w" description="" />
<node id="TriggerVetoR" address="0xc" permission="r" description="" />
<node id="ExternalTriggerVetoR" address="0xd" permission="r" description="" />
<node id="TriggerVetoR" address="0x14" permission="r" description="" />
<node id="ExternalTriggerVetoR" address="0x15" permission="r" description="" />
<node id="ResetCountersW" address="0x6" permission="w" description="" />
<node id="PulseStretchR" address="0xf" permission="r" description="" />
<node id="PulseStretchR" address="0x17" permission="r" description="" />
<node id="PulseStretchW" address="0x7" permission="w" description="" />
<node id="TriggerHoldOffR" address="0x18" permission="r" description="" />
<node id="TriggerHoldOffW" address="0x8" permission="r" description="" />
<node id="AuxTriggerCountR" address="0x19" permission="r" description="" />
</node>
<node id="eventBuffer" address="0x080" description="Event buffer">
......
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