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AIDA-2020 TLU
Commit c6751c4e authored by David Cussans's avatar David Cussans
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replaced timestamp counter with high/low parts with single 48-bit counter. seems… 

replaced timestamp counter with high/low parts with single 48-bit counter. seems to eliminate bug with bit flipping high prematurely. also gives shorter and easier to read code
parent 02df9202
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Showing with 15 additions and 39 deletions
firmware/hdl/common/eventFormatter_rtl.vhd
View file @ c6751c4e
......@@ -154,8 +154,9 @@ ARCHITECTURE rtl OF eventFormatter IS
constant c_COARSE_TIMESTAMP_WIDTH : positive := 48; -- ! Number of bits in 40MHz timestamp
constant c_COARSE_TIMESTAMP_L_WIDTH : positive := 32; -- ! Number of bits in 40MHz timestamp lower bits
constant c_COARSE_TIMESTAMP_H_WIDTH : positive := 16; -- ! Number of bits in 40MHz timestamp higher bits
signal s_coarse_timestamp_l, s_coarse_timestamp_l_d1, s_coarse_timestamp_l_d2, s_coarse_timestamp_l_d3 : unsigned(c_COARSE_TIMESTAMP_L_WIDTH-1 downto 0) := (others => '0'); -- 40MHz timestamp.
signal s_coarse_timestamp_h, s_coarse_timestamp_h_d1, s_coarse_timestamp_h_d2, s_coarse_timestamp_h_d3 : unsigned(c_COARSE_TIMESTAMP_H_WIDTH-1 downto 0) := (others => '0'); -- 40MHz timestamp.
-- signal s_coarse_timestamp_l, s_coarse_timestamp_l_d1, s_coarse_timestamp_l_d2, s_coarse_timestamp_l_d3 : unsigned(c_COARSE_TIMESTAMP_L_WIDTH-1 downto 0) := (others => '0'); -- 40MHz timestamp.
-- signal s_coarse_timestamp_h, s_coarse_timestamp_h_d1, s_coarse_timestamp_h_d2, s_coarse_timestamp_h_d3 : unsigned(c_COARSE_TIMESTAMP_H_WIDTH-1 downto 0) := (others => '0'); -- 40MHz timestamp.
signal s_coarse_timestamp : std_logic_vector(c_COARSE_TIMESTAMP_WIDTH-1 downto 0) := (others => '0'); -- 40MHz timestamp.
signal s_coarse_timestamp_ipbus : ipb_reg_v(1 downto 0) := ( others => (others => '0')); --! 40MHz timestamp on IPB clock domain.
signal s_timestamp_h_en : std_logic:='0';
......@@ -225,7 +226,7 @@ BEGIN
g_NUM_REGISTERS => 2 )
port map (
clk_input_i => clk_4x_logic_i,
data_i => ( std_logic_vector( "0000000000000000" & s_coarse_timestamp_h_d3 ) , std_logic_vector(s_coarse_timestamp_l_d3) ) ,
data_i => ( "0000000000000000" & s_coarse_timestamp(s_coarse_timestamp'left downto 32) , s_coarse_timestamp(31 downto 0) ) ,
data_o => s_coarse_timestamp_ipbus,
clk_output_i => ipbus_clk_i
);
......@@ -324,12 +325,6 @@ BEGIN
s_word2_d2 <= s_word2_d1;
s_word2_d3 <= s_word2_d2;
s_coarse_timestamp_l_d1 <= s_coarse_timestamp_l;
s_coarse_timestamp_l_d2 <= s_coarse_timestamp_l_d1;
s_coarse_timestamp_l_d3 <= s_coarse_timestamp_l_d2;
s_coarse_timestamp_h_d1 <= s_coarse_timestamp_h;
s_coarse_timestamp_h_d2 <= s_coarse_timestamp_h_d1;
s_coarse_timestamp_h_d3 <= s_coarse_timestamp_h_d2;
end if;
end process;
......@@ -355,7 +350,7 @@ BEGIN
--s_word0 <= s_evttype(0) & s_var(0) & std_logic_vector(s_coarse_timestamp_d2);
s_word0 <= s_evttype & s_var & std_logic_vector(s_coarse_timestamp_h_d2) & std_logic_vector(s_coarse_timestamp_l_d2);
s_word0 <= s_evttype & s_var & s_coarse_timestamp;
s_word1 <= "000" & trigger_times_d1(0) & "000" & trigger_times_d1(1) &
"000" & trigger_times_d1(2) & "000" & trigger_times_d1(3) &
......@@ -392,36 +387,17 @@ BEGIN
end if;
end process;
cmp_timeStampCounter: entity work.counterWithReset
generic map (
g_COUNTER_WIDTH => s_coarse_timestamp'length)
port map (
clock_i => clk_4x_logic_i,
reset_i => s_reset_timestamp_4x or logic_reset_i,
enable_i => logic_strobe_i,
result_o => s_coarse_timestamp);
-- purpose: Keep track of 40MHz timestamp
-- type : sequential
-- inputs : clk_4x_logic_i
-- outputs:
p_timestamp_l: process (clk_4x_logic_i, logic_reset_i)
begin -- process p_timestamp
if rising_edge(clk_4x_logic_i) then -- rising clock edge
if logic_reset_i = '1' or s_reset_timestamp_4x = '1' then
s_coarse_timestamp_l <= ( others => '0');
elsif ( logic_strobe_i = '1' ) then
s_coarse_timestamp_l <= s_coarse_timestamp_l + 1;
end if;
end if;
end process p_timestamp_l;
s_timestamp_h_en <= '1' when s_coarse_timestamp_l = x"ffff" else
'0';
p_timestamp_h: process (clk_4x_logic_i, logic_reset_i)
begin -- process p_timestamp
if rising_edge(clk_4x_logic_i) then -- rising clock edge
if logic_reset_i = '1' or s_reset_timestamp_4x = '1' then
s_coarse_timestamp_h <= ( others => '0');
elsif ( logic_strobe_i = '1' ) and (s_timestamp_h_en='1') then
s_coarse_timestamp_h <= s_coarse_timestamp_h + 1;
end if;
end if;
end process p_timestamp_h;
-- Generate data in format decided at DESY. Put out two strobes for the
-- two 64 bit words.
-- get trigger inputs to also generate a global time-stamp ??
......
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