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AIDA-2020 TLU
Commit 350bfc2c authored by David Cussans's avatar David Cussans
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Adding code to disable shutter when run is stopped 

(T0 pulse is generated when run_active goes high.)
parent b5401c78
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components/tlu/firmware/hdl/T0_Shutter_Iface_rtl.vhd
View file @ 350bfc2c
......@@ -63,7 +63,8 @@ ENTITY T0_Shutter_Iface IS
--! Output Signals
shutter_o: OUT STD_LOGIC; --! Shutter signal.
shutter_veto_o: OUT STD_LOGIC; --! Goes high when shutter vetoes triggers
T0_o: out std_logic --! T0 synchronization pulse
run_active_o: out std_logic; --! goes high when run is active.
T0_o: out std_logic --! T0 synchronization pulse. Pulses on leading edge of run_active_o
);
END T0_Shutter_Iface;
......@@ -80,16 +81,16 @@ ARCHITECTURE rtl OF T0_Shutter_Iface IS
signal s_enable_sequence : std_logic ; --! take high to enable sequence
signal s_enable_internal_cycle : std_logic ; --! take high to enable internal sequence
signal s_T0_ipbus : std_logic; --! T0 synchronization signal on IPBus clock domain.
-- signal s_run_active : std_logic; --! Take active to issue T0 pulse and enable shutters
constant c_NUM_CTRL_REGS : integer := 9;
-- signal s_T0_ipbus : std_logic; --! T0 synchronization signal on IPBus clock domain.
signal s_run_active : std_logic; --! Take active to issue T0 pulse and enable shutters
constant c_NUM_CTRL_REGS : integer := 8;
constant c_NUM_STAT_REGS : integer := 1;
signal s_ipbus_statusregs: ipb_reg_v(c_NUM_STAT_REGS - 1 downto 0) := (others => (others => '0'));
signal s_ipbus_controlregs: ipb_reg_v(c_NUM_CTRL_REGS - 1 downto 0);
constant c_ipbus_qmask : ipb_reg_v(c_NUM_CTRL_REGS - 1 downto 0) := (others => (others => '1'));
constant c_T0_address : std_logic_vector(3 downto 0) := "1000"; --! Write 1 to bit 0 of this address to produce a enable shutters and produce T0 pulse
-- constant c_T0_address : std_logic_vector(3 downto 0) := "1000"; --! Write 1 to bit 0 of this address to produce a enable shutters and produce T0 pulse
begin
......@@ -132,42 +133,45 @@ begin
);
-- s_enable_sequence <= ( s_ipbus_controlregs(0)(0) and s_run_active ) when (rising_edge(clk_4x_i) and (clk_4x_strobe_i = '1'));
s_enable_sequence <= s_ipbus_controlregs(0)(0) when (rising_edge(clk_4x_i) and (clk_4x_strobe_i = '1'));
s_enable_sequence <= ( s_ipbus_controlregs(0)(0) and s_run_active) when (rising_edge(clk_4x_i) and (clk_4x_strobe_i = '1'));
-- s_run_active <= s_ipbus_controlregs(8)(0); --! Set to 1 to issue T0 and start shutter
s_enable_internal_cycle <= s_ipbus_controlregs(0)(1);
s_trigger_source_select <= s_ipbus_controlregs(1);
s_internal_cycle_length <= s_ipbus_controlregs(2);
s_threshold_t1 <= s_ipbus_controlregs(3);
s_threshold_t2 <= s_ipbus_controlregs(4);
s_threshold_t3 <= s_ipbus_controlregs(5);
s_internal_cycle_length <= s_ipbus_controlregs(2);
s_run_active <= s_ipbus_controlregs(6)(0);
run_active_o <= s_run_active;
-- A bodge. I can't figure out which standard IPBus register generates a
-- pulse, so put this logic in parallel.
--------------------
ipbus_generateT0: process (ipbus_clk_i)
begin -- process ipbus_clk_i
if rising_edge(ipbus_clk_i) then
---- A bodge. I can't figure out which standard IPBus register generates a
---- pulse, so put this logic in parallel.
----------------------
--ipbus_generateT0: process (ipbus_clk_i)
--begin -- process ipbus_clk_i
--if rising_edge(ipbus_clk_i) then
if (ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '1' and ipbus_i.ipb_addr(3 downto 0) = c_T0_address ) then
s_T0_ipbus <= '1'; -- set T0 signal high
else
s_T0_ipbus <= '0';
end if;
-- if (ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '1' and ipbus_i.ipb_addr(3 downto 0) = c_T0_address ) then
-- s_T0_ipbus <= '1'; -- set T0 signal high
-- else
-- s_T0_ipbus <= '0';
-- end if;
end if;
end process ipbus_generateT0;
-- end if;
--end process ipbus_generateT0;
--! Retime T0 generated by IPBus onto clk_4x and align with strobe
cmp_T0_retime: entity work.stretchPulse4x
port map (
clk_4x_i => clk_4x_i,
clk_4x_strobe_i => clk_4x_strobe_i,
-- pulse_i => s_run_active,
pulse_i => s_T0_ipbus,
pulse_i => s_run_active,
-- pulse_i => s_T0_ipbus,
pulse_o => T0_o);
END rtl;
projects/TLU_v1e/addr_table/TLUaddrmap.xml
View file @ 350bfc2c
......@@ -4,12 +4,12 @@
<!-- Registers for the DUTs. These should be correct -->
<node id="DUTInterfaces" address="0x1000" description="DUT Interfaces control registers" fwinfo="endpoint;width=4">
<node id="DutMaskW" address="0x0" permission="w" description="" />
<node id="DUTMaskW" address="0x0" permission="w" description="" />
<node id="IgnoreDUTBusyW" address="0x1" permission="w" description="" />
<node id="IgnoreShutterVetoW" address="0x2" permission="w" description="" />
<node id="DUTInterfaceModeW" address="0x3" permission="w" description="" />
<node id="DUTInterfaceModeModifierW" address="0x4" permission="w" description="" />
<node id="DutMaskR" address="0x8" permission="r" description="" />
<node id="DUTMaskR" address="0x8" permission="r" description="" />
<node id="IgnoreDUTBusyR" address="0x9" permission="r" description="" />
<node id="IgnoreShutterVetoR" address="0xA" permission="r" description="" />
<node id="DUTInterfaceModeR" address="0xB" permission="r" description="" />
......@@ -21,10 +21,11 @@
<node id="ShutterSelectRW" address="0x1" permission="rw" description="Selects which input is used to trigger shutter"/>
<node id="InternalShutterPeriodRW" address="0x2" permission="rw" description="Internal trig generator period ( units = number of strobe pulses)"/>
<node id="ShutterOnTimeRW" address="0x3" permission="rw" description="Time between input trigger being received and shutter asserted(T1) ( units = number of strobe pulses)"/>
<node id="VetoOffTimeRW" address="0x4" permission="rw" description="time between input trigger and veto being de-asserted(T2) ( units = number of strobe pulses)"/>
<node id="ShutterVetoOffTimeRW" address="0x4" permission="rw" description="time between input trigger and veto being de-asserted(T2) ( units = number of strobe pulses)"/>
<node id="ShutterOffTimeRW" address="0x5" permission="rw" description="time between input trigger and time at which shutter de-asserted and veto reasserted(T3) ( units = number of strobe pulses)"/>
<node id="PulseT0" address="0x8" permission="rw" description="Writing to Bit-0 of this register causes sync line to pulse for one strobe-pulse interval"/>
<node id="RunActiveRW" address="0x6" permission="rw" description="Writing '1' to Bit-0 of this register raises the run_active line and causes sync line to pulse for one strobe-pulse interval"/>
</node>
<!-- I2C registers. Tested ok.-->
<node id="i2c_master" address="0x3000" description="I2C Master interface" fwinfo="endpoint;width=3">
<node id="i2c_pre_lo" address="0x0" mask="0x000000ff" permission="rw" description="" />
......
projects/TLU_v1e/firmware/hdl/top_enclustra_tlu_v1e.vhd
View file @ 350bfc2c
......@@ -25,7 +25,7 @@ use work.ipbus.ALL;
entity top is
generic(
constant FW_VERSION : unsigned(31 downto 0):= X"1e000010"; -- Firmware revision. Remember to change this as needed.
constant FW_VERSION : unsigned(31 downto 0):= X"1e000011"; -- Firmware revision. Remember to change this as needed.
g_NUM_DUTS : positive := 4; -- <- was 3
g_NUM_TRIG_INPUTS :positive := 6;-- <- was 4
g_NUM_EDGE_INPUTS :positive := 6;-- <-- was 4
......@@ -106,7 +106,7 @@ architecture rtl of top is
--signal s_i2c_scl_i : std_logic;
------------------------------------------
-- Internal signal declarations
SIGNAL T0_o : std_logic;
SIGNAL s_T0 : std_logic;
SIGNAL buffer_full_o : std_logic; --! Goes high when event buffer almost full
SIGNAL clk_8x_logic : std_logic; -- 320MHz clock
SIGNAL clk_4x_logic : std_logic; --! normally 160MHz
......@@ -132,6 +132,7 @@ architecture rtl of top is
--SIGNAL s_i2c_scl_enb : std_logic;
--SIGNAL s_i2c_sda_enb : std_logic;
SIGNAL s_shutter : std_logic; --! shutter signal from TimePix, retimed onto local clock
signal s_run_active : std_logic; --! Goes high when run is active.
SIGNAL s_triggerLogic_reset : std_logic;
SIGNAL shutter_cnt_i : std_logic_vector(g_SPILL_COUNTER_WIDTH-1 DOWNTO 0);
SIGNAL shutter_i : std_logic;
......@@ -142,8 +143,8 @@ architecture rtl of top is
SIGNAL trigger_count : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0);
SIGNAL trigger_times : t_triggerTimeArray(g_NUM_TRIG_INPUTS-1 DOWNTO 0); --! trigger arrival time ( w.r.t. logic_strobe)
SIGNAL triggers : std_logic_vector(g_NUM_TRIG_INPUTS-1 DOWNTO 0); --! Rising edge of trigger inputs
SIGNAL veto_o : std_logic; --! goes high when one or more DUT are busy
signal shutter_veto_o : std_logic; --! Goes high when triggers should be vetoed by shutter
SIGNAL s_veto : std_logic; --! goes high when one or more DUT are busy
signal s_shutter_veto : std_logic; --! Goes high when triggers should be vetoed by shutter
signal ctrl, stat: ipb_reg_v(0 downto 0);
--My signals
--SIGNAL busy_toggle_o : std_logic_vector(g_NUM_DUTS-1 downto 0);
......@@ -191,6 +192,7 @@ architecture rtl of top is
ipbus_clk_i : IN std_logic;
ipbus_i : IN ipb_wbus;
T0_o : OUT std_logic;
run_active_o : out std_logic;
accelerator_signals_i : in std_logic_vector(g_NUM_ACCELERATOR_SIGNALS-1 DOWNTO 0);
ipbus_o : OUT ipb_rbus;
shutter_veto_o: out std_logic;
......@@ -410,14 +412,14 @@ begin
-- ModuleWare code(v1.12) for instance 'I19' of 'merge'
--gpio_hdr <= dout1 & dout & s_shutter & T0_o;
-- ModuleWare code(v1.12) for instance 'I8' of 'sor'
overall_veto <= buffer_full_o OR veto_o ; -- or shutter_veto_o;
overall_veto <= buffer_full_o OR s_veto or s_shutter_veto when rising_edge(clk_4x_logic);
-- ModuleWare code(v1.12) for instance 'I16' of 'sor'
s_triggerLogic_reset <= logic_reset OR T0_o;
s_triggerLogic_reset <= logic_reset OR s_T0;
i2c_reset <= '1';
clk_gen_rst <= '1';
---gpio <= strobe_8x_logic;---
gpio <= veto_o;---
gpio <= s_veto;---
--gpio <= busy_i(1);---
--Set diff clock out to 0 because we cannot have the correct differential voltage output
......@@ -582,7 +584,7 @@ begin
ipbus_o => ipbrr(N_SLV_EVENT_FORMATTER),
data_strobe_o => data_strobe,
event_data_o => event_data,
reset_timestamp_i => T0_o,
reset_timestamp_i => s_T0,
reset_timestamp_o => OPEN
);
......@@ -614,9 +616,10 @@ begin
clk_4x_i => clk_4x_logic,
clk_4x_strobe_i => strobe_4x_logic,
accelerator_signals_i => triggers,
T0_o => T0_o,
T0_o => s_T0,
run_active_o => s_run_active,
shutter_o => s_shutter,
shutter_veto_o => shutter_veto_o,
shutter_veto_o => s_shutter_veto,
ipbus_clk_i => clk_ipb,
ipbus_i => ipbww(N_SLV_SHUTTER),
ipbus_o => ipbrr(N_SLV_SHUTTER)
......@@ -633,9 +636,9 @@ begin
strobe_4x_logic_i => strobe_4x_logic,
trigger_counter_i => trigger_count,
trigger_i => overall_trigger,
reset_or_clk_to_dut_i => T0_o,
reset_or_clk_to_dut_i => s_T0,
shutter_to_dut_i => s_shutter,
shutter_veto_i => shutter_veto_o,
shutter_veto_i => s_shutter_veto,
ipbus_clk_i => clk_ipb,
ipbus_i => ipbww(N_SLV_DUTINTERFACES),
ipbus_reset_i => rst_ipb,
......@@ -651,7 +654,7 @@ begin
--shutter_to_dut_n_o => shutter_to_dut_n_o,
--shutter_to_dut_p_o => shutter_to_dut_p_o,
shutter_to_dut => cont_o,
veto_o => veto_o
veto_o => s_veto
);
------------------------------------------
......
projects/TLU_v1e/firmware/ucf/TLU_enclustra_v1e.xdc
View file @ 350bfc2c
......@@ -129,6 +129,9 @@ create_clock -period 25.000 -name sysclk_40_i_p -waveform {0.000 12.500} [get_po
set_input_delay -clock [get_clocks [get_clocks -of_objects [get_pins I4/pll_base_inst/CLKOUT0]]] -rise -min 0.300 [get_ports -regexp -filter { NAME =~ ".*thresh.*" && DIRECTION == "IN" }]
set_input_delay -clock [get_clocks [get_clocks -of_objects [get_pins I4/pll_base_inst/CLKOUT0]]] -rise -max 1.400 [get_ports -regexp -filter { NAME =~ ".*thresh.*" && DIRECTION == "IN" }]
set_clock_groups -asynchronous -group [list [get_clocks clk_ipb_i] [get_clocks sysclk]] -group [list [get_clocks s_clk160] [get_clocks sysclk_40_i_p]]
connect_debug_port u_ila_0/probe13 [get_nets [list shutter_veto_o]]
connect_debug_port u_ila_0/probe16 [get_nets [list veto_i]]
create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
......@@ -141,12 +144,12 @@ set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list I4/clk_4x_logic_o]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 6 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {I5/trigger_o[0]} {I5/trigger_o[1]} {I5/trigger_o[2]} {I5/trigger_o[3]} {I5/trigger_o[4]} {I5/trigger_o[5]}]]
set_property port_width 4 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {I9/s_DUT_ignore_busy[0]} {I9/s_DUT_ignore_busy[1]} {I9/s_DUT_ignore_busy[2]} {I9/s_DUT_ignore_busy[3]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 4 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {I9/s_DUT_ignore_busy[0]} {I9/s_DUT_ignore_busy[1]} {I9/s_DUT_ignore_busy[2]} {I9/s_DUT_ignore_busy[3]}]]
set_property port_width 6 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {I5/trigger_o[0]} {I5/trigger_o[1]} {I5/trigger_o[2]} {I5/trigger_o[3]} {I5/trigger_o[4]} {I5/trigger_o[5]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
set_property port_width 6 [get_debug_ports u_ila_0/probe2]
......@@ -194,23 +197,15 @@ connect_debug_port u_ila_0/probe12 [get_nets [list I6/s_trigger]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
set_property port_width 1 [get_debug_ports u_ila_0/probe13]
connect_debug_port u_ila_0/probe13 [get_nets [list shutter_veto_o]]
connect_debug_port u_ila_0/probe13 [get_nets [list I6/trigger_i]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
set_property port_width 1 [get_debug_ports u_ila_0/probe14]
connect_debug_port u_ila_0/probe14 [get_nets [list I6/trigger_i]]
connect_debug_port u_ila_0/probe14 [get_nets [list I10/cmp_coincidence_logic/trigger_o]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
set_property port_width 1 [get_debug_ports u_ila_0/probe15]
connect_debug_port u_ila_0/probe15 [get_nets [list I10/cmp_coincidence_logic/trigger_o]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
set_property port_width 1 [get_debug_ports u_ila_0/probe16]
connect_debug_port u_ila_0/probe16 [get_nets [list veto_i]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
set_property port_width 1 [get_debug_ports u_ila_0/probe17]
connect_debug_port u_ila_0/probe17 [get_nets [list I9/veto_o]]
connect_debug_port u_ila_0/probe15 [get_nets [list I9/veto_o]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
......
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