Skip to content

A
AIDA-2020 TLU
Commit 6835bd75 authored by David Cussans's avatar David Cussans
Browse files
Options

Checking in modified files before taking tag. single_pulse changes not tested… 

Checking in modified files before taking tag. single_pulse changes not tested but should be harmless.
parent 034e8ac6
Hide whitespace changes
Inline Side-by-side
Showing with 58 additions and 18 deletions
firmware/hdl/common/single_pulse_rtl.vhd
View file @ 6835bd75
......@@ -3,8 +3,6 @@
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
-------------------------------------------------------------------------------
--
......@@ -21,6 +19,9 @@ use IEEE.STD_LOGIC_1164.ALL;
--! @brief gives a single cycle pulse ( high active) following the rising edge of LEVEL
entity single_pulse is
generic (
g_PRE_REGISTER : boolean := false; -- --! Set true to put a register before rising edge detect
g_POST_REGISTER : boolean := false); -- --! Set tru to put a register after rising edge detect
port (
level : in std_logic; --! When LEVEL goes high, PULSE goes high for one clock cycle
clk : in std_logic; --! rising edge active
......@@ -30,24 +31,63 @@ end entity single_pulse;
architecture rtl of single_pulse is
signal x, v : std_logic;
signal pre_level, pre_pulse , x, v : std_logic;
begin -- architecture rtl
ff1: process (clk , level) is
begin -- process ff1
if rising_edge(clk) then
x <= level;
end if;
end process ff1;
ff2: process (clk , x) is
begin -- process ff2
if rising_edge(clk) then
v <= not x;
end if;
end process ff2;
-----------------------------------------------
-- Optional register on input
-----------------------------------------------
gen_pre_ff: if g_PRE_REGISTER=true generate
ffpre: process (clk , level) is
begin -- process ff1
if rising_edge(clk) then
pre_level <= level;
end if;
end process ffpre;
end generate gen_pre_ff;
gen_no_pre_ff: if g_PRE_REGISTER=false generate
pre_level <= level;
end generate gen_no_pre_ff;
-----------------------------------------------
-- Register signal
-----------------------------------------------
ff1: process (clk , level) is
begin -- process ff1
if rising_edge(clk) then
x <= pre_level;
end if;
end process ff1;
-----------------------------------------------
-- Edge detection logic
-----------------------------------------------
ff2: process (clk , x) is
begin -- process ff2
if rising_edge(clk) then
v <= not x;
end if;
end process ff2;
pulse <= ( x and v );
pre_pulse <= ( x and v );
-----------------------------------------------
-- Optional register on output
-----------------------------------------------
gen_post_ff: if g_POST_REGISTER=true generate
ffpost: process (clk , level) is
begin -- process ff1
if rising_edge(clk) then
pulse <= pre_pulse;
end if;
end process ffpost;
end generate gen_post_ff;
gen_no_post_ff: if g_POST_REGISTER=false generate
pulse <= pre_pulse;
end generate gen_no_post_ff;
end architecture rtl;
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment