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AIDA-2020 TLU
Commit 6f451125 authored by David Cussans's avatar David Cussans
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Changes to run simulation with interfaces in EUDET mode.

Added Dummy_DUT.vhd - which clocks out trigger number

Added delay.vhd , dtype.vhd ( used by  DUTInterface_EUDET_rtl.vhd )

Edited comments in DUTInterface_EUDET_rtl.vhd

Wrote test bench which instantiates dummy EUDET DUTs ( fmc-tlu_v0-1_eudet_test-bench.vhd , based on fmc-tlu_v0-1_test-bench.vhd )

Created spread-sheet to keep track of verification tests on firmware.

Wrote script to put DUTs into AIDA mode ( test_aida_tlu_internal_triggers_eudet_v2.py , based on test_aida_tlu_internal_triggers_v2.py )
parent cbe603f8
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firmware/hdl/common/DUTInterface_EUDET_rtl.vhd
View file @ 6f451125
......@@ -143,7 +143,6 @@ end process;
-- purpose: Determine the next state
-- type : combinational
-- inputs : state,Dut_Busy_r2, trigger_i
-- state_logic: process (state, trigger_i , handshake_mode_i , enable_dut_veto_i , dut_clk_r2, dut_busy_r2 )
state_logic: process (state, trigger_i , enable_dut_veto_i , dut_clk_r2, dut_busy_r2 )
begin -- process state_logic
case state is
......
firmware/hdl/common/ipbus_ver.vhd
View file @ 6f451125
......@@ -25,7 +25,7 @@ architecture rtl of ipbus_ver is
begin
ipbus_out.ipb_rdata <= X"a610" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement).
ipbus_out.ipb_rdata <= X"a611" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement).
ipbus_out.ipb_ack <= ipbus_in.ipb_strobe;
ipbus_out.ipb_err <= '0';
......
firmware/scripts/test_aida_tlu_internal_triggers_eudet_v2.py 0 → 100644
View file @ 6f451125
#
# Script to exercise AIDA mini-TLU
#
# David Cussans, December 2012
#
# Hacked to only test internal triggers
from PyChipsUser import *
from FmcTluI2c import *
import sys
import time
bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
# Assume DIP-switch controlled address. Switches at 1
board = ChipsBusUdp(bAddrTab,"192.168.200.32",50001)
# Check the bus for I2C devices
#executeI2C = True
executeI2C = False
if executeI2C:
boardi2c = FmcTluI2c(board)
boardId = boardi2c.get_serial_number()
print "FMC-TLU serial number = " , boardId
boardi2c.set_threshold_voltage(7, -0.2)
firmwareID=board.read("FirmwareId")
print "Firmware = " , hex(firmwareID)
print "Disable data recording"
board.write("Enable_Record_Data",0)
Enable_Record_Data = board.read("Enable_Record_Data")
print "Event recording flags read back as = ",Enable_Record_Data
print "Enabling all DUTs "
board.write("DUTMaskW",7)
DUTMask = board.read("DUTMaskR")
print "DUT mask read back as " , DUTMask
print "Disable Trigger veto by DUT Busy"
board.write("IgnoreDUTBusyW", 7)
IgnoreDUTBusyW = board.read("IgnoreDUTBusyR")
print "DUT ignore BUSY veto read back as " , IgnoreDUTBusyW
print "Disable Trigger veto by DUT Shutter"
board.write("IgnoreShutterVetoW", 1)
IgnoreShutterVetoW = board.read("IgnoreShutterVetoR")
print "DUT ignore shutter veto read back as " , IgnoreShutterVetoW
print "Set DUT into EUDET mode"
board.write("DUTInterfaceModeW", 0x00)
DUTInterfaceModeR = board.read("DUTInterfaceModeR")
print "DUT mode read back as " , DUTInterfaceModeR
print "Set DUT mode modifier to zero ( don't allow DUT_CLK to veto ) "
board.write("DUTInterfaceModeModifierW", 0x00)
DUTInterfaceModeModifierR = board.read("DUTInterfaceModeModifierR")
print "DUT mode modifier read back as " , DUTInterfaceModeModifierR
print "Set Pulse stretch"
board.write("PulseStretchW", 0x00)
PulseStretchR = board.read("PulseStretchR")
print "DUT mode modifier read back as " , PulseStretchR
print "Set Pulse delay"
board.write("PulseDelayW", 0x00)
PulseDelayR = board.read("PulseDelayR")
print "DUT mode modifier read back as " , PulseDelayR
print "Turn off trigger veto"
board.write("TriggerVetoW",0)
TriggerVeto = board.read("TriggerVetoR")
print "Trigger veto read back as " , TriggerVeto
ExternalTriggerVeto = board.read("ExternalTriggerVetoR")
print "External veto = ", ExternalTriggerVeto
TriggerInterval = 0xABC
#TriggerInterval = 0x0000
print "Setting internal trigger interval to " , TriggerInterval
board.write("InternalTriggerIntervalW",TriggerInterval) #0->Internal pulse generator disabled. Any other value will generate pulses with a frequency of n*6.25ns
trigInterval = board.read("InternalTriggerIntervalR")
print "Trigger interval read back as ", trigInterval , "(should be 2 less than written)"
LogicClocksCSR = board.read("LogicClocksCSR")
print "Clocks status = " , hex(LogicClocksCSR)
numLoops = 3
for iLoop in range(0,numLoops):
preVetotriggerCount = board.read("PreVetoTriggersR")
postVetotriggerCount = board.read("PostVetoTriggersR")
print "pre , post veto triggers = " , preVetotriggerCount , postVetotriggerCount
timestampHigh = board.read("CurrentTimestampHR")
timestampLow = board.read("CurrentTimestampLR")
print "Current timestamp High,Low (hex) = " , hex(timestampHigh) , hex(timestampLow)
time.sleep( 1.0 )
firmware/simulation/scripts/add_files.tcl
View file @ 6f451125
......@@ -87,6 +87,10 @@ project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/slaves/hdl/ipbus_c
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ethernet/sim/eth_mac_sim.vhd
project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/sim/hdl/clock_sim.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/simulation_src/fmc-tlu_v0-1_test-bench.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/simulation_src/fmc-tlu_v0-1_eudet_test-bench.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/simulation_src/Dummy_DUT.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/simulation_src/delay.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/simulation_src/dtype.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/simulation_src/pmtPulseGenerator_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/T0_Shutter_Iface_rtl.vhd
......
firmware/simulation/verification/.~lock.verification_tests.xlsx# 0 → 100644
View file @ 6f451125
David Cussans,phdgc,maroc.phy.bris.ac.uk,03.09.2015 14:58,file:///users/phdgc/.config/libreoffice/4;
\ No newline at end of file
firmware/simulation_src/Dummy_DUT.vhd 0 → 100644
View file @ 6f451125
--------------------------------------------------------------------------------
--! @file
--
-- Company: University of Bristol
-- Engineer: David Cussans
--
-- Create Date: 16:28:09 07/07/2006
-- Design Name:
-- Module Name: Dummy_DUT - RTL
-- Project Name:
-- Target Devices:
-- Tool versions:
--
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- constant definitions.
--! @brief Pretends to be an EUDET-style device under test. Can also be synthesiszed for testing in hardware.
entity Dummy_DUT is
Port (
CLK : in STD_LOGIC; --! this is the USB clock.
RST : in STD_LOGIC; --! Synchronous clock
Trigger : in STD_LOGIC; --! Trigger from TLU
Busy : out STD_LOGIC; --! Busy to TLU
DUTClk : out STD_LOGIC; --! clock from DUT
TriggerNumber : out STD_LOGIC_VECTOR(15 downto 0);
TriggerNumberStrobe : out STD_LOGIC;
FSM_Error : out STD_LOGIC
);
end entity Dummy_DUT;
architecture RTL of Dummy_DUT is
-----------------------------------------------------------------------------
signal Registered_Trigger , Registered_RST : std_logic; -- trigger and reset signals after being registered to suppress meta-stability.
signal TriggerShiftRegister : STD_LOGIC_VECTOR (15 downto 0); --! register
--to accept
--incoming
--trigger number
type state_type is (IDLE , WAIT_FOR_TRIGGER_LOW , CLOCKING , OUTPUT_TRIGGER_NUMBER);
signal state : state_type := IDLE;
signal next_state : state_type := IDLE;
signal TriggerBitCounter : unsigned(4 downto 0) := ( others => '0'); --! stores bit being clocked
--in from TLU.
signal InternalDUTClk : std_logic := '0'; -- ! "can't read an output" bodge
constant DUTClockDivider : unsigned(3 downto 0) := to_unsigned(14,4);
constant TriggerBitCounterLimit : unsigned(4 downto 0) := to_unsigned(16,5);
signal DUTClockCounter : unsigned(4 downto 0) := ( others => '0');
begin
trigger_register: entity work.delay
generic map (
length => 2)
port map (
clock => clk,
input => Trigger,
output => Registered_Trigger);
reset_register: entity work.delay
generic map (
length => 2)
port map (
clock => clk,
input => RST,
output => Registered_RST);
busy_control: process (clk , state)
begin -- process busy_control
if rising_edge(clk) then
if state = IDLE then
busy <= '0';
else
busy <= '1';
end if;
end if;
end process busy_control;
clock_control: process (clk , state , TriggerBitCounter )
begin -- process busy_control
if rising_edge(clk) then
if state = CLOCKING then
if (InternalDUTClk = '0') and (DUTClockCounter = DUTClockDivider) then
TriggerBitCounter <= TriggerBitCounter +1;
else
TriggerBitCounter <= TriggerBitCounter;
end if;
else
TriggerBitCounter <= ( others => '0');
end if;
end if;
end process clock_control;
InternalDUTClk_control: process (clk , state , InternalDUTClk)
begin -- process busy_control
if rising_edge(clk) then
if state = CLOCKING then
if DUTClockCounter = DUTClockDivider then
InternalDUTClk <= not InternalDUTClk ;
DUTClockCounter <= ( others => '0');
else
DUTClockCounter <= DUTClockCounter + 1;
end if;
else
InternalDUTClk <= '0';
DUTClockCounter <= ( others => '0');
end if;
end if;
end process InternalDUTClk_control;
shift_register_control: process (clk , state , TriggerShiftRegister)
begin -- process shift_register_control
if rising_edge(clk) then
if state = IDLE then
TriggerShiftRegister <= ( others => '0');
elsif state = CLOCKING then
if (InternalDUTClk = '1') and (DUTClockCounter=to_unsigned(1,4 )) then
-- if (InternalDUTClk = '1') and (DUTClockCounter=to_unsigned(1,DUTClockCounter'length )) then
TriggerShiftRegister <= trigger & TriggerShiftRegister( 15 downto 1) ;
-- TriggerShiftRegister <= trigger & TriggerShiftRegister( TriggerShiftRegister'high downto 1) ;
else
TriggerShiftRegister <= TriggerShiftRegister;
end if;
end if;
end if;
end process shift_register_control;
strobe_control: process (clk , state )
begin -- process stobe_control
if rising_edge(clk) then
if state = OUTPUT_TRIGGER_NUMBER then
TriggerNumber <= TriggerShiftRegister;
TriggerNumberStrobe <= '1';
else
TriggerNumberStrobe <= '0';
end if;
end if;
end process strobe_control;
--! @brief controls the next state in the state machine
-- type : combinational
-- inputs : pattern_we, mask_we , beam_state_counter
-- outputs: state , beam_state_counter
state_logic: process (state, TriggerBitCounter , registered_trigger ,InternalDUTClk )
begin -- process state_logic
case state is
when IDLE =>
if ( registered_trigger = '1') then
next_state <= WAIT_FOR_TRIGGER_LOW;
else
next_state <= IDLE;
end if;
when WAIT_FOR_TRIGGER_LOW =>
if ( registered_trigger = '0' ) then
next_state <= CLOCKING;
else
next_state <= WAIT_FOR_TRIGGER_LOW;
end if;
when CLOCKING =>
if (( TriggerBitCounter = TriggerBitCounterLimit ) and ( InternalDUTClk = '0')) then
next_state <= OUTPUT_TRIGGER_NUMBER;
else
next_state <= CLOCKING;
end if;
when OUTPUT_TRIGGER_NUMBER =>
next_state <= IDLE;
when others =>
next_state <= IDLE;
end case;
end process state_logic;
--! @brief Register that holds the current state of the FSM
-- type : combinational
-- inputs : clk , next_state
-- outputs: state
state_register: process (clk )
begin -- process state_register
if rising_edge(clk) then
if (registered_rst = '1') then
state <= IDLE;
else
state <= next_state;
end if;
end if;
end process state_register;
DUTClk <= InternalDUTClk;
fsm_error <= '0'; -- hardware to zero.
end RTL;
firmware/simulation_src/Trigger_Number_Error_Checker.vhd 0 → 100755
View file @ 6f451125
----------------------------------------------------------------------------------
--! @file
--
-- Company: University of Bristol
-- Engineer: David Cussans
--
-- Create Date: 11/11/09
-- Design Name:
-- Module Name: Trigger_Number_Error_Checker - RTL
-- Project Name:
-- Target Devices:
-- Tool versions:
--! @brief Checks the trigger numbers being returned by the dummy dut.
--
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- constant definitions.
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Trigger_Number_Error_Checker is
Port (
CLK : in STD_LOGIC; --! this is the USB clock.
RST : in STD_LOGIC; --! Synchronous with clock
TriggerNumber : in STD_LOGIC_VECTOR(15 downto 0); --! should
--incremeent from
--0
TriggerNumberStrobe : in STD_LOGIC; --! Active high
TriggerCounter : out STD_LOGIC_VECTOR(15 downto 0); --!internal counter
ErrorFlag : out STD_LOGIC --! goes high if internal number
--doesn't match
);
end entity Trigger_Number_Error_Checker;
architecture RTL of Trigger_Number_Error_Checker is
signal InternalTriggerCounter : std_logic_vector(TriggerNumber'high downto 0); -- internal
-- store
-- to compare with output from TLU
signal InternalErrorFlag : std_logic := '0'; -- VHDL can't read an out-port bodge
signal Registered_TriggerNumberStrobe0 ,Registered_TriggerNumberStrobe1 ,Registered_TriggerNumberStrobe2 : std_logic := '0';
-- bodge 'cos I don't understand RTL...
signal Registered_TriggerNumber : std_logic_vector(15 downto 0);
begin
delay_triggerstrobe: process (clk , TriggerNumberStrobe ,Registered_TriggerNumberStrobe0 ,Registered_TriggerNumberStrobe1 , Registered_TriggerNumberStrobe2 )
begin -- process delay_triggerstrobe
if rising_edge(clk) then
Registered_TriggerNumberStrobe0 <= TriggerNumberStrobe;
Registered_TriggerNumberStrobe1 <= Registered_TriggerNumberStrobe0;
Registered_TriggerNumberStrobe2 <= Registered_TriggerNumberStrobe1;
end if;
end process delay_triggerstrobe;
register_trigger_number: process (clk , TriggerNumber )
begin -- process register_trigger_number
if rising_edge(clk) then
Registered_TriggerNumber <= TriggerNumber;
end if;
end process register_trigger_number;
check_error: process (clk ,Registered_TriggerNumberStrobe0 , Registered_TriggerNumber , InternalTriggerCounter)
begin -- process busy_control
if (rising_edge(clk) and (Registered_TriggerNumberStrobe0 = '1')) then
if ( unsigned(Registered_TriggerNumber) /= (unsigned(InternalTriggerCounter)+2) )then --
-- temporary fix to check that checker is working.
-- if ( unsigned(Registered_TriggerNumber) /= (unsigned(InternalTriggerCounter)+1) )then
InternalErrorFlag <= '1';
else
InternalErrorFlag <= '0';
end if;
end if;
end process check_error;
output_error: process (clk , Registered_TriggerNumberStrobe1 , InternalErrorFlag)
begin -- process output_error
if (rising_edge(clk)and (Registered_TriggerNumberStrobe1 = '1')) then
ErrorFlag <= InternalErrorFlag;
end if;
end process output_error;
register_trigger_number: process (clk , Registered_TriggerNumberStrobe2 , TriggerNumber )
begin -- process output_error
if (rising_edge(clk)and (Registered_TriggerNumberStrobe2 = '1')) then
InternalTriggerCounter <= TriggerNumber;
end if;
end process output_error;
TriggerCounter <= InternalTriggerCounter;
end RTL;
firmware/simulation_src/delay.vhd 0 → 100644
View file @ 6f451125
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity delay is
generic (
length : integer := 1); -- number of clock cycles to delay signal
port (
clock : in std_logic; -- rising edge active
input : in std_logic;
output : out std_logic);
end delay;
architecture rtl of delay is
signal internal_signal : std_logic_vector( length downto 0); -- signals along the pipe-line
begin -- rtl
internal_signal(0) <= input;
pipeline: for N in 1 to length generate
pipelinestage: entity work.dtype
port map (
q => internal_signal(N),
c => clock ,
clr => '0' ,
d => internal_signal(N-1),
ce => '1' ,
pre => '0'
);
end generate pipeline;
output <= internal_signal(length);
end rtl;
firmware/simulation_src/dtype.vhd 0 → 100644
View file @ 6f451125
----- CELL dtype -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- use IEEE.VITAL_Timing.all;
entity dtype is
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic;
CE : in std_logic;
PRE : in std_logic
);
end dtype;
architecture dtype_V of dtype is
begin
VITALBehavior : process(C, CLR, PRE)
begin
if (CLR = '1') then
Q <= '0';
elsif (PRE = '1') then
Q <= '1';
elsif (rising_edge(C) and CE='1') then
Q <= D ;
end if;
end process;
end dtype_V;
firmware/simulation_src/fmc-tlu_v0-1_eudet_test-bench.vhd 0 → 100644
View file @ 6f451125
--=============================================================================
--! @file fmc-tlu_v0-1_test-bench.vhd
--=============================================================================
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
--! @brief Test-bench for FMC format mini-TLU for AIDA with EUDET style DUTs
--
--! @details
--
--! @author David Cussans, 31/07/12
--! @date 11:49:20 02/21/2014
--------------------------------------------------------------------------------
ENTITY fmctlu_v0_1_eudet_testbench IS
END fmctlu_v0_1_eudet_testbench;
ARCHITECTURE behavior OF fmctlu_v0_1_eudet_testbench IS
constant c_NUM_DUTS : positive := 3;
--Inputs
-- Busy signals from DUT. Complementary pair
signal busy_n_i : std_logic_vector(c_NUM_DUTS-1 downto 0) := (others => '1');
signal busy_p_i : std_logic_vector(c_NUM_DUTS-1 downto 0) := (others => '0');
signal cfd_discr_n_i : std_logic_vector(3 downto 0) := (others => '1');
signal cfd_discr_p_i : std_logic_vector(3 downto 0) := (others => '0');
signal dip_switch_i : std_logic_vector(3 downto 0) := "0010" ; -- Set IP address to 192.168.200.32
signal dut_clk_n_i : std_logic_vector(c_NUM_DUTS-1 downto 0) := (others => '1');
signal dut_clk_p_i : std_logic_vector(c_NUM_DUTS-1 downto 0) := (others => '0');
signal gmii_rx_clk_i : std_logic := '0';
signal gmii_rx_dv_i : std_logic := '0';
signal gmii_rx_er_i : std_logic := '0';
signal gmii_rxd_i : std_logic_vector(7 downto 0) := (others => '0');
signal sysclk_n_i : std_logic := '0';
signal sysclk_p_i : std_logic := '0';
signal threshold_discr_n_i : std_logic_vector(3 downto 0) := (others => '1');
signal threshold_discr_p_i : std_logic_vector(3 downto 0) := (others => '0');
signal s_threshold_discr : std_logic_vector(3 downto 0) := (others => '0');
--BiDirs
signal extclk_n_b : std_logic;
signal extclk_p_b : std_logic;
signal i2c_scl_b : std_logic;
signal i2c_sda_b : std_logic;
--Outputs
signal gmii_gtx_clk_o : std_logic;
signal gmii_tx_en_o : std_logic;
signal gmii_tx_er_o : std_logic;
signal gmii_txd_o : std_logic_vector(7 downto 0);
signal gpio_hdr : std_logic_vector(3 downto 0);
signal leds_o : std_logic_vector(3 downto 0);
signal phy_rstb_o : std_logic;
signal reset_or_clk_n_o : std_logic_vector(c_NUM_DUTS-1 downto 0);
signal reset_or_clk_p_o : std_logic_vector(c_NUM_DUTS-1 downto 0);
signal triggers_n_o : std_logic_vector(c_NUM_DUTS-1 downto 0);
signal triggers_p_o : std_logic_vector(c_NUM_DUTS-1 downto 0);
signal T0_p_i,TPix_Shutter_n_i : std_logic := '0';
signal T0_n_i,TPix_Shutter_p_i : std_logic := '1';
signal s_T0 : std_logic := '0'; -- --! Signal to reset timestamp etc.
constant c_T0_delay : time := 10 us; -- --! Delay before T0 is set high
constant c_T0_width : time := 400 ns; -- --! Width of T0 high.
-- 200MHz on-board crystal oscillator
signal sysclock : std_logic := '0';
constant sysclock_period : time := 5 ns;
-- 40MHz from external clock source.
signal extclk : std_logic := '0';
constant extclk_period : time := 25 ns;
-- Dummy TLU
constant c_COUNTER_WIDTH : positive := 16;
type t_register_array is array(natural range <>) of std_logic_vector ( c_COUNTER_WIDTH-1 downto 0) ; -- --! Array of arrays for output register...
signal dummy_dut_trigger_number : t_register_array(c_NUM_DUTS-1 downto 0) := ( others => ( others => '0')); -- --! Output registers.
signal dummy_dut_trigger_number_strobe : std_logic_vector(c_NUM_DUTS-1 downto 0) := ( others => '0');
BEGIN
-- Instantiate AIDA TLU
uut: entity work.top_extphy
generic map (
g_NUM_DUTS => c_NUM_DUTS,
g_BUILD_SIMULATED_MAC => 1
)
PORT MAP (
busy_n_i => busy_n_i,
busy_p_i => busy_p_i,
cfd_discr_n_i => cfd_discr_n_i,
cfd_discr_p_i => cfd_discr_p_i,
dip_switch_i => dip_switch_i,
dut_clk_n_o => dut_clk_n_i,
dut_clk_p_o => dut_clk_p_i,
gmii_rx_clk_i => gmii_rx_clk_i,
gmii_rx_dv_i => gmii_rx_dv_i,
gmii_rx_er_i => gmii_rx_er_i,
gmii_rxd_i => gmii_rxd_i,
sysclk_n_i => sysclk_n_i,
sysclk_p_i => sysclk_p_i,
threshold_discr_n_i => threshold_discr_n_i,
threshold_discr_p_i => threshold_discr_p_i,
gmii_gtx_clk_o => gmii_gtx_clk_o,
gmii_tx_en_o => gmii_tx_en_o,
gmii_tx_er_o => gmii_tx_er_o,
gmii_txd_o => gmii_txd_o,
gpio_hdr => gpio_hdr,
leds_o => leds_o,
phy_rstb_o => phy_rstb_o,
reset_or_clk_n_o => reset_or_clk_n_o,
reset_or_clk_p_o => reset_or_clk_p_o,
triggers_n_o => triggers_n_o,
triggers_p_o => triggers_p_o,
extclk_n_b => extclk_n_b,
extclk_p_b => extclk_p_b,
i2c_scl_b => i2c_scl_b,
i2c_sda_b => i2c_sda_b
);
gen_duts: for dut in 0 to c_NUM_DUTS-1 generate
cmp_dummy_dut: entity work.Dummy_DUT
Port map (
CLK => sysclock,
RST => '0',
Trigger => triggers_p_o(dut),
Busy => busy_p_i(dut),
DUTClk => dut_clk_p_i(dut),
TriggerNumber => dummy_dut_trigger_number(dut),
TriggerNumberStrobe => dummy_dut_trigger_number_strobe(dut),
FSM_Error => open
);
busy_n_i(dut) <= not busy_p_i(dut);
dut_clk_n_i(dut) <= not dut_clk_p_i(dut);
end generate gen_duts;
-- Clock process definitions
sysclock_process :process
begin
sysclock <= '0';
wait for sysclock_period/2;
sysclock <= '1';
wait for sysclock_period/2;
end process;
sysclk_n_i <= not sysclock;
sysclk_p_i <= sysclock;
extclock_process :process
begin
extclk <= '0';
wait for extclk_period/2;
extclk <= '1';
wait for extclk_period/2;
end process;
extclk_n_b <= not extclk;
extclk_p_b <= extclk;
-- purpose: Pulses T0
-- type : combinational
-- inputs :
-- outputs: s_T0
p_T0_pulse: process is
begin -- process p_T0_pulse
s_T0 <= '0';
wait for c_T0_delay;
s_T0 <= '1';
wait for c_T0_width;
s_T0 <= '0';
wait;
end process p_T0_pulse;
T0_p_i <= s_T0;
T0_n_i <= not s_T0;
-- Generate pulses
cmp_pulseGen: entity work.pmtPulseGenerator
generic map (
g_NUM_CHANNELS => 4)
port map (
pulses_o => s_threshold_discr,
numPulses_i => 10,
initialDelay_i => 20 us,
averagePulseInterval_i => 10 us,
averagePulseWidth_i => 100 ns,
pulseJitter_i => 2 ns,
sysclock_i => sysclock,
simulationDone_o => open);
threshold_discr_p_i <= s_threshold_discr;
threshold_discr_n_i <= not s_threshold_discr;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for sysclock_period*10;
-- insert stimulus here
wait;
end process;
END;
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