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AIDA-2020 TLU
Commit cbe603f8 authored by David Cussans's avatar David Cussans
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Added EUDET style DUT interface 

Write to "DUTInterfaceMode" register to choose between EUDET (0) and AIDA (1) modes

Will result in pseudo-LVDS for clock lines ( Boo.... ) put termination resistors in bodge boards.

Executes in simulation, produces internal triggers when test_aida_tlu_internal_triggers_v2.py run.

Edited setup_project.tcl so that new files are inserted into ISE project ( NOT TESTED)

Edited add_files.tcl so that new files are are inserted into Modelsim/Questa project ( NOT TESTED)

Removed unused trigger_counter_o port from EventFormatter. Connected up DUTInterface to TriggerLogic trigger_counter instead.
parent 913f7688
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firmware/config/ise14/sp605/setup_project.tcl
View file @ cbe603f8
......@@ -108,6 +108,7 @@ puts "Adding TLU Files "
xfile add fmc-mtlu/firmware/hdl/common/dualSERDES_1to4_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/DUTInterfaces_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/DUTInterfaces_EUDET_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/single_pulse_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/DUTInterfaces_AIDA_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/eventBuffer_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/eventFormatter_rtl.vhd
......
firmware/hdl/common/DUTInterface_EUDET_rtl.vhd
View file @ cbe603f8
......@@ -20,7 +20,6 @@ entity DUTInterface_EUDET is
rst_i : in std_logic; --! asynchronous reset. Active high
busy_o : out std_logic; --! low if FSM is in IDLE state, high otherwise
fsm_state_value_o : out std_logic_vector(3 downto 0); --! detailed status of FSM.
handshake_mode_i : in std_logic; --! if high uses TRIG/BUSY handshake, if low only outputs a trigger
trigger_i : in std_logic; --! Trigger retimed onto system clock.active high.
trigger_counter_i : in std_logic_vector(g_TRIGGER_DATA_WIDTH-1 downto 0); --! event number
system_clk_i : in std_logic; --! rising edge active clock from TLU
......@@ -38,14 +37,6 @@ end DUTInterface_EUDET;
architecture rtl of DUTInterface_EUDET is
component single_pulse is
port (
level : in std_logic;
clk : in std_logic;
pulse : out std_logic
);
end component;
-----------------------------------------------------------------------------
-- Declarations for state machine
type state_type is (IDLE , WAIT_FOR_BUSY_HIGH , TRIGGER_DEGLITCH_DELAY1 ,
......@@ -75,6 +66,8 @@ architecture rtl of DUTInterface_EUDET is
begin -- rtl
dut_shutter_o <= shutter_to_dut_i ; -- for now just pass through.
-- purpose: suppress meta-stability by registering input signals.
-- type : combinational
-- inputs : dut_busy_r1 , dut_busy_r2 , dut_clk_r1 , dut_clk_r2
......@@ -93,7 +86,7 @@ begin -- rtl
rising_edge_pulse: single_pulse
rising_edge_pulse: entity work.single_pulse
port map (
level => dut_clk_i,
clk => system_clk_i,
......@@ -150,17 +143,14 @@ end process;
-- purpose: Determine the next state
-- type : combinational
-- inputs : state,Dut_Busy_r2, trigger_i
state_logic: process (state, trigger_i , handshake_mode_i , enable_dut_veto_i , dut_clk_r2, dut_busy_r2 )
-- state_logic: process (state, trigger_i , handshake_mode_i , enable_dut_veto_i , dut_clk_r2, dut_busy_r2 )
state_logic: process (state, trigger_i , enable_dut_veto_i , dut_clk_r2, dut_busy_r2 )
begin -- process state_logic
case state is
when IDLE =>
if ( trigger_i = '1') then -- respond to trigger going high
if ( handshake_mode_i = '1' ) then -- depending of state of control flag :
next_state <= WAIT_FOR_BUSY_HIGH; -- wait for DUT to respond to busy
else
next_state <= TRIGGER_DEGLITCH_DELAY1; -- go straight to deglitch-delay.
end if;
next_state <= WAIT_FOR_BUSY_HIGH; -- wait for DUT to respond to busy
elsif ( (dut_clk_r2 = '1') and (enable_dut_veto_i = '1') ) then -- If DUT asserts DUT_CLK_I then veto triggers
next_state <= DUT_INITIATED_VETO;
......@@ -183,13 +173,8 @@ end process;
-- delay for two clock cycles.
when TRIGGER_DEGLITCH_DELAY2 =>
-- if handshake-mode=1 then wait until BUSY drops before moving to IDLE
-- else if handshake-mode=0 then go straight to IDLE ignoring BUSY
if (handshake_mode_i = '1') then
next_state <= WAIT_FOR_BUSY_LOW;
else
next_state <= IDLE;
end if;
next_state <= WAIT_FOR_BUSY_LOW;
when WAIT_FOR_BUSY_LOW =>
......
firmware/hdl/common/DUTInterfaces_rtl.vhd
View file @ cbe603f8
This diff is collapsed.
firmware/hdl/common/eventFormatter_rtl.vhd
View file @ cbe603f8
......@@ -92,8 +92,7 @@ ENTITY eventFormatter IS
data_strobe_o : OUT std_logic; --! goes high when data ready to load into event buffer
event_data_o : OUT std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0);
reset_timestamp_i : IN std_logic; --! Taking high causes timestamp to be reset. Combined with internal timestmap reset and written to reset_timestamp_o
reset_timestamp_o : OUT std_logic; --! Goes high for one clock cycle of clk_4x_logic when timestamp reset
trigger_count_o : OUT std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0)
reset_timestamp_o : OUT std_logic --! Goes high for one clock cycle of clk_4x_logic when timestamp reset
);
-- Declarations
......
firmware/hdl/common/single_pulse_rtl.vhd 0 → 100644
View file @ cbe603f8
-------------------------------------------------------------------------------
--! @file
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
-------------------------------------------------------------------------------
--
-- VHDL for producing a single clock low-high-low pulse on the rising edge
-- of input signal (LEVEL)
--
-- David Cussans, Ocala, April 2005
--
-- LEVEL (input) - when LEVEL goes high, PULSE goes high for one clock cycle
-- - on next rising edge of CLK
-- CLK (input) - rising edge active
-- PULSE - changes on rising edge of clk
--
--! @brief gives a single cycle pulse ( high active) following the rising edge of LEVEL
entity single_pulse is
port (
level : in std_logic; --! When LEVEL goes high, PULSE goes high for one clock cycle
clk : in std_logic; --! rising edge active
pulse : out std_logic --! Pulses high for one cycle
);
end entity single_pulse;
architecture rtl of single_pulse is
signal x, v : std_logic;
begin -- architecture rtl
ff1: process (clk , level) is
begin -- process ff1
if rising_edge(clk) then
x <= level;
end if;
end process ff1;
ff2: process (clk , x) is
begin -- process ff2
if rising_edge(clk) then
v <= not x;
end if;
end process ff2;
pulse <= ( x and v );
end architecture rtl;
firmware/hdl/miniTLU/top_extphy_struct.vhd
View file @ cbe603f8
This diff is collapsed.
firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/symbol.sb
View file @ cbe603f8
......@@ -78,7 +78,7 @@ decl (Decl
n "leds_o"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 21
o 19
suid 2,0
)
)
......@@ -90,7 +90,7 @@ m 1
decl (Decl
n "gmii_gtx_clk_o"
t "std_logic"
o 16
o 14
suid 3,0
)
)
......@@ -102,7 +102,7 @@ m 1
decl (Decl
n "gmii_tx_en_o"
t "std_logic"
o 17
o 15
suid 4,0
)
)
......@@ -114,7 +114,7 @@ m 1
decl (Decl
n "gmii_tx_er_o"
t "std_logic"
o 18
o 16
suid 5,0
)
)
......@@ -171,7 +171,7 @@ m 1
decl (Decl
n "phy_rstb_o"
t "std_logic"
o 22
o 20
suid 10,0
)
)
......@@ -184,7 +184,7 @@ decl (Decl
n "gmii_txd_o"
t "std_logic_vector"
b "(7 DOWNTO 0)"
o 19
o 17
suid 11,0
)
)
......@@ -198,7 +198,7 @@ n "triggers_p_o"
t "std_logic_vector"
b "(g_NUM_DUTS-1 DOWNTO 0)"
eolc "--! Trigger lines to DUT"
o 28
o 26
suid 12,0
)
)
......@@ -225,7 +225,7 @@ n "reset_or_clk_p_o"
t "std_logic_vector"
b "(g_NUM_DUTS-1 DOWNTO 0)"
eolc "--! T0 synchronization signal"
o 24
o 22
suid 14,0
)
)
......@@ -335,7 +335,7 @@ decl (Decl
n "reset_or_clk_n_o"
t "std_logic_vector"
b "(g_NUM_DUTS-1 DOWNTO 0)"
o 23
o 21
suid 30,0
)
)
......@@ -348,7 +348,7 @@ decl (Decl
n "triggers_n_o"
t "std_logic_vector"
b "(g_NUM_DUTS-1 DOWNTO 0)"
o 27
o 25
suid 31,0
)
)
......@@ -399,7 +399,7 @@ decl (Decl
n "gpio_hdr"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 20
o 18
suid 36,0
)
)
......@@ -408,13 +408,13 @@ uid 1989,0
*42 (LogPort
port (LogicalPort
lang 11
m 1
m 2
decl (Decl
n "dut_clk_p_o"
t "std_logic_vector"
b "(g_NUM_DUTS-1 DOWNTO 0)"
eolc "--! Clock to DUT (P)"
o 15
o 28
suid 37,0
)
)
......@@ -423,12 +423,12 @@ uid 2089,0
*43 (LogPort
port (LogicalPort
lang 11
m 1
m 2
decl (Decl
n "dut_clk_n_o"
t "std_logic_vector"
b "(g_NUM_DUTS-1 DOWNTO 0)"
o 14
o 27
suid 38,0
)
)
......@@ -444,7 +444,7 @@ t "std_logic_vector"
b "(g_NUM_DUTS-1 DOWNTO 1)"
eolc "--! Shutter output"
posAdd 0
o 25
o 23
suid 47,0
)
)
......@@ -461,7 +461,7 @@ b "(g_NUM_DUTS-1 DOWNTO 1)"
eolc "--! Shutter output"
preAdd 0
posAdd 0
o 26
o 24
suid 48,0
)
)
......@@ -1091,19 +1091,19 @@ value "/users/phdgc/IPBus_stuff/fmc_tlu_test_modify_tpix3_nov14_aug15/fmc-mtlu/f
)
(vvPair
variable "date"
value "08/26/15"
value "09/03/15"
)
(vvPair
variable "day"
value "Wed"
value "Thu"
)
(vvPair
variable "day_long"
value "Wednesday"
value "Thursday"
)
(vvPair
variable "dd"
value "26"
value "03"
)
(vvPair
variable "entity_name"
......@@ -1131,7 +1131,7 @@ value "phdgc"
)
(vvPair
variable "graphical_source_date"
value "08/26/15"
value "09/03/15"
)
(vvPair
variable "graphical_source_group"
......@@ -1139,7 +1139,7 @@ value "users"
)
(vvPair
variable "graphical_source_time"
value "16:01:24"
value "11:30:28"
)
(vvPair
variable "group"
......@@ -1179,7 +1179,7 @@ value "$HDS_PROJECT_DIR/fmc_mTLU_lib/ise"
)
(vvPair
variable "mm"
value "08"
value "09"
)
(vvPair
variable "module_name"
......@@ -1187,11 +1187,11 @@ value "top_extphy"
)
(vvPair
variable "month"
value "Aug"
value "Sep"
)
(vvPair
variable "month_long"
value "August"
value "September"
)
(vvPair
variable "p"
......@@ -1259,7 +1259,7 @@ value "symbol"
)
(vvPair
variable "time"
value "16:01:24"
value "11:30:28"
)
(vvPair
variable "unit"
......@@ -1370,7 +1370,7 @@ uid 155,0
va (VaSet
font "courier,8,0"
)
xt "44000,19800,74500,20700"
xt "44000,18000,74500,18900"
st "leds_o : OUT std_logic_vector (3 DOWNTO 0) ;"
)
thePort (LogicalPort
......@@ -1380,7 +1380,7 @@ decl (Decl
n "leds_o"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 21
o 19
suid 2,0
)
)
......@@ -1418,7 +1418,7 @@ uid 160,0
va (VaSet
font "courier,8,0"
)
xt "44000,15300,65000,16200"
xt "44000,13500,65000,14400"
st "gmii_gtx_clk_o : OUT std_logic ;"
)
thePort (LogicalPort
......@@ -1426,7 +1426,7 @@ m 1
decl (Decl
n "gmii_gtx_clk_o"
t "std_logic"
o 16
o 14
suid 3,0
)
)
......@@ -1464,7 +1464,7 @@ uid 165,0
va (VaSet
font "courier,8,0"
)
xt "44000,16200,65000,17100"
xt "44000,14400,65000,15300"
st "gmii_tx_en_o : OUT std_logic ;"
)
thePort (LogicalPort
......@@ -1472,7 +1472,7 @@ m 1
decl (Decl
n "gmii_tx_en_o"
t "std_logic"
o 17
o 15
suid 4,0
)
)
......@@ -1510,7 +1510,7 @@ uid 170,0
va (VaSet
font "courier,8,0"
)
xt "44000,17100,65000,18000"
xt "44000,15300,65000,16200"
st "gmii_tx_er_o : OUT std_logic ;"
)
thePort (LogicalPort
......@@ -1518,7 +1518,7 @@ m 1
decl (Decl
n "gmii_tx_er_o"
t "std_logic"
o 18
o 16
suid 5,0
)
)
......@@ -1733,7 +1733,7 @@ uid 195,0
va (VaSet
font "courier,8,0"
)
xt "44000,20700,65000,21600"
xt "44000,18900,65000,19800"
st "phy_rstb_o : OUT std_logic ;"
)
thePort (LogicalPort
......@@ -1741,7 +1741,7 @@ m 1
decl (Decl
n "phy_rstb_o"
t "std_logic"
o 22
o 20
suid 10,0
)
)
......@@ -1779,7 +1779,7 @@ uid 200,0
va (VaSet
font "courier,8,0"
)
xt "44000,18000,74500,18900"
xt "44000,16200,74500,17100"
st "gmii_txd_o : OUT std_logic_vector (7 DOWNTO 0) ;"
)
thePort (LogicalPort
......@@ -1788,7 +1788,7 @@ decl (Decl
n "gmii_txd_o"
t "std_logic_vector"
b "(7 DOWNTO 0)"
o 19
o 17
suid 11,0
)
)
......@@ -1826,7 +1826,7 @@ uid 205,0
va (VaSet
font "courier,8,0"
)
xt "44000,26100,92500,27000"
xt "44000,24300,92500,25200"
st "triggers_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0) ; --! Trigger lines to DUT"
)
thePort (LogicalPort
......@@ -1836,7 +1836,7 @@ n "triggers_p_o"
t "std_logic_vector"
b "(g_NUM_DUTS-1 DOWNTO 0)"
eolc "--! Trigger lines to DUT"
o 28
o 26
suid 12,0
)
)
......@@ -1920,7 +1920,7 @@ uid 215,0
va (VaSet
font "courier,8,0"
)
xt "44000,22500,95000,23400"
xt "44000,20700,95000,21600"
st "reset_or_clk_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0) ; --! T0 synchronization signal"
)
thePort (LogicalPort
......@@ -1930,7 +1930,7 @@ n "reset_or_clk_p_o"
t "std_logic_vector"
b "(g_NUM_DUTS-1 DOWNTO 0)"
eolc "--! T0 synchronization signal"
o 24
o 22
suid 14,0
)
)
......@@ -2331,7 +2331,7 @@ uid 1792,0
va (VaSet
font "courier,8,0"
)
xt "44000,21600,80000,22500"
xt "44000,19800,80000,20700"
st "reset_or_clk_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0) ;"
)
thePort (LogicalPort
......@@ -2340,7 +2340,7 @@ decl (Decl
n "reset_or_clk_n_o"
t "std_logic_vector"
b "(g_NUM_DUTS-1 DOWNTO 0)"
o 23
o 21
suid 30,0
)
)
......@@ -2378,7 +2378,7 @@ uid 1797,0
va (VaSet
font "courier,8,0"
)
xt "44000,25200,80000,26100"
xt "44000,23400,80000,24300"
st "triggers_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0) ;"
)
thePort (LogicalPort
......@@ -2387,7 +2387,7 @@ decl (Decl
n "triggers_n_o"
t "std_logic_vector"
b "(g_NUM_DUTS-1 DOWNTO 0)"
o 27
o 25
suid 31,0
)
)
......@@ -2563,7 +2563,7 @@ uid 1995,0
va (VaSet
font "courier,8,0"
)
xt "44000,18900,74500,19800"
xt "44000,17100,74500,18000"
st "gpio_hdr : OUT std_logic_vector (3 DOWNTO 0) ;"
)
thePort (LogicalPort
......@@ -2573,7 +2573,7 @@ decl (Decl
n "gpio_hdr"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 20
o 18
suid 36,0
)
)
......@@ -2581,8 +2581,8 @@ suid 36,0
*160 (CptPort
uid 2092,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2093,0
shape (Diamond
uid 2749,0
ro 90
va (VaSet
vasetType 1
......@@ -2611,18 +2611,18 @@ uid 2096,0
va (VaSet
font "courier,8,0"
)
xt "44000,14400,90500,15300"
st "dut_clk_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0) ; --! Clock to DUT (P)"
xt "44000,26100,90500,27000"
st "dut_clk_p_o : INOUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0) ; --! Clock to DUT (P)"
)
thePort (LogicalPort
lang 11
m 1
m 2
decl (Decl
n "dut_clk_p_o"
t "std_logic_vector"
b "(g_NUM_DUTS-1 DOWNTO 0)"
eolc "--! Clock to DUT (P)"
o 15
o 28
suid 37,0
)
)
......@@ -2630,8 +2630,8 @@ suid 37,0
*161 (CptPort
uid 2097,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2098,0
shape (Diamond
uid 2750,0
ro 90
va (VaSet
vasetType 1
......@@ -2660,17 +2660,17 @@ uid 2101,0
va (VaSet
font "courier,8,0"
)
xt "44000,13500,80000,14400"
st "dut_clk_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0) ;"
xt "44000,25200,80000,26100"
st "dut_clk_n_o : INOUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0) ;"
)
thePort (LogicalPort
lang 11
m 1
m 2
decl (Decl
n "dut_clk_n_o"
t "std_logic_vector"
b "(g_NUM_DUTS-1 DOWNTO 0)"
o 14
o 27
suid 38,0
)
)
......@@ -2708,7 +2708,7 @@ uid 2557,0
va (VaSet
font "courier,8,0"
)
xt "44000,23400,89500,24300"
xt "44000,21600,89500,22500"
st "shutter_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 1) ; --! Shutter output"
)
thePort (LogicalPort
......@@ -2720,7 +2720,7 @@ t "std_logic_vector"
b "(g_NUM_DUTS-1 DOWNTO 1)"
eolc "--! Shutter output"
posAdd 0
o 25
o 23
suid 47,0
)
)
......@@ -2758,7 +2758,7 @@ uid 2562,0
va (VaSet
font "courier,8,0"
)
xt "44000,24300,89500,25200"
xt "44000,22500,89500,23400"
st "shutter_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 1) ; --! Shutter output"
)
thePort (LogicalPort
......@@ -2771,7 +2771,7 @@ b "(g_NUM_DUTS-1 DOWNTO 1)"
eolc "--! Shutter output"
preAdd 0
posAdd 0
o 26
o 24
suid 48,0
)
)
......@@ -3546,7 +3546,7 @@ xt "42000,0,42000,0"
tm "SyDeclarativeTextMgr"
)
)
lastUid 2702,0
lastUid 2842,0
okToSyncOnLoad 1
OkToSyncGenericsOnLoad 1
activeModelName "Symbol:CDM"
......
firmware/scripts/aida_mini_tlu_addr_map.txt
View file @ cbe603f8
......@@ -6,9 +6,13 @@ FirmwareId 0x00000000 0xffffffff 1 0
DUTMaskW 0x00000020 0xffffffff 0 1
IgnoreDUTBusyW 0x00000021 0xffffffff 0 1
IgnoreShutterVetoW 0x00000022 0xffffffff 0 1
DUTInterfaceModeW 0x00000023 0xffffffff 0 1
DUTInterfaceModeModifierW 0x00000024 0xffffffff 0 1
DUTMaskR 0x00000028 0xffffffff 1 0
IgnoreDUTBusyR 0x00000029 0xffffffff 1 0
IgnoreShutterVetoR 0x0000002A 0xffffffff 1 0
DUTInterfaceModeR 0x0000002B 0xffffffff 1 0
DUTInterfaceModeModifierR 0x0000002C 0xffffffff 1 0
*
* trigger inputs = 0x040
SerdesRstW 0x00000040 0xffffffff 0 1
......@@ -23,15 +27,15 @@ PostVetoTriggersR 0x00000068 0xffffffff 1 0
PreVetoTriggersR 0x00000069 0xffffffff 1 0
InternalTriggerIntervalW 0x00000062 0xffffffff 1 1
InternalTriggerIntervalR 0x0000006A 0xffffffff 1 1
TriggerPatternW 0x00000063 0xffffffff 1 1
TriggerPatternR 0x0000006B 0xffffffff 1 1
TriggerVetoW 0x00000064 0xffffffff 1 1
TriggerVetoR 0x0000006C 0xffffffff 1 1
TriggerPatternW 0x00000063 0xffffffff 0 1
TriggerPatternR 0x0000006B 0xffffffff 1 0
TriggerVetoW 0x00000064 0xffffffff 0 1
TriggerVetoR 0x0000006C 0xffffffff 1 0
ExternalTriggerVetoR 0x0000006D 0xffffffff 1 0
PulseStretchW 0x00000066 0xffffffff 0 1
PulseStretchR 0x0000006E 0xffffffff 0 1
PulseDelayW 0x00000067 0xffffffff 1 1
PulseDelayR 0x0000006F 0xffffffff 1 1
PulseStretchR 0x0000006E 0xffffffff 1 0
PulseDelayW 0x00000067 0xffffffff 0 1
PulseDelayR 0x0000006F 0xffffffff 1 0
*
* event buffer = 0x080
EventFifoData 0x00000080 0xffffffff 1 0
......
firmware/scripts/test_aida_tlu_internal_triggers_v2.py
View file @ cbe603f8
......@@ -50,6 +50,27 @@ board.write("IgnoreShutterVetoW", 1)
IgnoreShutterVetoW = board.read("IgnoreShutterVetoR")
print "DUT ignore shutter veto read back as " , IgnoreShutterVetoW
print "Set DUT into AIDA mode"
board.write("DUTInterfaceModeW", 0xFF)
DUTInterfaceModeR = board.read("DUTInterfaceModeR")
print "DUT mode read back as " , DUTInterfaceModeR
print "Set DUT mode modifier"
board.write("DUTInterfaceModeModifierW", 0xFF)
DUTInterfaceModeModifierR = board.read("DUTInterfaceModeModifierR")
print "DUT mode modifier read back as " , DUTInterfaceModeModifierR
print "Set Pulse stretch"
board.write("PulseStretchW", 0x00)
PulseStretchR = board.read("PulseStretchR")
print "DUT mode modifier read back as " , PulseStretchR
print "Set Pulse delay"
board.write("PulseDelayW", 0x00)
PulseDelayR = board.read("PulseDelayR")
print "DUT mode modifier read back as " , PulseDelayR
print "Turn off trigger veto"
board.write("TriggerVetoW",0)
......
firmware/simulation/scripts/add_files.tcl
View file @ cbe603f8
......@@ -75,6 +75,7 @@ project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/even
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/DUTInterfaces_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/DUTInterface_AIDA_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/DUTInterface_EUDET_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/single_pulse_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/coincidenceLogic_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/stretchPulse_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/synchronizeRegisters_rtl.vhd
......
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