Write to "DUTInterfaceMode" register to choose between EUDET (0) and AIDA (1) modes

Will result in pseudo-LVDS for clock lines ( Boo.... ) put termination resistors in bodge boards.

Executes in simulation, produces internal triggers when test_aida_tlu_internal_triggers_v2.py run.

Edited setup_project.tcl so that new files are inserted into ISE project ( NOT TESTED)

Edited add_files.tcl so that new files are are inserted into Modelsim/Questa project ( NOT TESTED)

Removed unused trigger_counter_o port from EventFormatter. Connected up DUTInterface to TriggerLogic trigger_counter instead.