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AIDA-2020 TLU
Commit 913f7688 authored by David Cussans's avatar David Cussans
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Factorized  hdl/common/DUTInterfaces_rtl.vhd to put hand-shake specific ( EUDET/AIDA ) code into hdl/common/DUTInterface_AIDA_rtl.vhd and hdl/common/DUTInterface_EUDET_rtl.vhd.

N.B. DUTInterface_EUDET_rtl.vhd not yet tested. DUTInterface_AIDA_rtl.vhd runs in simulation.

Improved Doxygen comments in coincidenceLogic_rtl.vhd , hdl/common/synchronizeRegisters_rtl.vhd ,  hdl/common/triggerLogic_rtl.vhd

Increased number of DUTs in simulation_src/fmc-tlu_v0-1_test-bench.vhd from 2 to 3.

Modified
parent e597fd4b
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firmware/config/ise14/sp605/setup_project.tcl
View file @ 913f7688
......@@ -107,6 +107,8 @@ puts "Adding TLU Files "
# Add FMC-MTLU files. First the hand-written VHDL
xfile add fmc-mtlu/firmware/hdl/common/dualSERDES_1to4_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/DUTInterfaces_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/DUTInterfaces_EUDET_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/DUTInterfaces_AIDA_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/eventBuffer_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/eventFormatter_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/i2c_master_rtl.vhd
......@@ -137,15 +139,11 @@ xfile add fmc-mtlu/firmware/hdl/common/coincidenceLogic_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/stretchPulse_rtl.vhd
# Then add the HDL-Designer generated files..
#xfile add fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
#xfile add fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg_body.vhd
#xfile add fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg.vhd
# Move to same directory as other code. Use links to get hdl_designer to work....
# ( Links to files in HDL designer hierarchy )
xfile add fmc-mtlu/firmware/hdl/miniTLU/top_extphy_struct.vhd
xfile add fmc-mtlu/firmware/hdl/common/fmcTLU_pkg_body.vhd
xfile add fmc-mtlu/firmware/hdl/common/fmcTLU_pkg.vhd
# Add files that only ever get built for simulation...
xfile add ipbus/firmware/sim/hdl/clock_sim.vhd
xfile add ipbus/firmware/ethernet/sim/eth_mac_sim.vhd
......
firmware/hdl/common/DUTInterface_AIDA_rtl.vhd 0 → 100644
View file @ 913f7688
--=============================================================================
--! @file DUTInterface_AIDA_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture fmc_mTLU_lib.DUTInterface_AIDA.rtl
--
--------------------------------------------------------------------------------
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--! @brief "AIDA Style" Interface to a Device Under Test (DUT) connector.
--! factorized from original DUTInterfaces_rtl.vhd firmware.
--!
--! @author David Cussans , David.Cussans@bristol.ac.uk
--!
--! @date 1/Sept/2015
--!
--! @version v0.1
--!
--! @details
--
ENTITY DUTInterface_AIDA IS
GENERIC(
g_IPBUS_WIDTH : positive := 32
);
PORT(
clk_4x_logic_i : IN std_logic;
strobe_4x_logic_i : IN std_logic; --! goes high every 4th clock cycle
trigger_counter_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Number of trigger events since last reset
trigger_i : IN std_logic; --! goes high when trigger logic issues a trigger
reset_or_clk_to_dut_i : IN std_logic; --! Synchronization signal. Passed to DUT pins
shutter_to_dut_i : IN std_logic; --! Goes high to indicate data-taking active. DUTs report busy unless ignore_shutter_veto flag is set high
ignore_shutter_veto_i : in std_logic;
ignore_dut_busy_i : in std_logic;
dut_mask_i : in std_logic; --! Set high if DUT is active.
busy_o : OUT std_logic; --! goes high when DUT is busy or vetoed by shutter
-- Signals to/from DUT
dut_busy_i : IN std_logic; --! BUSY input from DUTs
dut_clk_o : OUT std_logic; --! clocks trigger data when in EUDET mode
dut_reset_or_clk_o : OUT std_logic; --! Either reset line or trigger
dut_shutter_o : OUT std_logic; --! Shutter output. Output 0 (RJ45) has no shutter signal
dut_trigger_o : OUT std_logic --! Trigger output
);
-- Declarations
END ENTITY DUTInterface_AIDA ;
--
ARCHITECTURE rtl OF DUTInterface_AIDA IS
signal s_strobe_4x_logic_d1 : std_logic;
signal s_dut_clk : std_logic := '0'; -- Clock to be sent to DUT connectors ( before final register )
signal s_dut_clk_sr : std_logic_vector(2 downto 0) := "001"; --! Gets shifted out by clk_4x logic. Loaded by strobe_4x_logic
signal s_stretch_trig_in : std_logic := '0'; -- ! stretched version of trigger_i
signal s_stretch_trig_in_sr : std_logic_vector(2 downto 0) := "111"; --! Gets shifted out by clk_4x logic. Loaded by trigger_i
signal s_trigger_out : std_logic := '0'; -- ! trigger shifted to start on strobe_4x_logic
-- Set length of output trigger here ( output length = length of this vector + 1 )
signal s_trigger_out_sr : std_logic_vector(2 downto 0) := ( others => '1'); --! Gets shifted out by clk_4x logic. Loaded by strobe_4x_logic.
BEGIN
-- Copy reset/clk signal straight through
dut_reset_or_clk_o <= reset_or_clk_to_dut_i;
dut_shutter_o <= shutter_to_dut_i;
-- purpose: generates a clock from 4x clock and strobe ( high once every 4 cycles )
-- should produce 11001100... etc. ie. 40MHz clock from 160MHz clock
-- type : combinational
-- inputs : clk_4x_logic_i , strobe_4x_i
-- outputs: s_dut_clk
p_dut_clk_gen: process (clk_4x_logic_i , strobe_4x_logic_i) is
begin -- process p_dut_clk_gen
if rising_edge(clk_4x_logic_i) then
if (strobe_4x_logic_i = '1') then
s_dut_clk <= '1';
s_dut_clk_sr <= "001";
else
s_dut_clk <= s_dut_clk_sr(0);
s_dut_clk_sr <= '0' & s_dut_clk_sr(s_dut_clk_sr'left downto 1);
end if;
end if;
end process p_dut_clk_gen;
-- purpose: re-times a single cycle pulse on trigger on clk_4x_logic onto clk_logic
-- type : combinational
-- inputs : clk_4x_logic_i , strobe_4x_logic_i , trigger_i
-- outputs: s_premask_trigger_to_dut
p_dut_trig_retime: process (clk_4x_logic_i , strobe_4x_logic_i , trigger_i) is
begin -- process p_dut_trig_retime
if rising_edge(clk_4x_logic_i) then
-- Stretch trigger_i pulse to 4 clock cycles on clk4x
if trigger_i = '1' then
s_stretch_trig_in <= '1';
s_stretch_trig_in_sr <= ( others => '1' );
else
s_stretch_trig_in <= s_stretch_trig_in_sr(0);
s_stretch_trig_in_sr <= '0' & s_stretch_trig_in_sr(s_stretch_trig_in_sr'left downto 1);
end if;
--
if (strobe_4x_logic_i = '1') and ( s_stretch_trig_in = '1' ) then
s_trigger_out <= '1';
s_trigger_out_sr <= ( others => '1' );
else
s_trigger_out <= s_trigger_out_sr(0);
s_trigger_out_sr <= '0' & s_trigger_out_sr(s_trigger_out_sr'left downto 1);
end if;
end if;
end process p_dut_trig_retime;
-- purpose: register for internal signals and output signals
-- type : combinational
-- inputs : clk_4x_logic_i , strobe_4x_logic_i , s_veto
-- outputs: busy_o
register_signals: process (clk_4x_logic_i)-- , strobe_4x_logic_i , s_veto)
begin -- process register_signals
if rising_edge(clk_4x_logic_i) then
s_strobe_4x_logic_d1 <= strobe_4x_logic_i;
busy_o <= ((not ignore_shutter_veto_i ) and (not shutter_to_dut_i)) or
((dut_busy_i and DUT_mask_i ) and (not ignore_dut_busy_i) );
dut_clk_o <= s_dut_clk ;
dut_trigger_o <= DUT_mask_i and s_trigger_out;
end if;
end process register_signals;
END ARCHITECTURE rtl;
firmware/hdl/common/DUTInterface_EUDET_rtl.vhd 0 → 100644
View file @ 913f7688
This diff is collapsed.
firmware/hdl/common/DUTInterfaces_rtl.vhd
View file @ 913f7688
This diff is collapsed.
firmware/hdl/common/coincidenceLogic_rtl.vhd
View file @ 913f7688
......@@ -17,8 +17,14 @@ USE ieee.std_logic_1164.all;
Library UNISIM;
use UNISIM.vcomponents.all;
--! @brief Takes a set of input pulses and produces an output pulse based on trigger pattern
--
--! @brief Takes a set of input pulses and produces an output pulse based on trigger
--! pattern. Defaults to "OR" of all inputs.
--!
--! @details If triggers_i matches a pattern in triggerPattern then trigger_o
--! goes high for one clock cycle of logicClk_o. Load a new pattern by taking loadPattern_i high for one cycle of configClk_i
--!
--! @author David Cussans
--! @date 2014
-------------------------------------------------------------------------------
entity coincidenceLogic is
......
firmware/hdl/common/synchronizeRegisters_rtl.vhd
View file @ 913f7688
......@@ -9,17 +9,24 @@
------------------------------------------------------------------------------- --
-- VHDL Architecture worklib.synchronizeRegisters.rtl
--
--! @brief Regularly transfers the input to the output.\n
--! One clock for input , one clock for output\n
--! Can't just put entire bus through a couple of register stages,\n
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.ipbus_reg_types.all;
--! @brief Regularly transfers the input to the output.
--! One clock for input , one clock for output
--! Can't just put entire bus through a couple of register stages,
--! Since this will just swap meta-stability issues for race issues.
--
--!
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--!
--! @date 24/Nov/12
--
--!
--! @version v0.1
--
--!
--! @details A six stage "ring oscillator" is used to generate two strobes.
--! One reads data into a register. The other registers the data to the output
--! Three stages are clocked on clk_write_i , three stages are clocked on clk_read_i
......@@ -29,50 +36,33 @@
--!
--! Based on registerCounters
--!
--! <b>Dependencies:</b>\n
--!
--! <b>References:</b>\n
--!
--! <b>Modified by:</b>\n
--! Author:
--! David Cussans, 26/2/14 - Added registers to output to aid timing closure.
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
-------------------------------------------------------------------------------
--! @todo <next thing to do> \n
--! <another thing to do> \n
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--use work.fmcTLU.all;
use work.ipbus_reg_types.all;
entity synchronizeRegisters is
generic (
--g_DATA_WIDTH : positive := 15;
g_NUM_REGISTERS : positive := 1); -- ! Width of counter
g_NUM_REGISTERS : positive := 1); --! Number of registers to synchronize
port (
clk_input_i : in std_logic; -- ! clock for input
data_i : in ipb_reg_v(g_NUM_REGISTERS-1 downto 0); -- ! array of registers to transfer to output
data_o : out ipb_reg_v(g_NUM_REGISTERS-1 downto 0); -- ! Data now in clk_output_i domain
clk_output_i : in std_logic); -- ! clock for output
clk_input_i : in std_logic; --! clock for input
data_i : in ipb_reg_v(g_NUM_REGISTERS-1 downto 0); --! array of registers to transfer to output
data_o : out ipb_reg_v(g_NUM_REGISTERS-1 downto 0); --! Data now in clk_output_i domain
clk_output_i : in std_logic); --! clock for output
end synchronizeRegisters;
architecture rtl of synchronizeRegisters is
signal s_ring_d0 , s_ring_d1 , s_ring_d2 , s_ring_d3 , s_ring_d4, s_ring_d5: std_logic := '0'; -- stages in "ring oscillator" used to generate strobes
signal s_registered_data : ipb_reg_v(data_i'range) := ( others => ( others => '0')); -- ! Register to store data between clock domains
signal s_registered_data : ipb_reg_v(data_i'range) := ( others => ( others => '0')); --! Register to store data between clock domains
signal s_read_strobe , s_write_strobe : std_logic := '0'; -- ! Strobes high to register data from input and to output
signal s_read_strobe , s_write_strobe : std_logic := '0'; --! Strobes high to register data from input and to output
begin -- rtl
-- purpose: part of "ring oscillator" transfering strobe between clock domains
--! purpose: part of "ring oscillator" transfering strobe between clock domains
-- type : combinational
-- inputs : clk_read_i
-- outputs:
......@@ -89,10 +79,9 @@ begin -- rtl
end if;
end process p_gen_capture_strobe;
s_read_strobe <= s_ring_d1 xor s_ring_d2; --! Generate a strobe with
--width one clk_read_i
s_read_strobe <= s_ring_d1 xor s_ring_d2; --! Generate a strobe (with width one clk_read_i) that captures data at input
-- purpose: part of "ring oscillator" transfering strobe between clock domains
--! purpose: part of "ring oscillator" transfering strobe between clock domains
-- type : combinational
-- inputs : clk_output_i
-- outputs:
......@@ -109,6 +98,6 @@ begin -- rtl
end if;
end process p_gen_output_strobe;
s_write_strobe <= s_ring_d4 xor s_ring_d5; --! Generate a strobe
--
s_write_strobe <= s_ring_d4 xor s_ring_d5; --! Generate the strobe that causes data to be written to output
end rtl;
firmware/hdl/common/triggerLogic_rtl.vhd
View file @ 913f7688
......@@ -35,7 +35,7 @@ USE work.fmcTLU.all;
--! \li 0x00000001 RO - Number of possible triggers since last reset (i.e. pre-veto triggers)
--! \li 0x00000010 RW - Interval between internal triggers in ticks of logic_strobe_i
--! \li 0x00000011 RW - trigger pattern - value that gets loaded into CFGLUT5
--! \li 0x00000100 RW - bit-0 - internal trigger veto. Set to halt vetos.
--! \li 0x00000100 RW - bit-0 - internal trigger veto. Set high to halt triggers.
--! \li 0x00000101 RO - state of external veto
--! \li 0x00000110 RW - stretch of pulses. Additional width = 0-31 clock cycles.
--! \li 0x00000111 RW - delay of pulses. 0-31 clock cycles.
......
firmware/scripts/aida_mini_tlu_addr_map.txt
View file @ 913f7688
......@@ -6,9 +6,9 @@ FirmwareId 0x00000000 0xffffffff 1 0
DUTMaskW 0x00000020 0xffffffff 0 1
IgnoreDUTBusyW 0x00000021 0xffffffff 0 1
IgnoreShutterVetoW 0x00000022 0xffffffff 0 1
DUTMaskR 0x00000024 0xffffffff 1 0
IgnoreDUTBusyR 0x00000025 0xffffffff 1 0
IgnoreShutterVetoR 0x00000026 0xffffffff 1 0
DUTMaskR 0x00000028 0xffffffff 1 0
IgnoreDUTBusyR 0x00000029 0xffffffff 1 0
IgnoreShutterVetoR 0x0000002A 0xffffffff 1 0
*
* trigger inputs = 0x040
SerdesRstW 0x00000040 0xffffffff 0 1
......
firmware/scripts/test_aida_tlu_internal_triggers_v2.py
View file @ 913f7688
......@@ -17,7 +17,8 @@ bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
board = ChipsBusUdp(bAddrTab,"192.168.200.32",50001)
# Check the bus for I2C devices
executeI2C = True
#executeI2C = True
executeI2C = False
if executeI2C:
boardi2c = FmcTluI2c(board)
boardId = boardi2c.get_serial_number()
......@@ -35,7 +36,7 @@ Enable_Record_Data = board.read("Enable_Record_Data")
print "Event recording flags read back as = ",Enable_Record_Data
print "Enabling all DUTs "
board.write("DUTMaskW",3)
board.write("DUTMaskW",7)
DUTMask = board.read("DUTMaskR")
print "DUT mask read back as " , DUTMask
......
firmware/simulation_src/fmc-tlu_v0-1_test-bench.vhd
View file @ 913f7688
......@@ -22,7 +22,7 @@ END fmctlu_v0_1_testbench;
ARCHITECTURE behavior OF fmctlu_v0_1_testbench IS
constant c_NUM_DUTS : positive := 2;
constant c_NUM_DUTS : positive := 3;
--Inputs
......
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