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AIDA-2020 TLU
Commit e597fd4b authored by David Cussans's avatar David Cussans
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Tidying up simulation set-up scripts

parent f6809ab7
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Showing with 2 additions and 62 deletions
firmware/simulation/scripts/add_files.tcl
View file @ e597fd4b
......@@ -73,6 +73,8 @@ project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/i2c_
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/eventFormatter_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/eventBuffer_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/DUTInterfaces_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/DUTInterface_AIDA_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/DUTInterface_EUDET_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/coincidenceLogic_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/stretchPulse_rtl.vhd
project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/synchronizeRegisters_rtl.vhd
......
firmware/simulation/scripts/addfiles_sim.tcl.sav deleted 100644 → 0
View file @ f6809ab7
# Horrible hacky TCL script to build ISE project from hierarchy of source lists
proc dofile {f} {
set fp [open $f r]
set files [read $fp]
close $fp
foreach f_line [split $files "\n"] {
if {$f_line == "" || [string index $f_line 0] == "#"} {
continue
}
set l [split $f_line]
set cmd [lindex $l 0]
set arg1 [lindex $l 1]
set arg2 [lindex $l 2]
set f_list [glob $::env(REPOS_FW_DIR)/$arg1]
foreach f_loc $f_list {
set f_loc_s [exec basename $f_loc]
if {$cmd == "hdl"} {
addfile $f_loc $arg2
} elseif {$cmd == "core"} {
addcore $f_loc $arg2
} elseif {$cmd == "include"} {
dofile $f_loc
}
}
}
}
proc addfile {f lib} {
project addfile $f
}
proc addcore {f lib} {
addfile [file rootname $f].vhd $lib
}
dofile $::env(REPOS_BUILD_DIR)/file_list
firmware/simulation/scripts/setup_project.tcl deleted 100644 → 0
View file @ f6809ab7
# Creates a new Questa project for ipbus demo
#
# You will want to amend the path to compiled Xilinx libraries to suit
# your system.
#
# Dave Newbold, April 2011
#
# $Id$
set xlib_vhdl $::env(ISE_VHDL_MTI)
set xlib_vlog $::env(ISE_VLOG_MTI)
project new ./ ipbus_sim_demo
vmap unisim $xlib_vhdl/unisim
vmap unimacro $xlib_vhdl/unimacro
vmap secureip $xlib_vlog/secureip
vmap xilinxcorelib $xlib_vhdl/xilinxcorelib
source $::env(REPOS_FW_DIR)/ipbus/firmware/sim/scripts/addfiles_sim.tcl
project calculateorder
project close
quit
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